OpenCores
URL https://opencores.org/ocsvn/wb_z80/wb_z80/trunk

Subversion Repositories wb_z80

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 11 to Rev 12
    ↔ Reverse comparison
  •

Rev 11 → Rev 12

/trunk/rtl/inst_exec.v
71,10 → 71,10
//
//-------1---------2---------3--------CVS Log -----------------------7---------8---------9--------0
//
// $Id: inst_exec.v,v 1.2 2004-04-18 18:50:08 bporcella Exp $
// $Id: inst_exec.v,v 1.3 2004-04-19 05:09:11 bporcella Exp $
//
// $Date: 2004-04-18 18:50:08 $
// $Revision: 1.2 $
// $Date: 2004-04-19 05:09:11 $
// $Revision: 1.3 $
// $Author: bporcella $
// $Locker: $
// $State: Exp $
81,6 → 81,9
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2004/04/18 18:50:08 bporcella
// fixed some lint problems --
//
// Revision 1.1.1.1 2004/04/13 23:49:54 bporcella
// import first files
//
128,10 → 131,10
wire [7:0] src_pqr; // arithmetic sources gven by ir2[2:0]
wire [7:0] src_hr ;
wire [7:0] src_lr ;
wire [7:0] alu_out; // {CF. 8bit_result}
wire alu_cry;
//wire [7:0] alu_out; // {CF. 8bit_result}
//wire alu_cry;
 
wire c_in0, c_out7, c_in8, c_out11, cout15;
//wire c_in0, c_out7, c_in8, c_out11, cout15;
wire [15:0] src_a, src_b;
wire [15:0] add16;
wire sf, zf, f5f, hf, f3f, pvf, nf, cf;
142,7 → 145,7
wire [7:0] add_8bit;
 
wire [15:0] src_dblhr ;
wire src_cb_r20 ;
//wire src_cb_r20 ;
wire [7:0] src_pqr20 ;
wire [7:0] src_pqr53 ;
wire [15:0] src_dbl ;
226,8 → 229,8
//assign src_cb_r20 = (ddcb_grp | fdcb_grp) ? nn[7:0] :
// cb_grp ? src_pqr20 :
// ar ;
 
 
assign br_eq0 = ~|br; // for first cut do this quick and dirty.
assign cr_eq0 = ~|cr; // if this becomes a critical path - make these registers.
assign src_pqr20 = {8{ir2[2:0]==REG8_B }} & br |
{8{ir2[2:0]==REG8_C }} & cr |
{8{ir2[2:0]==REG8_D }} & dr |
1105,7 → 1108,7
// pretty nomal stuff here
//CB_BIT = 4'b01_01, // these must be compaired with ir2[9:6]
// which alu? -- done from alu8
//ED_NEG = 5'b01___100, // compair with {ir2[7:6],ir2[2:0]} all A<= -A
//ED_NEG = 5'b01___100, // compair with {ir2[7:6],ir2[2:0]} all A<= -A
 
// rmw 8 types these handled by standard INC and DEC logic done.
//INCs6HL7 = 'h34,// INC (HL) ; 34
1164,7 → 1167,7
( upd_fr_cbsh ) |
(CB_BIT == ir2[9:6]) |
( ed_blk_cp ) |
(ED_INsREG_6C7 == {ir2[7:6],ir2[2:0]}) |
(ED_INsREG_6C7 == {ir2[7:6],ir2[2:0]}) |
(CCF == ir2 ) |
(CPL == ir2 ) |
(DAA == ir2 ) |
1182,12 → 1185,12
begin
if ( upd_fr_alu8 ) fr <= alu8_fr; // assembled above with 8 bit ALU
if ( upd_fr_add16) fr <= {sf, zf, add16[13], c_16out11, add16[11], pvf, 1'b0, c_16out15};
if ( upd_fr_edadd16) fr <= {add16[15], ~|add16, add16[13], c_out11,
if ( upd_fr_edadd16) fr <= {add16[15], ~|add16, add16[13], c_16out11,
add16[11], add16_ofl, ~ir2[3], c_16out15};
if ( upd_fr_sh ) fr <= {sf, zf, sh_alu[5], 1'b0, sh_alu[3], pvf, 1'b0, sh_cry};
if ( upd_fr_cbsh ) fr <= {sh_alu[7], ~|sh_alu, sh_alu[5], 1'b0,
sh_alu[3], ~^sh_alu, 1'b0, sh_cry};
if (CB_BIT == ir2[9:6]) fr <={bit_alu[7], ~|bit_alu, bit_alu[5], 1'b1, //no idea why hf<=1
if (CB_BIT == ir2[9:6]) fr <={bit_alu[7], ~|bit_alu, bit_alu[5], 1'b1, //no idea why hf<=1
bit_alu[3], ~|bit_alu, 1'b0 , cf };// pvf == zf ???
if ( ed_blk_cp ) fr <= {alu8_out[7], ~|alu8_out, alu8_out[5], alu8_hcry,//std a-n stuff
alu8_out[3], alu8_out[7], 1'b1, cf }; //cept nf and cf
1202,7 → 1205,7
ar[3], ~^{ar[7:4],nn[3:0]}, 1'b0 , cf };
if (ED_RLD == ir2) fr <= { sf, ~|{ar[7:4],nn[7:4]}, ar[5], 1'b0,
ar[3], ~^{ar[7:4],nn[7:4]}, 1'b0 , cf };
if (ED_LDsA_I == ir2) fr <= { ir2[7], ~|ir2, ir2[5], 1'b0, ir2[3], iff2, 1'b0, cf }; // iff2 ?
if (ED_LDsA_I == ir2) fr <= { ir2[7], ~|ir2, ir2[5], 1'b0, ir2[3], iff2, 1'b0, cf }; // iff2 ?
end
// in the case of blk_cp the update above is executed 2nd - and so these are don't cares.
1214,10 → 1217,8
//----------------------- intr -----------------------------------------------------------
always @(posedge clk)
begin
if (( ED_LDsI_A == ir2) & exec_ir2) intr <= ar;
end
always @(posedge clk or posedge rst)
if (rst) intr <= 8'h0;
else if (( ED_LDsI_A == ir2) & exec_ir2) intr <= ar;
 
endmodule
/trunk/rtl/memstate2.v
109,10 → 109,10
// complete before starting the ir1 operation
//-------1---------2---------3--------CVS Log -----------------------7---------8---------9--------0
//
// $Id: memstate2.v,v 1.6 2004-04-18 18:50:09 bporcella Exp $
// $Id: memstate2.v,v 1.7 2004-04-19 05:09:11 bporcella Exp $
//
// $Date: 2004-04-18 18:50:09 $
// $Revision: 1.6 $
// $Date: 2004-04-19 05:09:11 $
// $Revision: 1.7 $
// $Author: bporcella $
// $Locker: $
// $State: Exp $
119,6 → 119,9
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.6 2004/04/18 18:50:09 bporcella
// fixed some lint problems --
//
// Revision 1.5 2004/04/17 15:18:02 bporcella
// 4th lint try
// Miha claims reports are now correct
138,7 → 141,7
//
//
//-------1---------2---------3--------Module Name and Port List------7---------8---------9--------0
module memstate2(wb_adr, wb_we, wb_cyc, wb_stb, wb_lock, wb_tga_io, wb_dat_o, add_out,
module memstate2(wb_adr, wb_we, wb_cyc, wb_stb, wb_lock, wb_tga_io, wb_dat_o,
exec_ir2, ir1, ir2, ir1dd, ir1fd, ir2dd, ir2fd, nn, sp,
upd_ar, upd_br, upd_cr, upd_dr, upd_er, upd_hr, upd_lr,upd_fr,
164,7 → 167,7
output wb_lock; // bit set and clear insts should be atomic - could matter sometime
output [1:0] wb_tga_io;
output [7:0] wb_dat_o; // from nn
output [15:0] add_out; // output of adder (may not wb_adr)
//output [15:0] add_out; (may not wb_adr) 4/18/2004?? why?
 
output exec_ir2;
output [9:0] ir1, ir2;
195,9 → 198,9
parameter TAG_IO = 2'b01, // need to review general wb usage to undrstand how best to
TAG_INT = 2'b10; // document this.
// 12na
parameter IPIPE_NOP = 4'b0000,
IPIPE_A2 = 4'b0001,
IPIPE_ENN = 4'b0010,
parameter IPIPE_NOP = 4'b0000, // guess I could define single bits and add them up
IPIPE_A2 = 4'b0001, // would keep from getting lint bitching -- but heck
IPIPE_ENN = 4'b0010, // I'm married -> an expert at ignoring such stuff :-)
IPIPE_ENNA2 = 4'b0011,
IPIPE_EN2 = 4'b0100,
IPIPE_EN2A2 = 4'b0101,
347,18 → 350,18
//-------1---------2---------3--------Wires----------------6---------7---------8---------9--------0
 
 
wire use_sp;
wire use_pc;
wire use_hl;
wire use_de;
wire use_bc;
wire use_flags;
//wire use_sp; // old names probably from first go-around
//wire use_pc;
//wire use_hl;
//wire use_de;
//wire use_bc;
//wire use_flags;
wire cb_mem;
wire br_test8t; // branch test true (8 test field)
wire br_test4t; // branch test true (4 test field)
//wire br_test8t; // branch test true (8 test field)
//wire br_test4t; // branch test true (4 test field)
wire ofos;
wire any_os; // most terms above only valid on mem_exec this includes all stores
//wire ofos;
//wire any_os; // most terms above only valid on mem_exec this includes all stores
wire wb_rdy_nhz;
wire dec_blk_inc;
wire we_next;
390,8 → 393,8
reg wb_we;
reg wb_cyc;
reg wb_stb;
reg wb_lock;
reg wb_tga_io;
//reg wb_lock; Not used (yet -- don't delete)
reg [1:0] wb_tga_io;
 
reg blk_inc_flg;
reg [9:0] ir1, ir2;
1093,8 → 1096,8
 
wire src2 = {16{ inc }} & 16'h0001 |
{16{ dec }} & 16'hffff |
{16{ rel }} & {{8{nn[15]}},nn[15:8]}|
{16{~(rel |inc |dec )}} & 16'h0 ;
{16{ reln }} & {{8{nn[15]}},nn[15:8]}|
{16{~(reln |inc |dec )}} & 16'h0 ;
 
wire adr_alu = src2 + src_mux;
1202,7 → 1205,7
DEC_EDNN1: next_state = {DEC_EDNN2, MEM_NOP, IPIPE_ENN}; // address to nn
DEC_EDNN2:
if (ed_dbl_rd) next_state = {DEC_EDRD1, MEM_OFNN, IPIPE_NOP};
else next_state = {DEC_EDWR, MEM_OSNN, IPIPE_NOP};// OSNN selects data ok?
else next_state = {DEC_EDWR, MEM_OSNN, IPIPE_NOP};// OSNN selects data ok?
DEC_EDRD1: next_state = {DEC_EDRD2, MEM_OFADRP1, IPIPE_ENN}; // 1st byte 2n
DEC_EDRD2: next_state = {DEC_IF2, MEM_IFPP1, IPIPE_ENNA2}; // 2nd byte 2nn
DEC_EDWR: next_state = {DEC_IF1, MEM_OSADRP1, IPIPE_NOP};
1251,9 → 1254,9
// For CALL Use MEM_CALL to transfer pc<=nn, nn<=pc, adr<=sp then MEM_OSSP then IFPP1
// For LDsSP_NN yes update from ir2 decode.
DEC_NN:
if (callnn_true) next_state = {DEC_NNCALL1, MEM_NOP, IPIPE_ENN}; // this gets new adr in nn
// if we store from nn we can't do
// a mem op now
if (callnn_true) next_state = {DEC_NNCALL1, MEM_NOP, IPIPE_ENN};// this gets new adr in nn
//if we store from nn we can't do
// a mem op now
else if (jmpnn_true) next_state = {DEC_NNJMP, MEM_NOP, IPIPE_ENN}; // gotta get nn before we can
// transfer to adr.
1359,8 → 1362,8
// are keyed off exec_ir2 - and always happen immediately. ( exec_ir2 always is
// immediately reset - unless of course a new instruction is transferred and executed.
//
//
//
//
always @(posedge clk or posedge rst)
if (rst) ir2 <= 10'h0;
else if (wb_rdy_nhz & next_pipe_state[2]) ir2 <= ir1;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.