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Rev 11 → Rev 12

/branches/avendor/rtl/io_package.vhd
63,18 → 63,22
 
constant write32_time_out : integer := 6; -- number of clocks to wait
-- on w32, before an error
 
constant read32_time_out : integer := 6; -- number of clocks to wait
-- on r32, before an error
 
constant clk_period : time := 10 ns; -- period of simulation clock
 
constant max_block_size : integer := 128; -- maximum number of read or write
-- locations in a block transfer
 
type cycle_type is ( unknown,
bus_rst,
bus_idle,
rd32, rd16, rd8,
wr32, wr16, wr8,
rmw32, rmw16, rmw8
rd32, rd16, rd8, -- read
wr32, wr16, wr8, -- write
rmw32, rmw16, rmw8, -- read modify write
bkr32, bkr16, brw8, -- block read
bkw32, bkw16, bkw8 -- block write
);
type bus_cycle is
119,6 → 123,9
'Z'
);
 
type block_type is array ( max_block_size downto 0 ) of std_logic_vector( 31 downto 0 );
 
 
-- ----------------------------------------------------------------------
-- to_nibble
-- ----------------------------------------------------------------------
205,9 → 212,34
);
 
 
-- ----------------------------------------------------------------------
-- bkw_32
-- ----------------------------------------------------------------------
-- usage bkw_32 ( address_array, write_data_array, array_size , bus_record )
-- write each data to the coresponding address of the array
 
procedure bkw_32 (
constant address_data : in block_type;
constant write_data : in block_type;
constant array_size : in integer;
signal bus_c : inout bus_cycle
);
 
-- ----------------------------------------------------------------------
-- bkr_32
-- ----------------------------------------------------------------------
-- usage bkr_32 ( address_array, read_data_array, array_size , bus_record )
-- read from each address data to the coresponding address of the array
 
procedure bkr_32 (
constant address_data : in block_type;
variable read_data : out block_type;
constant array_size : in integer;
signal bus_c : inout bus_cycle
) ;
 
 
 
-- -------------------------------------------------------------------------
end io_pack;
-- -------------------------------------------------------------------------
481,6 → 513,104
end procedure rmw_32;
 
 
-- ----------------------------------------------------------------------
-- bkw_32
-- ----------------------------------------------------------------------
-- usage bkw_32 ( address_array, write_data_array, array_size , bus_record )
-- write each data to the coresponding address of the array
 
procedure bkw_32 (
constant address_data : in block_type;
constant write_data : in block_type;
constant array_size : in integer;
signal bus_c : inout bus_cycle
) is
variable bus_write_timer : integer;
 
begin
-- for each element, perform a write 32.
 
for n in 0 to array_size - 1 loop
bus_c.c_type <= bkw32;
bus_c.add_o <= address_data(n);
bus_c.dat_o <= write_data(n);
bus_c.we <= '1'; -- write cycle
bus_c.sel <= ( others => '1'); -- on all four banks
bus_c.cyc <= '1';
bus_c.stb <= '1';
bus_write_timer := 0;
wait until rising_edge( bus_c.clk );
while bus_c.ack = '0' loop
bus_write_timer := bus_write_timer + 1;
wait until rising_edge( bus_c.clk );
exit when bus_write_timer >= write32_time_out;
end loop;
bus_c.c_type <= bus_idle;
bus_c.add_o <= ( others => '0');
bus_c.dat_o <= ( others => '0');
bus_c.we <= '0';
bus_c.sel <= ( others => '0');
bus_c.cyc <= '0';
bus_c.stb <= '0';
end loop;
 
end procedure bkw_32;
 
-- ----------------------------------------------------------------------
-- bkr_32
-- ----------------------------------------------------------------------
-- usage bkr_32 ( address_array, read_data_array, array_size , bus_record )
-- read from each address data to the coresponding address of the array
 
procedure bkr_32 (
constant address_data : in block_type;
variable read_data : out block_type;
constant array_size : in integer;
signal bus_c : inout bus_cycle
) is
variable bus_read_timer : integer;
 
begin
-- for each element, perform a read 32.
 
for n in 0 to array_size - 1 loop
bus_c.c_type <= bkr32;
bus_c.add_o <= address_data(n);
bus_c.we <= '0'; -- read cycle
bus_c.sel <= ( others => '1'); -- on all four banks
bus_c.cyc <= '1';
bus_c.stb <= '1';
bus_read_timer := 0;
wait until rising_edge( bus_c.clk );
while bus_c.ack = '0' loop
bus_read_timer := bus_read_timer + 1;
wait until rising_edge( bus_c.clk );
exit when bus_read_timer >= read32_time_out;
end loop;
 
read_data(n) := bus_c.dat_i;
bus_c.c_type <= bus_idle;
bus_c.add_o <= ( others => '0');
bus_c.dat_o <= ( others => '0');
bus_c.we <= '0';
bus_c.sel <= ( others => '0');
bus_c.cyc <= '0';
bus_c.stb <= '0';
end loop;
 
end procedure bkr_32;
 
 
-- -------------------------------------------------------------------------
end io_pack;
-- -------------------------------------------------------------------------
/branches/avendor/rtl/wb_master.vhd
108,6 → 108,7
 
signal reset_int : std_logic;
 
 
-- --------------------------------------------------------------------
begin
-- --------------------------------------------------------------------
142,7 → 143,14
--
variable slv_32 : std_logic_vector( 31 downto 0);
 
variable bka_test_array : block_type :=
( others => x"0000_0000");
variable bkd_test_array : block_type :=
( others => x"0000_0000");
 
 
 
 
begin
 
-- Wait 100 ns for global reset to finish
154,24 → 162,45
wb_init( bus_c); -- initalise wishbone bus
wb_rst( 2, reset_int, bus_c ); -- reset system for 2 clocks
 
-- set up some address / data pairs
bka_test_array(0) := X"0000_0002";
bkd_test_array(0) := X"5555_0002";
 
wr_32( x"8000_0004", x"5555_5555", bus_c); -- write 32 bits address of 32 bit data
bka_test_array(1) := X"0000_0004";
bkd_test_array(1) := X"55AA_0004";
 
rd_32( x"8000_0004", slv_32, bus_c); -- read 32 bits address of 32 bit data
report to_hex( slv_32);
bka_test_array(2) := X"0000_0006";
bkd_test_array(2) := X"AAAA_0006";
 
clock_wait( 2, bus_c );
 
rmw_32( x"8000_0004", slv_32, x"ABCD_EF01", bus_c );
report to_hex( slv_32);
bkw_32( bka_test_array, bkd_test_array, 3, bus_c);
 
clock_wait( 2, bus_c );
clock_wait( 1, bus_c );
 
rmw_32( x"8000_0004", slv_32, x"01CD_EFAB", bus_c );
report to_hex( slv_32);
bkr_32( bka_test_array, bkd_test_array, 3, bus_c);
 
report to_hex(bkd_test_array(0));
report to_hex(bkd_test_array(1));
report to_hex(bkd_test_array(2));
 
--
--wr_32( x"8000_0004", x"5555_5555", bus_c); -- write 32 bits address of 32 bit data
--
--rd_32( x"8000_0004", slv_32, bus_c); -- read 32 bits address of 32 bit data
--report to_hex( slv_32);
--
--clock_wait( 2, bus_c );
--
--rmw_32( x"8000_0004", slv_32, x"ABCD_EF01", bus_c );
--report to_hex( slv_32);
--
--clock_wait( 2, bus_c );
--
--rmw_32( x"8000_0004", slv_32, x"01CD_EFAB", bus_c );
--report to_hex( slv_32);
--
 
 
clock_wait( 1, bus_c );
wb_rst( 2, reset_int, bus_c ); -- reset system for 2 clocks
 

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