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Rev 110 → Rev 111

/funbase_ip_library/trunk/TUT/ip.hwp.interface/pcie/pcie_to_hibi.comp/2.0/doc/PCIe_to_HIBI_v2.docx Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/funbase_ip_library/trunk/TUT/ip.hwp.interface/pcie/pcie_to_hibi.comp/2.0/doc/fig/PCIe_to_HIBI_v2.mdzip Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/funbase_ip_library/trunk/TUT/ip.hwp.interface/pcie/pcie_to_hibi.comp/2.0/doc/fig/PCIe_to_HIBI_v2.pptx Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/funbase_ip_library/trunk/TUT/ip.hwp.interface/pcie/pcie_to_hibi.comp/2.0/tb/a2_pex_x8_app_if.v
23,7 → 23,6
//*/
module a2_pex_x8_example_chaining_pipen1b (
// inputs:
free_100MHz,
local_rstn,
pcie_rstn,
pclk_in,
30,6 → 29,7
phystatus_ext,
pipe_mode,
pld_clk,
reconfig_clk,
refclk,
rx_in0,
rx_in1,
86,7 → 86,7
clk500_out,
core_clk_out,
lane_width_code,
pcie_reconfig_busy,
pcie_reconfig_rstn,
phy_sel_code,
powerdown_ext,
rate_ext,
149,7 → 149,7
output clk500_out;
output core_clk_out;
output [ 3: 0] lane_width_code;
output pcie_reconfig_busy;
output pcie_reconfig_rstn;
output [ 3: 0] phy_sel_code;
output [ 1: 0] powerdown_ext;
output rate_ext;
205,7 → 205,6
output txelecidle5_ext;
output txelecidle6_ext;
output txelecidle7_ext;
input free_100MHz;
input local_rstn;
input pcie_rstn;
input pclk_in;
212,7 → 211,7
input phystatus_ext;
input pipe_mode;
input pld_clk;
 
input reconfig_clk;
input refclk;
input rx_in0;
input rx_in1;
286,7 → 285,6
wire cpl_pending_icm;
wire [ 4: 0] dl_ltssm;
wire [127: 0] err_desc;
wire fixedclk_serdes;
wire [ 23: 0] gnd_cfg_tcvcmap_icm;
wire gnd_msi_stream_ready0;
wire [ 9: 0] gnd_pm_data;
307,9 → 305,7
wire open_msi_stream_valid0;
wire [ 9: 0] open_pm_data;
wire open_rx_st_err0;
wire otb0;
wire otb1;
wire pcie_reconfig_busy;
wire pcie_reconfig_rstn;
wire [ 4: 0] pex_msi_num_icm;
wire [ 3: 0] phy_sel_code;
wire pme_to_sr;
316,8 → 312,6
wire [ 1: 0] powerdown_ext;
wire rate_ext;
wire rc_pll_locked;
wire reconfig_clk;
wire reconfig_clk_locked;
wire [ 3: 0] ref_clk_sel_code;
wire rx_mask0;
wire [ 7: 0] rx_st_bardec0;
340,7 → 334,7
wire rxpolarity7_ext;
wire srstn;
wire [ 8: 0] test_out_icm;
wire [ 8: 0] test_out_int;
wire [ 63: 0] test_out_int;
wire [ 3: 0] tl_cfg_add;
wire [ 31: 0] tl_cfg_ctl;
wire tl_cfg_ctl_wr;
401,11 → 395,9
assign ref_clk_sel_code = 0;
assign lane_width_code = 3;
assign phy_sel_code = 6;
assign otb0 = 1'b0;
assign otb1 = 1'b1;
assign gnd_pm_data = 0;
assign ko_cpl_spc_vc0[7 : 0] = 8'd4;
assign ko_cpl_spc_vc0[19 : 8] = 12'd16;
assign ko_cpl_spc_vc0[7 : 0] = 8'd28;
assign ko_cpl_spc_vc0[19 : 8] = 12'd112;
assign gnd_cfg_tcvcmap_icm = 0;
assign tx_st_sop0 = tx_stream_data0[73];
assign tx_st_err0 = tx_stream_data0[74];
414,8 → 406,8
assign tx_st_data0 = {tx_stream_data0_1[63 : 0],tx_stream_data0[63 : 0]};
assign tx_st_eop0 = tx_stream_data0_1[72];
assign tx_st_empty0 = tx_stream_data0[72];
assign test_out_icm = test_out_int;
assign pcie_reconfig_busy = 1'b1;
assign test_out_icm = {lane_act,dl_ltssm};
assign pcie_reconfig_rstn = 1'b1;
assign gnd_tx_stream_mask0 = 1'b0;
assign gnd_msi_stream_ready0 = 1'b0;
a2_pex_x8_plus ep_plus
431,7 → 423,6
.core_clk_out (core_clk_out),
.cpl_err (cpl_err_icm),
.cpl_pending (cpl_pending_icm),
.fixedclk_serdes (fixedclk_serdes),
.lane_act (lane_act),
.lmi_ack (lmi_ack),
.lmi_addr (lmi_addr),
456,7 → 447,6
.rate_ext (rate_ext),
.rc_pll_locked (rc_pll_locked),
.reconfig_clk (reconfig_clk),
.reconfig_clk_locked (reconfig_clk_locked),
.refclk (refclk),
.rx_in0 (rx_in0),
.rx_in1 (rx_in1),
585,15 → 575,6
);
 
 
altpcierd_reconfig_clk_pll reconfig_pll
(
.c0 (reconfig_clk),
.c1 (fixedclk_serdes),
.inclk0 (free_100MHz),
.locked (reconfig_clk_locked)
);
 
 
altpcierd_tl_cfg_sample cfgbus
(
.cfg_busdev (cfg_busdev_icm),
631,7 → 612,6
.rstn (srstn)
);
 
pcie_to_hibi_test_app
#( .HIBI_DATA_WIDTH(32),
.HIBI_ADDR_SPACE_WIDTH(11),
714,59 → 694,59
.lmi_ack_in(lmi_ack),
.lmi_addr_out(lmi_addr),
.lmi_data_out(lmi_din) );
// altpcierd_example_app_chaining app
// (
// .aer_msi_num (open_aer_msi_num),
// .app_int_ack (app_int_ack_icm),
// .app_int_sts (app_int_sts_icm),
// .app_msi_ack (app_msi_ack),
// .app_msi_num (app_msi_num),
// .app_msi_req (app_msi_req),
// .app_msi_tc (app_msi_tc),
// .cfg_busdev (cfg_busdev_icm),
// .cfg_devcsr (cfg_devcsr_icm),
// .cfg_linkcsr (cfg_linkcsr_icm),
// .cfg_msicsr (cfg_msicsr),
// .cfg_prmcsr (cfg_prmcsr_icm),
// .cfg_tcvcmap (gnd_cfg_tcvcmap_icm),
// .clk_in (pld_clk),
// .cpl_err (cpl_err_in),
// .cpl_pending (cpl_pending_icm),
// .err_desc (err_desc),
// .ko_cpl_spc_vc0 (ko_cpl_spc_vc0),
// .msi_stream_data0 (open_msi_stream_data0),
// .msi_stream_ready0 (gnd_msi_stream_ready0),
// .msi_stream_valid0 (open_msi_stream_valid0),
// .pex_msi_num (pex_msi_num_icm),
// .pm_data (open_pm_data),
// .rstn (srstn),
// .rx_stream_data0_0 (rx_stream_data0),
// .rx_stream_data0_1 (rx_stream_data0_1),
// .rx_stream_mask0 (rx_mask0),
// .rx_stream_ready0 (rx_stream_ready0),
// .rx_stream_valid0 (rx_stream_valid0),
// .test_sim (test_in[0]),
// .tx_stream_cred0 (tx_stream_cred0),
// .tx_stream_data0_0 (tx_stream_data0),
// .tx_stream_data0_1 (tx_stream_data0_1),
// .tx_stream_fifo_empty0 (tx_fifo_empty0),
// .tx_stream_mask0 (gnd_tx_stream_mask0),
// .tx_stream_ready0 (tx_stream_ready0),
// .tx_stream_valid0 (tx_stream_valid0)
// );
//
// defparam app.AVALON_WADDR = 12,
// app.CHECK_BUS_MASTER_ENA = 1,
// app.CHECK_RX_BUFFER_CPL = 1,
// app.CLK_250_APP = 0,
// app.ECRC_FORWARD_CHECK = 0,
// app.ECRC_FORWARD_GENER = 0,
// app.MAX_NUMTAG = 32,
// app.MAX_PAYLOAD_SIZE_BYTE = 256,
// app.TL_SELECTION = 7,
// app.TXCRED_WIDTH = 36;
/* altpcierd_example_app_chaining app
(
.aer_msi_num (open_aer_msi_num),
.app_int_ack (app_int_ack_icm),
.app_int_sts (app_int_sts_icm),
.app_msi_ack (app_msi_ack),
.app_msi_num (app_msi_num),
.app_msi_req (app_msi_req),
.app_msi_tc (app_msi_tc),
.cfg_busdev (cfg_busdev_icm),
.cfg_devcsr (cfg_devcsr_icm),
.cfg_linkcsr (cfg_linkcsr_icm),
.cfg_msicsr (cfg_msicsr),
.cfg_prmcsr (cfg_prmcsr_icm),
.cfg_tcvcmap (gnd_cfg_tcvcmap_icm),
.clk_in (pld_clk),
.cpl_err (cpl_err_in),
.cpl_pending (cpl_pending_icm),
.err_desc (err_desc),
.ko_cpl_spc_vc0 (ko_cpl_spc_vc0),
.msi_stream_data0 (open_msi_stream_data0),
.msi_stream_ready0 (gnd_msi_stream_ready0),
.msi_stream_valid0 (open_msi_stream_valid0),
.pex_msi_num (pex_msi_num_icm),
.pm_data (open_pm_data),
.rstn (srstn),
.rx_stream_data0_0 (rx_stream_data0),
.rx_stream_data0_1 (rx_stream_data0_1),
.rx_stream_mask0 (rx_mask0),
.rx_stream_ready0 (rx_stream_ready0),
.rx_stream_valid0 (rx_stream_valid0),
.test_sim (test_in[0]),
.tx_stream_cred0 (tx_stream_cred0),
.tx_stream_data0_0 (tx_stream_data0),
.tx_stream_data0_1 (tx_stream_data0_1),
.tx_stream_fifo_empty0 (tx_fifo_empty0),
.tx_stream_mask0 (gnd_tx_stream_mask0),
.tx_stream_ready0 (tx_stream_ready0),
.tx_stream_valid0 (tx_stream_valid0)
);
 
defparam app.AVALON_WADDR = 12,
app.CHECK_BUS_MASTER_ENA = 1,
app.CHECK_RX_BUFFER_CPL = 1,
app.CLK_250_APP = 0,
app.ECRC_FORWARD_CHECK = 0,
app.ECRC_FORWARD_GENER = 0,
app.MAX_NUMTAG = 64,
app.MAX_PAYLOAD_SIZE_BYTE = 256,
app.TL_SELECTION = 7,
app.TXCRED_WIDTH = 36;*/
 
 
endmodule
 
/funbase_ip_library/trunk/TUT/ip.hwp.interface/pcie/pcie_to_hibi.comp/2.0/tb/set_tb.do
24,6 → 24,8
set PHY_TYPE_STRATIXVGX 0
set MSIM_AE ""
set NOIMMEDCA ""
set QUIET_COMP -nologo
#-quiet
 
alias comp_alt {
# Using non-OEM Version, compile all of the libraries
35,7 → 37,12
vlib altera_mf_ver
vmap altera_mf_ver altera_mf_ver
vlog -work altera_mf_ver $QUARTUS_ROOTDIR/eda/sim_lib/altera_mf.v
vlib altera_mfr
vmap altera_mf altera_mf
vcom -work altera_mf $QUARTUS_ROOTDIR/eda/sim_lib/altera_mf_components.vhd
vcom -work altera_mf $QUARTUS_ROOTDIR/eda/sim_lib/altera_mf.vhd
vlib sgate_ver
vmap sgate_ver sgate_ver
vlog -work sgate_ver $QUARTUS_ROOTDIR/eda/sim_lib/sgate.v
116,6 → 123,7
}
}
 
 
# Create the work library
vlib work
 
229,12 → 237,50
run 140us
}
 
proc comp_list {comp_dir} {
set simlist_file [open $comp_dir/sim_filelist r]
if { [ file exists $comp_dir/incdir_list ] } {
set incdirlist_file [open $comp_dir/incdir_list r]
while {[gets $incdirlist_file temp_str] >= 0} {
append incdirlist "+$comp_dir/$temp_str"
}
} else {
set incdirlist ""
}
while {[gets $simlist_file vfile] >= 0} {
if { [ regexp {\.v$} $vfile ] || [ regexp {\.vo$} $vfile ] } {
regexp {.*/} $vfile inc_dir
vlog -reportprogress 300 +incdir+$comp_dir/$inc_dir$incdirlist -work work $comp_dir/$vfile
} else {
vcom -work work -check_synthesis -error 1400 $comp_dir/$vfile
}
}
close $simlist_file
}
 
 
alias comp_p2h {
vcom -work work -check_synthesis -error 1400 ../hdl/*.vhd
vcom -work work -check_synthesis -error 1400 ../tb/pcie_to_hibi_test_app.vhd
vlog -reportprogress 300 -work work ../tb/a2_pex_x8_app_if.v
vcom -work work -check_synthesis -error 1400 ../../../../../ip.hwp.support/txt_util/1.0/hdl/*.vhd $QUIET_COMP
vcom -work work -check_synthesis -error 1400 ../../../../../ip.hwp.storage/onchip_mem/alt_mem_dc_dw.comp/1.0/hdl/*.vhd $QUIET_COMP
vcom -work work -check_synthesis -error 1400 ../../../../../ip.hwp.storage/onchip_mem/alt_mem_sc.comp/1.0/hdl/*.vhd $QUIET_COMP
vcom -work work -check_synthesis -error 1400 ../../../../../ip.hwp.storage/onchip_fifo/alt_fifo_dc_dw.comp/1.0/hdl/*.vhd $QUIET_COMP
vcom -work work -check_synthesis -error 1400 ../../../../../ip.hwp.storage/onchip_fifo/alt_fifo_sc.comp/1.0/hdl/*.vhd $QUIET_COMP
comp_list ./
vcom -work work -check_synthesis -error 1400 ../tb/hibiv3_seg_r3.vhd $QUIET_COMP
vcom -work work -check_synthesis -error 1400 ../tb/pcie_to_hibi_test_app.vhd $QUIET_COMP
vlog -reportprogress 300 -work work ../tb/a2_pex_x8_app_if.v $QUIET_COMP
}
 
alias comp {
comp_alt
comp_list ../../../../../ip.hwp.communication/hibi/hibi_segment_small/3.0/tb
comp_list ../../../../../ip.hwp.storage/ddrx/alt_ddr2_agx2.comp/2.0/tb
comp_list ../../../../../ip.hwp.storage/ddrx/hibi_mem_dma.comp/2.0/tb
comp_list ../../../../../ip.hwp.interface/pcie/alt_pcie_a2gx.comp/1.0/tb
comp_p2h
}
 
alias comp_sim {
comp_p2h
simulate
244,3 → 290,11
comp_p2h
simulate_adv
}
 
echo "--------------------------------------------------------------------------------------------------------------"
echo " command 'comp' compiles all the necessary files for running the testbench"
echo " - this command has to be run only once"
echo ""
echo " command 'comp_sim' compiles only the pcie_to_hibi and starts the simulation"
echo " - use this command each time you have made changes to the pcie_to_hibi and want to verify it's functionality"
echo "--------------------------------------------------------------------------------------------------------------"
/funbase_ip_library/trunk/TUT/ip.hwp.interface/pcie/pcie_to_hibi.comp/2.0/tb/sim_filelist
0,0 → 1,10
../../../../../ip.hwp.support/txt_util/1.0/hdl/*.vhd
../hdl/buf_ptr_ctrl.vhd
../hdl/req_ctrl.vhd
../hdl/pkt_buf.vhd
../hdl/pcie_tx.vhd
../hdl/pcie_rx.vhd
../hdl/multi_mutex.vhd
../hdl/pcie_dma.vhd
../hdl/hibi_if.vhd
../hdl/pcie_to_hibi.vhd
/funbase_ip_library/trunk/TUT/ip.hwp.interface/pcie/pcie_to_hibi.comp/2.0/tb/hibiv3_seg_r3.vhd
447,133 → 447,133
end generate wrappers;
 
 
bridge_needed : if seg > 0 generate
-- bridge_needed : if seg > 0 generate
--
-- i_bridge : entity work.hibi_bridge
-- generic map (
-- a_id_g =>
-- id_a(seg-1, n_segments_g, wrappers_per_segment_c),
-- a_addr_g => bridge_a_addr_base_c(seg-1),
-- a_inv_addr_en_g => bridge_a_inv_addr_c(seg-1),
-- a_id_width_g => id_width_g,
-- a_addr_width_g => addr_width_g,
-- a_data_width_g => data_width_g+separate_addr_g*addr_width_g,
-- a_separate_addr_g => separate_addr_g,
-- a_comm_width_g => comm_width_g,
-- a_counter_width_g => counter_width_g,
-- a_rx_fifo_depth_g => rx_fifo_depth_g,
-- a_tx_fifo_depth_g => tx_fifo_depth_g,
-- a_rx_msg_fifo_depth_g => rx_msg_fifo_depth_g,
-- a_tx_msg_fifo_depth_g => tx_msg_fifo_depth_g,
-- a_arb_type_g => arb_type_g,
-- a_fifo_sel_g => fifo_sel_g,
--
-- a_debug_width_g => debug_width_g,
-- a_prior_g =>
-- priority_a(seg-1, n_segments_g, wrappers_per_segment_c),
-- a_max_send_g => max_send_g,
-- a_n_agents_g =>
-- n_agents_in_segment(seg-1, n_segments_g, wrappers_per_segment_c),
-- a_n_cfg_pages_g => n_cfg_pages_g,
-- a_n_time_slots_g => n_time_slots_g,
-- a_n_extra_params_g => n_extra_params_g,
-- a_cfg_re_g => cfg_re_g,
-- a_cfg_we_g => cfg_we_g,
--
-- b_id_g =>
-- id_b(seg, n_segments_g, wrappers_per_segment_c),
-- b_addr_g => bridge_b_addr_base_c(seg-1),
-- b_inv_addr_en_g => bridge_b_inv_addr_c(seg-1),
-- b_id_width_g => id_width_g,
-- b_addr_width_g => addr_width_g,
-- b_data_width_g => data_width_g+separate_addr_g*addr_width_g,
-- b_separate_addr_g => separate_addr_g,
-- b_comm_width_g => comm_width_g,
-- b_counter_width_g => counter_width_g,
-- b_rx_fifo_depth_g => rx_fifo_depth_g,
-- b_tx_fifo_depth_g => tx_fifo_depth_g,
-- b_rx_msg_fifo_depth_g => rx_msg_fifo_depth_g,
-- b_tx_msg_fifo_depth_g => tx_msg_fifo_depth_g,
-- b_arb_type_g => arb_type_g,
-- b_fifo_sel_g => fifo_sel_g,
--
-- b_debug_width_g => debug_width_g,
-- b_prior_g =>
-- priority_b(seg, n_segments_g, wrappers_per_segment_c),
-- b_max_send_g => max_send_g,
-- b_n_agents_g =>
-- n_agents_in_segment(seg, n_segments_g, wrappers_per_segment_c),
-- b_n_cfg_pages_g => n_cfg_pages_g,
-- b_n_time_slots_g => n_time_slots_g,
-- b_n_extra_params_g => n_extra_params_g,
-- b_cfg_re_g => cfg_re_g,
-- b_cfg_we_g => cfg_we_g,
--
-- a_id_min_g => bridge_a_id_min_c(seg-1),
-- a_id_max_g => bridge_a_id_max_c(seg-1),
-- a_addr_limit_g => bridge_a_addr_limit_c(seg-1),
--
-- b_id_min_g => bridge_b_id_min_c(seg-1),
-- b_id_max_g => bridge_b_id_max_c(seg-1),
-- b_addr_limit_g => bridge_b_addr_limit_c(seg-1)
--
-- )
-- port map (
-- a_clk => clk_noc,
-- a_rst_n => rst_n,
-- b_clk => clk_noc,
-- b_rst_n => rst_n,
-- a_bus_av_in => bus_wra_av(seg-1),
-- a_bus_data_in => bus_wra_data(seg-1),
-- a_bus_comm_in => bus_wra_comm(seg-1),
-- a_bus_full_in => bus_wra_full(seg-1),
-- a_bus_lock_in => bus_wra_lock(seg-1),
-- b_bus_av_in => bus_wra_av(seg),
-- b_bus_data_in => bus_wra_data(seg),
-- b_bus_comm_in => bus_wra_comm(seg),
-- b_bus_full_in => bus_wra_full(seg),
-- b_bus_lock_in => bus_wra_lock(seg),
-- a_bus_av_out => wra_bus_av(seg-1)(wrappers_per_segment_c),
-- a_bus_data_out => wra_bus_data(seg-1)(wrappers_per_segment_c),
-- a_bus_comm_out => wra_bus_comm(seg-1)(wrappers_per_segment_c),
-- a_bus_lock_out => wra_bus_lock(seg-1)(wrappers_per_segment_c),
-- a_bus_full_out => wra_bus_full(seg-1)(wrappers_per_segment_c),
-- b_bus_av_out => wra_bus_av(seg)(wrappers_per_segment_c+1),
-- b_bus_data_out => wra_bus_data(seg)(wrappers_per_segment_c+1),
-- b_bus_comm_out => wra_bus_comm(seg)(wrappers_per_segment_c+1),
-- b_bus_lock_out => wra_bus_lock(seg)(wrappers_per_segment_c+1),
-- b_bus_full_out => wra_bus_full(seg)(wrappers_per_segment_c+1)
-- -- synthesis translate_off
-- ,
-- a_debug_out => open,
-- a_debug_in => (others => '0'),
-- b_debug_out => open,
-- b_debug_in => (others => '0')
-- -- synthesis translate_on
-- );
--
-- -- nullify extra signals
-- nullify_first_seg : if seg = 1 generate
-- -- no b-side on the first segment
-- wra_bus_av(seg-1)(wrappers_per_segment_c+1) <= '0';
-- wra_bus_full(seg-1)(wrappers_per_segment_c+1) <= '0';
-- wra_bus_lock(seg-1)(wrappers_per_segment_c+1) <= '0';
-- wra_bus_comm(seg-1)(wrappers_per_segment_c+1) <= (others => '0');
-- wra_bus_data(seg-1)(wrappers_per_segment_c+1) <= (others => '0');
-- end generate nullify_first_seg;
--
-- nullify_last_seg : if seg = n_segments_g-1 generate
-- -- no a-side here
-- wra_bus_av(seg)(wrappers_per_segment_c) <= '0';
-- wra_bus_full(seg)(wrappers_per_segment_c) <= '0';
-- wra_bus_lock(seg)(wrappers_per_segment_c) <= '0';
-- wra_bus_comm(seg)(wrappers_per_segment_c) <= (others => '0');
-- wra_bus_data(seg)(wrappers_per_segment_c) <= (others => '0');
-- end generate nullify_last_seg;
--
-- end generate bridge_needed;
 
i_bridge : entity work.hibi_bridge
generic map (
a_id_g =>
id_a(seg-1, n_segments_g, wrappers_per_segment_c),
a_addr_g => bridge_a_addr_base_c(seg-1),
a_inv_addr_en_g => bridge_a_inv_addr_c(seg-1),
a_id_width_g => id_width_g,
a_addr_width_g => addr_width_g,
a_data_width_g => data_width_g+separate_addr_g*addr_width_g,
a_separate_addr_g => separate_addr_g,
a_comm_width_g => comm_width_g,
a_counter_width_g => counter_width_g,
a_rx_fifo_depth_g => rx_fifo_depth_g,
a_tx_fifo_depth_g => tx_fifo_depth_g,
a_rx_msg_fifo_depth_g => rx_msg_fifo_depth_g,
a_tx_msg_fifo_depth_g => tx_msg_fifo_depth_g,
a_arb_type_g => arb_type_g,
a_fifo_sel_g => fifo_sel_g,
 
a_debug_width_g => debug_width_g,
a_prior_g =>
priority_a(seg-1, n_segments_g, wrappers_per_segment_c),
a_max_send_g => max_send_g,
a_n_agents_g =>
n_agents_in_segment(seg-1, n_segments_g, wrappers_per_segment_c),
a_n_cfg_pages_g => n_cfg_pages_g,
a_n_time_slots_g => n_time_slots_g,
a_n_extra_params_g => n_extra_params_g,
a_cfg_re_g => cfg_re_g,
a_cfg_we_g => cfg_we_g,
 
b_id_g =>
id_b(seg, n_segments_g, wrappers_per_segment_c),
b_addr_g => bridge_b_addr_base_c(seg-1),
b_inv_addr_en_g => bridge_b_inv_addr_c(seg-1),
b_id_width_g => id_width_g,
b_addr_width_g => addr_width_g,
b_data_width_g => data_width_g+separate_addr_g*addr_width_g,
b_separate_addr_g => separate_addr_g,
b_comm_width_g => comm_width_g,
b_counter_width_g => counter_width_g,
b_rx_fifo_depth_g => rx_fifo_depth_g,
b_tx_fifo_depth_g => tx_fifo_depth_g,
b_rx_msg_fifo_depth_g => rx_msg_fifo_depth_g,
b_tx_msg_fifo_depth_g => tx_msg_fifo_depth_g,
b_arb_type_g => arb_type_g,
b_fifo_sel_g => fifo_sel_g,
 
b_debug_width_g => debug_width_g,
b_prior_g =>
priority_b(seg, n_segments_g, wrappers_per_segment_c),
b_max_send_g => max_send_g,
b_n_agents_g =>
n_agents_in_segment(seg, n_segments_g, wrappers_per_segment_c),
b_n_cfg_pages_g => n_cfg_pages_g,
b_n_time_slots_g => n_time_slots_g,
b_n_extra_params_g => n_extra_params_g,
b_cfg_re_g => cfg_re_g,
b_cfg_we_g => cfg_we_g,
 
a_id_min_g => bridge_a_id_min_c(seg-1),
a_id_max_g => bridge_a_id_max_c(seg-1),
a_addr_limit_g => bridge_a_addr_limit_c(seg-1),
 
b_id_min_g => bridge_b_id_min_c(seg-1),
b_id_max_g => bridge_b_id_max_c(seg-1),
b_addr_limit_g => bridge_b_addr_limit_c(seg-1)
 
)
port map (
a_clk => clk_noc,
a_rst_n => rst_n,
b_clk => clk_noc,
b_rst_n => rst_n,
a_bus_av_in => bus_wra_av(seg-1),
a_bus_data_in => bus_wra_data(seg-1),
a_bus_comm_in => bus_wra_comm(seg-1),
a_bus_full_in => bus_wra_full(seg-1),
a_bus_lock_in => bus_wra_lock(seg-1),
b_bus_av_in => bus_wra_av(seg),
b_bus_data_in => bus_wra_data(seg),
b_bus_comm_in => bus_wra_comm(seg),
b_bus_full_in => bus_wra_full(seg),
b_bus_lock_in => bus_wra_lock(seg),
a_bus_av_out => wra_bus_av(seg-1)(wrappers_per_segment_c),
a_bus_data_out => wra_bus_data(seg-1)(wrappers_per_segment_c),
a_bus_comm_out => wra_bus_comm(seg-1)(wrappers_per_segment_c),
a_bus_lock_out => wra_bus_lock(seg-1)(wrappers_per_segment_c),
a_bus_full_out => wra_bus_full(seg-1)(wrappers_per_segment_c),
b_bus_av_out => wra_bus_av(seg)(wrappers_per_segment_c+1),
b_bus_data_out => wra_bus_data(seg)(wrappers_per_segment_c+1),
b_bus_comm_out => wra_bus_comm(seg)(wrappers_per_segment_c+1),
b_bus_lock_out => wra_bus_lock(seg)(wrappers_per_segment_c+1),
b_bus_full_out => wra_bus_full(seg)(wrappers_per_segment_c+1)
-- synthesis translate_off
,
a_debug_out => open,
a_debug_in => (others => '0'),
b_debug_out => open,
b_debug_in => (others => '0')
-- synthesis translate_on
);
 
-- nullify extra signals
nullify_first_seg : if seg = 1 generate
-- no b-side on the first segment
wra_bus_av(seg-1)(wrappers_per_segment_c+1) <= '0';
wra_bus_full(seg-1)(wrappers_per_segment_c+1) <= '0';
wra_bus_lock(seg-1)(wrappers_per_segment_c+1) <= '0';
wra_bus_comm(seg-1)(wrappers_per_segment_c+1) <= (others => '0');
wra_bus_data(seg-1)(wrappers_per_segment_c+1) <= (others => '0');
end generate nullify_first_seg;
 
nullify_last_seg : if seg = n_segments_g-1 generate
-- no a-side here
wra_bus_av(seg)(wrappers_per_segment_c) <= '0';
wra_bus_full(seg)(wrappers_per_segment_c) <= '0';
wra_bus_lock(seg)(wrappers_per_segment_c) <= '0';
wra_bus_comm(seg)(wrappers_per_segment_c) <= (others => '0');
wra_bus_data(seg)(wrappers_per_segment_c) <= (others => '0');
end generate nullify_last_seg;
end generate bridge_needed;
 
 
no_bridges : if n_segments_g = 1 generate
 
-- no bridges, nullify extra all signals
/funbase_ip_library/trunk/TUT/ip.hwp.interface/pcie/pcie_to_hibi.comp/2.0/tb/pcie_to_hibi_test_app.vhd
224,7 → 224,7
constant MEM_DATA_WIDTH : integer := 256;
constant MEM_BE_WIDTH : integer := MEM_DATA_WIDTH/8;
component a2_ddr2_dimm_1GB
component alt_ddr2_agx2
port (
local_address : in std_logic_vector(MEM_ADDR_WIDTH-1 downto 0);
local_write_req : in std_logic;
268,7 → 268,7
--synthesis translate_off
component a2_ddr2_dimm_1GB_full_mem_model
component alt_ddr2_agx2_full_mem_model
port (
global_reset_n : out std_logic;
mem_dq : inout std_logic_vector(63 downto 0);
664,7 → 664,7
mem_be(MEM_BE_WIDTH-1 downto 4) <= (others => '1');
gen_1 : if ENABLE_SIM = 1 generate
mem_ctrl : a2_ddr2_dimm_1GB
mem_ctrl : alt_ddr2_agx2
port map (
pll_ref_clk => clk_ref,
phy_clk => clk,
702,7 → 702,7
end generate;
gen_2 : if ENABLE_SIM = 0 generate
mem_ctrl : a2_ddr2_dimm_1GB
mem_ctrl : alt_ddr2_agx2
port map (
pll_ref_clk => clk_ref,
phy_clk => clk,
739,7 → 739,7
end generate;
--synthesis translate_off
a2_ddr2_dimm_1GB_0 : a2_ddr2_dimm_1GB_full_mem_model
a2_ddr2_dimm_1GB_0 : alt_ddr2_agx2_full_mem_model
port map (
mem_clk => ddr2_clk_0(0),
mem_clk_n => ddr2_clk_n_0(0),
/funbase_ip_library/trunk/TUT/ip.hwp.interface/pcie/pcie_to_hibi.comp/2.0/hdl/pcie_dma.vhd
1,37 → 1,44
-------------------------------------------------------------------------------
-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
-------------------------------------------------------------------------------
-- Title : PCIe DMA
-- Project :
-- Project : Funbase
-------------------------------------------------------------------------------
-- File : pcie_dma.vhd
-- Author :
-- Company :
-- Last update: 07.02.2011
-- Version : 0.1
-- Author : Juha Arvio
-- Company : TUT
-- Last update: 05.10.2011
-- Version : 0.91
-- Platform :
-------------------------------------------------------------------------------
-- Description:
--
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 07.02.2010 0.1 arvio Created
-- 07.02.2011 0.1 arvio Created
-- 05.10.2011 0.91 arvio
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This file is a part of a free IP-block: you can redistribute it and/or modify
-- it under the terms of the Lesser GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This IP-block is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- Lesser GNU General Public License for more details.
--
-- You should have received a copy of the Lesser GNU General Public License
-- along with Transaction Generator. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
49,7 → 56,7
HIBI_RW_LENGTH_WIDTH : integer := 16;
PCIE_RW_LENGTH_WIDTH : integer := 13;
PCIE_ID_WIDTH : integer := 16;
-- PKT_TAG_WIDTH : integer := 9;
PKT_TAG_WIDTH : integer := 8;
PCIE_TAG_WIDTH : integer := 6;
PCIE_DATA_WIDTH : integer := 128;
57,10 → 64,15
PCIE_LOWER_ADDR_WIDTH : integer := 7;
DMA_BAR : integer := 2;
BURST_LATENCY : integer := 2;
DMA_DESC_REQ_FREE_LOW_LIMIT : integer := 16;
ADDR_TO_LIMIT_WIDTH : integer := 12;
IRQ_WIDTH : integer := 5;
INFO_WIDTH : integer := 3 ); -- traffic class number width on pcie
INFO_WIDTH : integer := 3; -- traffic class number width on pcie
CYCLES_IN_SEC : integer := 100000000;
CYCLES_IN_SEC_WIDTH : integer := 32;
PERF_REGS : integer := 1 );
port (
clk : in std_logic;
75,7 → 87,7
-- ipkt_addr_size_in : in std_logic;
ipkt_length_in : in std_logic_vector(PCIE_RW_LENGTH_WIDTH-1 downto 0);
ipkt_req_id_in : in std_logic_vector(PCIE_ID_WIDTH-1 downto 0);
ipkt_tag_in : in std_logic_vector(PCIE_TAG_WIDTH-1 downto 0);
ipkt_tag_in : in std_logic_vector(PKT_TAG_WIDTH-1 downto 0);
ipkt_bar_in : in std_logic_vector(2 downto 0);
ipkt_re_out : out std_logic;
90,7 → 102,7
-- ipkt_addr_size_out : out std_logic;
ipkt_length_out : out std_logic_vector(HIBI_RW_LENGTH_WIDTH-1 downto 0);
ipkt_req_id_out : out std_logic_vector(PCIE_ID_WIDTH-1 downto 0);
ipkt_tag_out : out std_logic_vector(PCIE_TAG_WIDTH-1 downto 0);
ipkt_tag_out : out std_logic_vector(PKT_TAG_WIDTH-1 downto 0);
-- ipkt_bardec_out : out std_logic_vector(7 downto 0);
ipkt_re_in : in std_logic;
105,7 → 117,7
-- opkt_addr_size_in : in std_logic;
opkt_length_in : in std_logic_vector(PCIE_RW_LENGTH_WIDTH-1 downto 0);
opkt_req_id_in : in std_logic_vector(PCIE_ID_WIDTH-1 downto 0);
opkt_tag_in : in std_logic_vector(PCIE_TAG_WIDTH-1 downto 0);
opkt_tag_in : in std_logic_vector(PKT_TAG_WIDTH-1 downto 0);
opkt_we_in : in std_logic;
opkt_burst_we_in : in std_logic;
120,7 → 132,7
-- opkt_addr_size_out : out std_logic;
opkt_length_out : out std_logic_vector(PCIE_RW_LENGTH_WIDTH-1 downto 0);
opkt_req_id_out : out std_logic_vector(PCIE_ID_WIDTH-1 downto 0);
opkt_tag_out : out std_logic_vector(PCIE_TAG_WIDTH-1 downto 0);
opkt_tag_out : out std_logic_vector(PKT_TAG_WIDTH-1 downto 0);
opkt_we_out : out std_logic;
opkt_burst_we_out : out std_logic;
132,6 → 144,11
irq_full_in : in std_logic;
dma_irq_full_out : out std_logic;
dma_writes_in_sec_out : out std_logic_vector(CYCLES_IN_SEC_WIDTH-1 downto 0);
dma_reads_in_sec_out : out std_logic_vector(CYCLES_IN_SEC_WIDTH-1 downto 0);
dma_write_to_read_cycles_out : out std_logic_vector(CYCLES_IN_SEC_WIDTH-1 downto 0);
dummy_debug_out : out std_logic;
debug_out : out std_logic );
 
end pcie_dma;
219,6 → 236,8
constant DMA_DESC_FIFO_MAX_DESCS : integer := DMA_DESC_FIFO_LENGTH/4;
constant DMA_DESC_FIFO_MAX_DESCS_WIDTH : integer := log2_ceil(DMA_DESC_FIFO_MAX_DESCS);
-- constant CYCLES_IN_SEC_WIDTH : integer := log2_ceil(CYCLES_IN_SEC);
-- constant DMA_TAG : std_logic_vector(PKT_TAG_WIDTH-PCIE_LOWER_TAG_WIDTH downto 0) := i2s(1, PKT_TAG_WIDTH-PCIE_LOWER_TAG_WIDTH+1);
constant DMA_DESC_TAG : std_logic_vector(1 downto 0) := (others => '0');
constant DMA_RDATA_TAG : std_logic_vector(1 downto 0) := DMA_DESC_TAG + 1;
225,7 → 244,7
constant DMA_P2H_RDATA_TAG : std_logic_vector(1 downto 0) := DMA_RDATA_TAG + 1;
constant H2P_RDATA_TAG : std_logic_vector(1 downto 0) := DMA_P2H_RDATA_TAG + 1;
type dma_state_t is (DMA_WAIT, DMA_DESC_WAIT, DMA_DELAY, DMA_WAIT_EPLAST, DMA_SEND_EPLAST, DMA_SEND_IRQ, DMA_WRITE, DMA_WDATA_WAIT, DMA_READ, DMA_RDATA_WAIT);
type dma_state_t is (DMA_WAIT, DMA_DESC_WAIT, DMA_DELAY, DMA_WAIT_EPLAST, DMA_SEND_EPLAST, DMA_SEND_IRQ, DMA_WAIT_WRITE, DMA_WRITE, DMA_WDATA_WAIT, DMA_READ, DMA_RDATA_WAIT);
signal dma_state_r : dma_state_t;
type dma_cfg_rd_state_t is (DMA_CFG_READ_WAIT, DMA_CFG_READ);
278,7 → 297,7
signal dma_cfg_raddr_r : std_logic_vector(4 downto 0);
signal dma_cfg_rdata : std_logic_vector(31 downto 0);
signal dma_cfg_req_id_r : std_logic_vector(PCIE_ID_WIDTH-1 downto 0);
signal dma_cfg_tag_r : std_logic_vector(PCIE_TAG_WIDTH-1 downto 0);
signal dma_cfg_tag_r : std_logic_vector(PKT_TAG_WIDTH-1 downto 0);
signal dma_ep_addr_r : std_logic_vector(HIBI_DATA_WIDTH-1 downto 0);
signal dma_rc_addr_r : std_logic_vector(PCIE_ADDR_WIDTH-1 downto 0);
signal dma_rw_length_r : std_logic_vector(15 downto 0);
331,11 → 350,22
-- signal opkt_burst_we : std_logic;
signal opkt_is_write : std_logic;
signal opkt_is_dma_rdata_0 : std_logic;
signal opkt_we : std_logic;
signal debug_start_r : std_logic;
signal debug_started_r : std_logic;
signal debug_desc_fifo_rw : std_logic;
signal sec_pulse_r : std_logic;
signal intra_sec_cnt_r : std_logic_vector(CYCLES_IN_SEC_WIDTH-1 downto 0);
signal dma_write_sec_cnt_r : std_logic_vector(CYCLES_IN_SEC_WIDTH-1 downto 0);
signal dma_read_sec_cnt_r : std_logic_vector(CYCLES_IN_SEC_WIDTH-1 downto 0);
signal dma_write_sec_val_r : std_logic_vector(CYCLES_IN_SEC_WIDTH-1 downto 0);
signal dma_read_sec_val_r : std_logic_vector(CYCLES_IN_SEC_WIDTH-1 downto 0);
signal dma_write_to_read_cycles_r : std_logic_vector(CYCLES_IN_SEC_WIDTH-1 downto 0);
signal dma_write_to_read_on_r : std_logic;
begin
debug_out <= debug_start_r;
process (clk, rst_n)
357,11 → 387,69
end if;
end process;
dma_cfg_rd_ready <= opkt_ready_in and not(burst_active);
dma_desc_rd_ready <= dma_cfg_rd_ready and not(opkt_dma_cfg_rdata_r);
dma_desc_wr_ready <= dma_desc_rd_ready and not(dma_desc_re_r);
dma_h2p_rd_ready <= dma_desc_wr_ready and not(dma_desc_we_r);
------------------------------------------------------------------------------
-- Performance registers:
------------------------------------------------------------------------------
gen_perf_regs : if (PERF_REGS = 1) generate
dma_writes_in_sec_out <= dma_write_sec_val_r;
dma_reads_in_sec_out <= dma_read_sec_val_r;
dma_write_to_read_cycles_out <= dma_write_to_read_cycles_r;
process (clk, rst_n)
begin
if (rst_n = '0') then
intra_sec_cnt_r <= (others => '0');
sec_pulse_r <= '0';
dma_write_sec_cnt_r <= (others => '0');
dma_read_sec_cnt_r <= (others => '0');
dma_write_sec_val_r <= (others => '0');
dma_read_sec_val_r <= (others => '0');
dma_write_to_read_cycles_r <= (others => '0');
dma_write_to_read_on_r <= '0';
elsif (clk'event and clk = '1') then
if (intra_sec_cnt_r = (CYCLES_IN_SEC-1)) then
intra_sec_cnt_r <= (others => '0');
sec_pulse_r <= '1';
else
intra_sec_cnt_r <= intra_sec_cnt_r + 1;
sec_pulse_r <= '0';
end if;
if (wdma_start_r = '1') then
dma_write_to_read_on_r <= '1';
elsif (rdma_start_r = '1') then
dma_write_to_read_on_r <= '0';
end if;
if (wdma_start_r = '1') then
dma_write_to_read_cycles_r <= (others => '0');
elsif (dma_write_to_read_on_r = '1') then
dma_write_to_read_cycles_r <= dma_write_to_read_cycles_r + 1;
end if;
if (sec_pulse_r = '1') then
dma_write_sec_val_r <= dma_write_sec_cnt_r;
dma_write_sec_cnt_r <= (others => '0');
elsif ((ipkt_is_dma_rdata = '1') and (ipkt_valid = '1') and (ipkt_re_in = '1')) then
dma_write_sec_cnt_r <= dma_write_sec_cnt_r + 1;
else
dma_write_sec_cnt_r <= dma_write_sec_cnt_r;
end if;
if (sec_pulse_r = '1') then
dma_read_sec_val_r <= dma_read_sec_cnt_r;
dma_read_sec_cnt_r <= (others => '0');
elsif ((opkt_is_dma_rdata_0 = '1') and (opkt_burst_we_in = '1')) then
dma_read_sec_cnt_r <= dma_read_sec_cnt_r + 1;
else
dma_read_sec_cnt_r <= dma_read_sec_cnt_r;
end if;
end if;
end process;
end generate;
opkt_ready_out <= opkt_ready_in and not(opkt_dma_cfg_rdata_r) and not(dma_desc_re_r) and not(dma_desc_we_r) and not(dma_p2h_re_r);
ipkt_is_dma_cfg_wr <= ipkt_is_write_in and is_dma_bar;
378,7 → 466,13
-- ipkt_re_out <= ipkt_re_in and not(ipkt_re_stall);
ipkt_valid_out <= ipkt_valid or dma_p2h_re_r;
opkt_we_out <= not(burst_active) and (opkt_we_in or opkt_dma_cfg_rdata_r or dma_desc_re_r or dma_desc_we_r or dma_h2p_re_r);
-- opkt_we_dma_desc_re <= not(burst_active) and (opkt_we_in or opkt_dma_cfg_rdata_r or dma_desc_we_r or dma_h2p_re_r);
-- opkt_we_dma_desc_we <= not(burst_active) and (opkt_we_in or opkt_dma_cfg_rdata_r or dma_desc_re_r or dma_h2p_re_r);
-- opkt_we_dma_cfg_rdata <= not(burst_active) and (opkt_we_in or dma_desc_re_r or dma_desc_we_r or dma_h2p_re_r);
-- opkt_we_dma_h2p_re <= not(burst_active) and (opkt_we_in or opkt_dma_cfg_rdata_r or dma_desc_re_r or dma_desc_we_r or dma_h2p_re_r);
opkt_we <= not(burst_active) and (opkt_we_in or opkt_dma_cfg_rdata_r or dma_desc_re_r or dma_desc_we_r or dma_h2p_re_r);
opkt_we_out <= opkt_we;
opkt_burst_we_out <= opkt_burst_we_in;
ipkt_addr_to_limit_out <= addr_to_limit_r(ADDR_TO_LIMIT_WIDTH-1 downto 0);
392,7 → 486,8
dma_cfg_rdata, dma_cfg_req_id_r, dma_cfg_tag_r, dma_desc_re_r, dma_desc_addr_r, dma_desc_length_r, ipkt_data_in, ipkt_re_in, ipkt_is_write_in, dma_h2p_re_r,
ipkt_is_read_req_in, ipkt_is_rdata_in, ipkt_addr_in, ipkt_length_in, ipkt_req_id_in, ipkt_tag_in, ipkt_is_dma_cfg_rdata, ipkt_valid_in, dma_p2h_re_r, ipkt_bar_in,
dma_rw_length_r, dma_rc_addr_r, is_dma_bar, ipkt_re_r, opkt_is_dma_rdata, dma_desc_we_r, dma_desc_cnt_r, ipkt_is_dma_rdata, wdma_start_r, opkt_burst_we_in,
opkt_dma_cfg_rdata_r, rdma_desc_last_r, dma_ep_addr_r, opkt_is_write_r, opkt_is_dma_rdata_r, opkt_is_dma_rdata_0, burst_active_r)
opkt_dma_cfg_rdata_r, rdma_desc_last_r, dma_ep_addr_r, opkt_is_write_r, opkt_is_dma_rdata_r, opkt_is_dma_rdata_0, burst_active_r, burst_active,
dma_cfg_rd_ready, dma_desc_rd_ready, dma_desc_wr_ready, opkt_ready_in)
-- variable opkt_burst_we_v : std_logic;
-- variable opkt_is_write_v : std_logic;
-- variable opkt_is_dma_rdata_v : std_logic;
466,11 → 561,19
opkt_is_read_req_out <= opkt_is_read_req_in;
opkt_is_rdata_out <= opkt_is_rdata_in;
opkt_length_out <= opkt_length_in;
opkt_tag_out <= opkt_tag_in(PCIE_TAG_WIDTH-1 downto 0);
opkt_tag_out <= opkt_tag_in(PKT_TAG_WIDTH-1 downto 0);
opkt_data_out <= opkt_data_in;
opkt_addr_out <= opkt_addr_in;
opkt_req_id_out <= opkt_req_id_in;
---------------------------------------------------------------------------
-- the order of these two blocks should be the same
---------------------------------------------------------------------------
dma_cfg_rd_ready <= opkt_ready_in and not(burst_active);
dma_desc_rd_ready <= dma_cfg_rd_ready and not(opkt_dma_cfg_rdata_r);
dma_desc_wr_ready <= dma_desc_rd_ready and not(dma_desc_re_r);
dma_h2p_rd_ready <= dma_desc_wr_ready and not(dma_desc_we_r);
---------------------------------------------------------------------------
if (opkt_is_dma_rdata_0 = '1') then
opkt_is_write_out <= '1';
opkt_is_read_req_out <= '0';
494,7 → 597,8
opkt_is_rdata_out <= '0';
opkt_addr_out <= dma_desc_addr_r;
opkt_length_out <= dma_desc_length_r;
opkt_tag_out <= DMA_DESC_TAG & "0000";
opkt_tag_out <= (others => '0');
opkt_tag_out(PKT_TAG_WIDTH-1 downto PKT_TAG_WIDTH-2) <= DMA_DESC_TAG;
elsif (dma_desc_we_r = '1') then
opkt_is_write_out <= '1';
516,9 → 620,12
opkt_is_rdata_out <= '0';
opkt_addr_out <= dma_rc_addr_r;
opkt_length_out <= dma_rw_length_r(PCIE_RW_LENGTH_WIDTH-3 downto 0) & "00";
opkt_tag_out <= DMA_RDATA_TAG & "0000";
opkt_tag_out <= (others => '0');
opkt_tag_out(PKT_TAG_WIDTH-1 downto PKT_TAG_WIDTH-2) <= DMA_RDATA_TAG;
end if;
---------------------------------------------------------------------------
ipkt_data_out <= ipkt_data_in;
ipkt_is_write_out <= ipkt_is_write_in;
ipkt_is_read_req_out <= ipkt_is_read_req_in;
536,7 → 643,8
ipkt_is_rdata_out <= '0';
ipkt_addr_out <= dma_ep_addr_r; --(HIBI_DATA_WIDTH-3 downto 0) & "00";
ipkt_length_out <= dma_rw_length_r(HIBI_RW_LENGTH_WIDTH-3 downto 0) & "00";
ipkt_tag_out <= DMA_P2H_RDATA_TAG & "0000";
ipkt_tag_out <= (others => '0');
ipkt_tag_out(PKT_TAG_WIDTH-1 downto PKT_TAG_WIDTH-2) <= DMA_P2H_RDATA_TAG;
ipkt_valid <= '1';
ipkt_re_out <= '0';
560,11 → 668,11
is_dma_bar <= '0';
end if;
if (ipkt_tag_in(PCIE_TAG_WIDTH-1 downto PCIE_TAG_WIDTH-2) = DMA_DESC_TAG) then
if (ipkt_tag_in(PKT_TAG_WIDTH-1 downto PKT_TAG_WIDTH-2) = DMA_DESC_TAG) then
is_dma_desc_tag <= '1';
is_dma_rdata_tag <= '0';
is_h2p_rdata_tag <= '0';
elsif (ipkt_tag_in(PCIE_TAG_WIDTH-1 downto PCIE_TAG_WIDTH-2) = DMA_RDATA_TAG) then
elsif (ipkt_tag_in(PKT_TAG_WIDTH-1 downto PKT_TAG_WIDTH-2) = DMA_RDATA_TAG) then
is_dma_desc_tag <= '0';
is_dma_rdata_tag <= '1';
is_h2p_rdata_tag <= '0';
574,7 → 682,7
is_h2p_rdata_tag <= '1';
end if;
if ((opkt_tag_in(PCIE_TAG_WIDTH-1) = '1') and (opkt_is_rdata_in = '1')) then
if ((opkt_tag_in(PKT_TAG_WIDTH-1) = '1') and (opkt_is_rdata_in = '1')) then
opkt_is_dma_rdata <= '1';
else
opkt_is_dma_rdata <= '0';
740,7 → 848,7
when DMA_READ_DESC_WAIT =>
if (dma_desc_fetch_amount_r > 0) then
if (dma_desc_req_free_amount_r > 0) then
if ((dma_desc_req_free_amount_r > DMA_DESC_REQ_FREE_LOW_LIMIT) and (opkt_we = '0')) then
dma_desc_re_r <= '1';
if (dma_desc_fetch_amount_r > dma_desc_req_free_amount_r) then
802,6 → 910,8
if (((wdma_started_r = '1') and (dma_desc_cnt_r > wdma_desc_last_r)) or ((rdma_started_r = '1') and (dma_desc_cnt_r > rdma_desc_last_r))) then
-- wdma_start_r <= wdma_start_r and not(wdma_started_r);
-- rdma_start_r <= rdma_start_r and not(rdma_started_r);
wdma_started_r <= '0';
rdma_started_r <= '0';
dma_state_r <= DMA_WAIT;
else
if (dma_desc_fifo_empty = '0') then
821,10 → 931,11
when others => --DMA_DESC_RC_LOWER_ADDR_WORD =>
dma_rc_addr_r(31 downto 0) <= dma_desc_fifo_rdata;
addr_to_limit_r <= "1000000000000" - dma_desc_fifo_rdata(11 downto 0);
dma_desc_req_free_inc_v := '1';
if (wdma_started_r = '1') then
dma_desc_req_free_inc_v := '1';
dma_h2p_re_r <= '1';
dma_state_r <= DMA_WRITE;
-- dma_h2p_re_r <= '1';
dma_state_r <= DMA_WAIT_WRITE;
else
dma_p2h_re_r <= '1';
dma_state_r <= DMA_READ;
838,14 → 949,17
end if;
when DMA_DELAY =>
if (dma_delay_r = (BURST_LATENCY-1)) then
if ((dma_delay_r = (BURST_LATENCY-1)) and (opkt_we = '0')) then
dma_desc_we_r <= '1';
dma_state_r <= DMA_SEND_EPLAST;
end if;
dma_delay_r <= dma_delay_r + 1;
if (dma_delay_r < (BURST_LATENCY-1)) then
dma_delay_r <= dma_delay_r + 1;
end if;
when DMA_WAIT_EPLAST =>
if (burst_active = '0') then
if ((burst_active = '0') and (opkt_we = '0')) then
dma_desc_we_r <= '1';
dma_state_r <= DMA_SEND_EPLAST;
end if;
870,6 → 984,12
dma_state_r <= DMA_DESC_WAIT;
end if;
when DMA_WAIT_WRITE =>
if (opkt_we = '0') then
dma_h2p_re_r <= '1';
dma_state_r <= DMA_WRITE;
end if;
when DMA_WRITE =>
if (dma_h2p_rd_ready = '1') then
dma_h2p_re_r <= '0';
908,7 → 1028,7
if ((opkt_is_dma_rdata_0 = '1') and (opkt_ready_in = '1') and (opkt_burst_we_in = '1')) then
if (dma_rw_length_r = 1) then
if ((dma_eplast_ena_r = '1') or (rdma_eplast_ena_r = '1')) then
dma_desc_we_r <= '1';
-- dma_desc_we_r <= '1';
dma_state_r <= DMA_WAIT_EPLAST;
elsif ((dma_msi_ena_r = '1') or (rdma_msi_ena_r = '1')) then
dma_desc_cnt_r <= dma_desc_cnt_r + 1;
967,7 → 1087,7
end if;
end process;
dma_desc_fifo : entity work.fifo_sc
dma_desc_fifo : entity work.alt_fifo_sc
generic map ( DATA_WIDTH => HIBI_DATA_WIDTH,
FIFO_LENGTH => DMA_DESC_FIFO_LENGTH,
CNT_WIDTH => log2_ceil(DMA_DESC_FIFO_LENGTH-1) )
979,6 → 1099,9
re_in => dma_desc_fifo_re_r,
we_in => dma_desc_fifo_we_r,
empty_out => dma_desc_fifo_empty );
debug_desc_fifo_rw <= dma_desc_fifo_re_r or dma_desc_fifo_we_r;
dummy_debug_out <= debug_desc_fifo_rw;
end rtl;
/funbase_ip_library/trunk/TUT/ip.hwp.interface/pcie/pcie_to_hibi.comp/2.0/hdl/buf_ptr_ctrl.vhd
1,37 → 1,44
-------------------------------------------------------------------------------
-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
-------------------------------------------------------------------------------
-- Title : Buffer pointer control
-- Project :
-- Project : Funbase
-------------------------------------------------------------------------------
-- File : buf_ptr_ctrl.vhd
-- Author :
-- Company :
-- Last update: 27.05.2011
-- Version : 0.9
-- Author : Juha Arvio
-- Company : TUT
-- Last update: 05.10.2011
-- Version : 0.91
-- Platform :
-------------------------------------------------------------------------------
-- Description:
--
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 30.11.2010 0.1 arvio Created
-- 05.10.2011 0.91 arvio
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This file is a part of a free IP-block: you can redistribute it and/or modify
-- it under the terms of the Lesser GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This IP-block is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- Lesser GNU General Public License for more details.
--
-- You should have received a copy of the Lesser GNU General Public License
-- along with Transaction Generator. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
585,7 → 592,7
buf_rpart_p1 <= cnt_rdata_p1(BUFFER_RPART_U downto BUFFER_RPART_L);
addr_to_limit_p1 <= cnt_rdata_p1(ADDR_TO_LIMIT_U downto ADDR_TO_LIMIT_L);
cnt_mem_0 : entity work.onchip_mem_sc
cnt_mem_0 : entity work.alt_mem_sc
generic map ( DATA_WIDTH => COUNT_DATA_WIDTH,
ADDR_WIDTH => BUFFERS_WIDTH,
MEM_SIZE => BUFFERS )
/funbase_ip_library/trunk/TUT/ip.hwp.interface/pcie/pcie_to_hibi.comp/2.0/hdl/hibi_if.vhd
1,37 → 1,44
-------------------------------------------------------------------------------
-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
-------------------------------------------------------------------------------
-- Title : HIBI interface
-- Project : Funbase
-------------------------------------------------------------------------------
-- File : hibi_if.vhd
-- Author : Juha Arvio
-- Company : TTY
-- Last update: 27.05.2011
-- Version : 0.9
-- Company : TUT
-- Last update: 05.10.2011
-- Version : 0.91
-- Platform :
-------------------------------------------------------------------------------
-- Description: a HIBI interface for PCIE to HIBI adapter
--
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 15.10.2010 0.1 arvio Created
-- 05.10.2011 0.91 arvio
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This file is a part of a free IP-block: you can redistribute it and/or modify
-- it under the terms of the Lesser GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This IP-block is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- Lesser GNU General Public License for more details.
--
-- You should have received a copy of the Lesser GNU General Public License
-- along with Transaction Generator. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
61,7 → 68,7
PCIE_RW_LENGTH_WIDTH : integer := 13;
PCIE_ID_WIDTH : integer := 16;
PCIE_FUNC_WIDTH : integer := 3;
-- PKT_TAG_WIDTH : integer := 9;
PKT_TAG_WIDTH : integer := 8;
PCIE_TAG_WIDTH : integer := 6;
ADDR_TO_LIMIT_WIDTH : integer := 12;
123,7 → 130,7
-- ipkt_byte_cnt_in : in std_logic_vector(PCIE_RW_LENGTH_WIDTH-1 downto 0);
ipkt_req_id_in : in std_logic_vector(PCIE_ID_WIDTH-1 downto 0);
-- ipkt_cmp_id_in : in std_logic_vector(PCIE_ID_WIDTH-1 downto 0);
ipkt_tag_in : in std_logic_vector(PCIE_TAG_WIDTH-1 downto 0);
ipkt_tag_in : in std_logic_vector(PKT_TAG_WIDTH-1 downto 0);
ipkt_valid_in : in std_logic;
-- ipkt_one_d_in : in std_logic;
143,7 → 150,7
opkt_req_id_out : out std_logic_vector(PCIE_ID_WIDTH-1 downto 0);
-- opkt_cmp_id_out : out std_logic_vector(PCIE_ID_WIDTH-1 downto 0);
-- opkt_func_id_out : out std_logic_vector(PCIE_FUNC_WIDTH-1 downto 0);
opkt_tag_out : out std_logic_vector(PCIE_TAG_WIDTH-1 downto 0);
opkt_tag_out : out std_logic_vector(PKT_TAG_WIDTH-1 downto 0);
-- opkt_wdata_req_in : in std_logic;
297,7 → 304,7
constant P2H_REQ_ID_L : integer := P2H_PARTS_LEFT_U + 1;
constant P2H_REQ_ID_U : integer := P2H_REQ_ID_L + PCIE_ID_WIDTH - 1;
constant P2H_TAG_L : integer := P2H_REQ_ID_U + 1;
constant P2H_TAG_U : integer := P2H_TAG_L + PCIE_TAG_WIDTH - 1;
constant P2H_TAG_U : integer := P2H_TAG_L + PKT_TAG_WIDTH - 1;
constant P2H_RCONF_WIDTH : integer := P2H_TAG_U+1;
514,7 → 521,7
signal opkt_tx_packets_left_r : std_logic_vector(HIBI_RW_LENGTH_WIDTH-PCIE_LOWER_ADDR_WIDTH-1 downto 0);
signal opkt_tx_req_id_r : std_logic_vector(PCIE_ID_WIDTH-1 downto 0);
-- signal opkt_tx_cpl_id_r : std_logic_vector(PCIE_ID_WIDTH-1 downto 0);
signal opkt_tx_tag_r : std_logic_vector(PCIE_TAG_WIDTH-1 downto 0);
signal opkt_tx_tag_r : std_logic_vector(PKT_TAG_WIDTH-1 downto 0);
signal opkt_tx_is_write_r : std_logic;
signal opkt_tx_is_read_req_r : std_logic;
539,7 → 546,7
signal p2h_rconf_total_amount_rv : std_logic_vector(HIBI_RW_LENGTH_WIDTH-1 downto 0);
signal p2h_rconf_packets_left_rv : std_logic_vector(HIBI_RW_LENGTH_WIDTH-PCIE_LOWER_ADDR_WIDTH-1 downto 0);
signal p2h_rconf_req_id_rv : std_logic_vector(PCIE_ID_WIDTH-1 downto 0);
signal p2h_rconf_tag_rv : std_logic_vector(PCIE_TAG_WIDTH-1 downto 0);
signal p2h_rconf_tag_rv : std_logic_vector(PKT_TAG_WIDTH-1 downto 0);
signal p2h_rconf_upd_we_r : std_logic;
547,6 → 554,8
signal p2h_rconf_upd_wdata : std_logic_vector(P2H_RCONF_WIDTH-1 downto 0);
signal p2h_rconf_upd_rdata : std_logic_vector(P2H_RCONF_WIDTH-1 downto 0);
signal ipkt_packets : std_logic_vector(HIBI_RW_LENGTH_WIDTH-PCIE_CPL_LENGTH_MIN_WIDTH-1 downto 0);
-- signal p2h_tx_lower_addr : std_logic_vector(PCIE_LOWER_ADDR_WIDTH-1 downto 0);
-- signal p2h_tx_length_total : std_logic_vector(HIBI_RW_LENGTH_WIDTH-1 downto 0);
-- signal p2h_tx_packets_left : std_logic_vector(HIBI_RW_LENGTH_WIDTH-PCIE_LOWER_ADDR_WIDTH-1 downto 0);
563,6 → 572,28
signal init_done : std_logic;
begin
--synthesis translate_off
-- debug_gen_0 : if DEBUG = 1 generate
process
variable DEBUG : integer;
begin
DEBUG := 1;
report "---------------------------------------------------";
report "";
report "HIBI_DATA_WIDTH: " & str(HIBI_DATA_WIDTH);
report "HIBI_COM_WIDTH: " & str(HIBI_COM_WIDTH);
report "HIBI_COM_WR: " & str(HIBI_COM_WR);
report "HIBI_COM_RD: " & str(HIBI_COM_RD);
report "HIBI_COM_MSG_WR: " & str(HIBI_COM_MSG_WR);
report "HIBI_IF_ADDR: " & str(HIBI_IF_ADDR);
report "H2P_WR_CHANS: " & str(H2P_WR_CHANS);
report "H2P_RD_CHANS: " & str(H2P_RD_CHANS);
report "---------------------------------------------------";
wait until DEBUG = 0;
end process;
-- end generate;
--synthesis translate_on
init_done <= h2p_conf_state_init_done_r and p2h_req_init_done and opkt_buf_init_done;
init_done_out <= init_done;
872,7 → 903,8
hibi_msg_wdata_r(HIBI_RW_LENGTH_WIDTH-1 downto 0) <= ipkt_length_in;
hibi_msg_wdata_r(HIBI_DATA_BYTE_WIDTH+HDMA_RW_AMOUNT_WIDTH-1 downto HDMA_RW_AMOUNT_WIDTH) <= (others => '1');
when "01" =>
hibi_msg_wdata_r <= HIBI_IF_ADDR(HIBI_DATA_WIDTH-1 downto HIBI_ADDR_SPACE_WIDTH) & P2H_RD_RET_ADDR_BASE_OFFSET(HIBI_ADDR_SPACE_WIDTH-1 downto OPKT_BUFFERS_WIDTH) & p2h_buf_index_r;
hibi_msg_wdata_r <= HIBI_IF_ADDR(HIBI_DATA_WIDTH-1 downto HIBI_ADDR_SPACE_WIDTH)
& P2H_RD_RET_ADDR_BASE_OFFSET(HIBI_ADDR_SPACE_WIDTH-1 downto OPKT_BUFFERS_WIDTH) & p2h_buf_index_r;
when "10" =>
hibi_msg_wdata_r(HIBI_DATA_WIDTH-1 downto 1) <= (others => '0');
hibi_msg_wdata_r(0) <= '1';
1481,7 → 1513,7
------------------------------------------------------------------------------------------
-- H2P read/write configuration state memory
------------------------------------------------------------------------------------------
h2p_conf_state_mem : entity work.onchip_mem_sc
h2p_conf_state_mem : entity work.alt_mem_sc
generic map ( DATA_WIDTH => H2P_CONF_STATE_WIDTH,
ADDR_WIDTH => H2P_CHANS_WIDTH + 1,
MEM_SIZE => H2P_CHANS*2 )
1580,7 → 1612,8
p2h_ack_rx_hibi_dma_comp <= hibi_msg_addr_in(P2H_HDMA_ADDR_SPACES_WIDTH downto 0);
p2h_ack_rx_hibi_dma_offset <= hibi_msg_data_in(HDMA_CHANNELS_WIDTH-1 downto 0);
process (hibi_msg_re_r, hibi_msg_empty_in, hibi_msg_addr_in(10 downto 8), hibi_msg_data_in, p2h_req_tx_we_r, hibi_msg_we_r, hibi_msg_full_in)
process (hibi_msg_re_r, hibi_msg_empty_in, hibi_msg_addr_in(10 downto 8), hibi_msg_data_in, p2h_req_tx_we_r, hibi_msg_we_r, hibi_msg_full_in,
ipkt_length_in)
begin
if ((p2h_req_tx_we_r = '1') and (hibi_msg_we_r = '0') and (hibi_msg_full_in = '0')) then
p2h_req_tx_ready <= '1';
1600,12 → 1633,18
else
p2h_ack_rx_valid <= '0';
end if;
if (ipkt_length_in(PCIE_CPL_LENGTH_MIN_WIDTH-1 downto 0) = 0) then
ipkt_packets <= ipkt_length_in(HIBI_RW_LENGTH_WIDTH-1 downto PCIE_CPL_LENGTH_MIN_WIDTH) - 1;
else
ipkt_packets <= ipkt_length_in(HIBI_RW_LENGTH_WIDTH-1 downto PCIE_CPL_LENGTH_MIN_WIDTH);
end if;
end process;
------------------------------------------------------------------------------------------
-- PC to HIBI output packet conf memory
------------------------------------------------------------------------------------------
p2h_opkt_conf_mem : entity work.onchip_mem_sc
p2h_opkt_conf_mem : entity work.alt_mem_sc
generic map ( DATA_WIDTH => P2H_RCONF_WIDTH,
ADDR_WIDTH => P2H_RD_CHANS_WIDTH,
MEM_SIZE => P2H_RD_CHANS )
1630,7 → 1669,7
p2h_rconf_wdata(P2H_LOWER_ADDR_U downto P2H_LOWER_ADDR_L) <= ipkt_addr_in(PCIE_LOWER_ADDR_WIDTH-1 downto 0);
p2h_rconf_wdata(P2H_TOTAL_AMOUNT_U downto P2H_TOTAL_AMOUNT_L) <= ipkt_length_in;
p2h_rconf_wdata(P2H_PARTS_LEFT_U downto P2H_PARTS_LEFT_L) <= ipkt_length_in(HIBI_RW_LENGTH_WIDTH-1 downto PCIE_CPL_LENGTH_MIN_WIDTH);
p2h_rconf_wdata(P2H_PARTS_LEFT_U downto P2H_PARTS_LEFT_L) <= ipkt_packets;
p2h_rconf_wdata(P2H_REQ_ID_U downto P2H_REQ_ID_L) <= ipkt_req_id_in;
p2h_rconf_wdata(P2H_TAG_U downto P2H_TAG_L) <= ipkt_tag_in;
1667,7 → 1706,7
------------------------------------------------------------------------------------------
-- H2P read configuration memory
------------------------------------------------------------------------------------------
h2p_rd_conf_mem : entity work.onchip_mem_sc
h2p_rd_conf_mem : entity work.alt_mem_sc
generic map ( DATA_WIDTH => H2P_RCONF_WIDTH,
ADDR_WIDTH => H2P_RD_CHANS_WIDTH,
MEM_SIZE => H2P_RD_CHANS )
1708,7 → 1747,7
end if;
end process;
h2p_rd_res_fifo : entity work.fifo_sc
h2p_rd_res_fifo : entity work.alt_fifo_sc
generic map ( DATA_WIDTH => H2P_RD_CHANS_WIDTH,
FIFO_LENGTH => H2P_RD_CHANS,
CNT_WIDTH => H2P_RD_CHANS_WIDTH )
1723,7 → 1762,7
h2p_rd_cfg_wdata <= (others => '0');
 
h2p_rd_cfg_fifo : entity work.fifo_sc
h2p_rd_cfg_fifo : entity work.alt_fifo_sc
generic map ( DATA_WIDTH => H2P_RD_CHANS_WIDTH,
FIFO_LENGTH => H2P_RD_CHANS,
CNT_WIDTH => H2P_RD_CHANS_WIDTH )
1739,7 → 1778,7
------------------------------------------------------------------------------------------
-- HIBI to PC write conf memory
------------------------------------------------------------------------------------------
h2p_opkt_conf_mem : entity work.onchip_mem_sc
h2p_opkt_conf_mem : entity work.alt_mem_sc
generic map ( DATA_WIDTH => H2P_WCONF_WIDTH,
ADDR_WIDTH => H2P_WR_CHANS_WIDTH,
MEM_SIZE => H2P_WR_CHANS )
/funbase_ip_library/trunk/TUT/ip.hwp.interface/pcie/pcie_to_hibi.comp/2.0/hdl/pcie_rx.vhd
1,37 → 1,46
-------------------------------------------------------------------------------
-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
-------------------------------------------------------------------------------
-- Title : PCIe RX
-- Project :
-- Project : Funbase
-------------------------------------------------------------------------------
-- File : pcie_rx.vhd
-- Author :
-- Company :
-- Last update: 03.02.2011
-- Version : 0.6
-- Author : Juha Arvio
-- Company : TUT
-- Last update: 05.10.2011
-- Version : 0.91
-- Platform :
-------------------------------------------------------------------------------
-- Description:
--
-- converts a PCIe RX interface (Altera PCIe compiler's Avalon ST interface)
-- to a input packet interface
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 13.10.2010 0.1 arvio Created
-- 05.10.2011 0.91 arvio
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This file is a part of a free IP-block: you can redistribute it and/or modify
-- it under the terms of the Lesser GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This IP-block is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- Lesser GNU General Public License for more details.
--
-- You should have received a copy of the Lesser GNU General Public License
-- along with Transaction Generator. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
49,7 → 58,8
PCIE_RW_LENGTH_WIDTH : integer := 13;
PCIE_ID_WIDTH : integer := 16;
PCIE_TAG_WIDTH : integer := 6;
-- PKT_TAG_WIDTH : integer := 9;
PKT_TAG_WIDTH : integer := 8;
PCIE_RD_LENGTH_WIDTH : integer := 7;
PCIE_DATA_WIDTH : integer := 128;
PCIE_ADDR_WIDTH : integer := 32 );
80,7 → 90,7
-- ipkt_byte_cnt_out : out std_logic_vector(PCIE_RW_LENGTH_WIDTH-1 downto 0);
ipkt_req_id_out : out std_logic_vector(PCIE_ID_WIDTH-1 downto 0);
-- ipkt_cmp_id_out : out std_logic_vector(PCIE_ID_WIDTH-1 downto 0);
ipkt_tag_out : out std_logic_vector(PCIE_TAG_WIDTH-1 downto 0);
ipkt_tag_out : out std_logic_vector(PKT_TAG_WIDTH-1 downto 0);
ipkt_bar_out : out std_logic_vector(2 downto 0);
ipkt_valid_out : out std_logic;
89,11 → 99,14
-- ipkt_last_part_out : out std_logic;
ipkt_re_in : in std_logic;
ipkt_data_out : out std_logic_vector(HIBI_DATA_WIDTH-1 downto 0);
debug_out : out std_logic );
-- tag_fifo_re_out : out std_logic;
-- tag_fifo_empty_in : in std_logic;
-- tag_fifo_data_in : in std_logic_vector(PKT_TAG_WIDTH-1 downto 0) );
debug_out : out std_logic;
tag_release_out : out std_logic;
tag_release_ready_in : in std_logic;
tag_release_res_out : out std_logic_vector(PCIE_TAG_WIDTH-1 downto 0);
tag_release_amount_out : out std_logic_vector(PCIE_RD_LENGTH_WIDTH-1 downto 0);
tag_release_data_in : in std_logic_vector(PKT_TAG_WIDTH-1 downto 0) );
 
end pcie_rx;
 
137,7 → 150,7
constant ENABLE_SIM : integer := 0
-- synthesis translate_off
+ 1
-- + 1
-- synthesis translate_on
;
249,6 → 262,8
signal tlp_hdri_addr_r : std_logic_vector(HIBI_DATA_WIDTH-1 downto 0);
signal tag_release_r : std_logic;
signal tlp_hdro_req_id : std_logic_vector(PCIE_ID_WIDTH-1 downto 0);
signal tlp_hdro_tag : std_logic_vector(PCIE_TAG_WIDTH-1 downto 0);
270,6 → 285,9
type tlp_part_state_t is (NO_PACKET, READ_FIRST_EMPTY_PARTS, READ_LAST_EMPTY_PARTS, FIRST_PART, MIDDLE_PART, LAST_PART);
signal tlp_part_state_r : tlp_part_state_t;
type tag_release_state_t is (WAIT_HEADER, WRITE_TAG, WAIT_HEADER_READ);
signal tag_release_state_r : tag_release_state_t;
signal tlp_data_part_cnt_r : std_logic_vector(10 downto 0);
signal tlp_first_empty_part_cnt : std_logic_vector(log2(PCIE_DATA_WIDTH, HIBI_DATA_WIDTH)-1 downto 0);
signal tlp_first_empty_part_cnt_r : std_logic_vector(log2(PCIE_DATA_WIDTH, HIBI_DATA_WIDTH)-1 downto 0);
280,6 → 298,9
signal tlp_new_packet_r : std_logic;
signal ipkt_valid_r : std_logic;
signal ipkt_tag_r : std_logic_vector(PKT_TAG_WIDTH-1 downto 0);
signal ipkt_tag : std_logic_vector(PKT_TAG_WIDTH-1 downto 0);
-- signal pcie_dma_valid_r : std_logic;
signal tlp_header_fifo_we_r : std_logic;
302,16 → 323,6
signal tlp_data_fifo_rcnt : std_logic_vector(TLP_DATA_FIFO_RCNT_WIDTH-1 downto 0);
-- signal ipkt_re_stall_r : std_logic;
-- synthesis translate_off
signal debug_pcie_rx_sop_r : std_logic;
signal debug_tlp_hdri_addr_size_r : std_logic;
signal debug_tlp_hdri_not_qword_aligned_r : std_logic;
signal debug_tlp_hdri_length_r : std_logic_vector(PCIE_RW_LENGTH_WIDTH-1 downto 0);
signal debug_tlp_hdri_addr_size : std_logic;
signal debug_tlp_hdri_not_qword_aligned : std_logic;
signal debug_tlp_hdri_length : std_logic_vector(PCIE_RW_LENGTH_WIDTH-1 downto 0);
-- synthesis translate_on
signal debug_start_r : std_logic;
signal debug_started_r : std_logic;
begin
333,6 → 344,10
-- tag_fifo_re_out <= tag_fifo_re_r;
tag_release_out <= tag_release_r;
tag_release_res_out <= tlp_hdro_tag;
tag_release_amount_out <= tlp_hdro_length(PCIE_RD_LENGTH_WIDTH-1 downto 0);
pcie_rx_eop <= pcie_rx_eop_in;
debug_out <= debug_start_r;
414,7 → 429,9
end generate;
process (pcie_rx_data, tlp_hdri_has_data, tlp_hdri_type, tlp_hdri_addr_size, tlp_hdri_addr_63_2, tlp_hdri_length, tlp_hdri_word_addr, tlp_hdri_first_be, tlp_hdri_last_be,
tlp_hdri_length_0, pcie_rx_bardec_in, tlp_hdri_byte_cnt, pcie_rx_sop, tlp_hdri_not_qword_aligned_r, tlp_hdri_not_qword_aligned, tlp_hdri_is_rdata)
tlp_hdri_length_0, pcie_rx_bardec_in, tlp_hdri_byte_cnt, pcie_rx_sop, tlp_hdri_not_qword_aligned_r, tlp_hdri_not_qword_aligned, tlp_hdri_is_rdata, tlp_hdri_tag,
ipkt_re_in, ipkt_valid_r, tlp_hdro_has_data, tlp_data_fifo_re, tlp_data_fifo_section_end_r, tlp_last_part_r, tag_release_state_r, tlp_hdro_tag, ipkt_tag_r,
tlp_hdro_is_rdata)
begin
tlp_hdri_is_write <= '0';
tlp_hdri_is_read_req <= '0';
423,12 → 440,6
tlp_hdri_req_id <= pcie_rx_data(63 downto 48);
tlp_hdri_tag <= pcie_rx_data(45 downto 40);
-- if ( ((tlp_hdri_is_rdata = '0') and (pcie_rx_bardec_in = PCIE_DMA_BAR)) or ((tlp_hdri_is_rdata = '1') and (tlp_hdri_tag(PCIE_LOWER_TAG_WIDTH) = '1')) ) then
-- tlp_hdri_pcie_dma <= '1';
-- else
-- tlp_hdri_pcie_dma <= '0';
-- end if;
if (pcie_rx_bardec_in(0) = '1') then
pcie_rx_bar <= "000";
elsif (pcie_rx_bardec_in(1) = '1') then
549,27 → 560,22
tlp_hdri_length_1 <= tlp_hdri_length_0;
end if;
end process;
-- synthesis translate_off
gen_sim_0 : if (ENABLE_SIM = 1) generate
process (pcie_rx_sop, tlp_hdri_length_1, tlp_hdri_addr_size, tlp_hdri_not_qword_aligned, debug_tlp_hdri_length_r, debug_tlp_hdri_addr_size_r,
debug_tlp_hdri_not_qword_aligned_r)
begin
if (pcie_rx_sop = '1') then
debug_tlp_hdri_length <= tlp_hdri_length_1;
debug_tlp_hdri_addr_size <= tlp_hdri_addr_size;
debug_tlp_hdri_not_qword_aligned <= tlp_hdri_not_qword_aligned;
if ( ((ipkt_re_in = '1') and (ipkt_valid_r = '1') and (tlp_hdro_has_data = '0'))
or ((tlp_data_fifo_re = '1') and (tlp_data_fifo_section_end_r = '1') and (tlp_last_part_r = '1')
and not((tag_release_state_r = WAIT_HEADER) and (tlp_hdro_is_rdata = '1'))) ) then
tlp_header_fifo_re <= '1';
else
debug_tlp_hdri_length <= debug_tlp_hdri_length_r;
debug_tlp_hdri_addr_size <= debug_tlp_hdri_addr_size_r;
debug_tlp_hdri_not_qword_aligned <= debug_tlp_hdri_not_qword_aligned_r;
tlp_header_fifo_re <= '0';
end if;
if (tlp_hdro_is_rdata = '0') then
ipkt_tag <= (others => '0');
ipkt_tag(PCIE_TAG_WIDTH-1 downto 0) <= tlp_hdro_tag;
else
ipkt_tag <= ipkt_tag_r;
end if;
end process;
end generate;
-- synthesis translate_on
tlp_hdro_has_data <= tlp_hdro_is_write or tlp_hdro_is_rdata;
pcie_rx_ready_out <= pcie_rx_ready;
578,11 → 584,9
ipkt_is_write_out <= tlp_hdro_is_write;
ipkt_is_read_req_out <= tlp_hdro_is_read_req;
ipkt_is_rdata_out <= tlp_hdro_is_rdata;
-- ipkt_relax_ord_out <= tlp_hdro_relax_ord;
-- ipkt_addr_size_out <= tlp_hdro_addr_size;
ipkt_length_out <= tlp_hdro_length;
ipkt_req_id_out <= tlp_hdro_req_id;
ipkt_tag_out <= tlp_hdro_tag;
ipkt_tag_out <= ipkt_tag; --tlp_hdro_tag;
ipkt_bar_out <= tlp_hdro_bar;
ipkt_addr_out <= tlp_hdro_addr;
591,9 → 595,6
-- ipkt_byte_cnt_out <= tlp_hdro_extra_data(PCIE_RW_LENGTH_WIDTH-1 downto 0);
ipkt_valid_out <= ipkt_valid_r;
-- ipkt_one_d_out <= tlp_data_fifo_one_d;
-- ipkt_first_part_out <= tlp_first_part_r;
-- ipkt_last_part_out <= tlp_last_part_r;
ipkt_data_out <= tlp_data_fifo_rdata;
process (clk_pcie, rst_n)
610,26 → 611,14
tlp_hdri_is_read_req_r <= '0';
tlp_hdri_is_rdata_r <= '0';
tlp_hdri_is_other_r <= '0';
-- tlp_hdri_relax_ord_r <= '0';
tlp_hdri_addr_size_r <= '0';
tlp_hdri_not_qword_aligned_r <= '0';
tlp_hdri_addr_r <= (others => '0');
-- tag_fifo_re_r <= '0';
-- synthesis translate_off
debug_pcie_rx_sop_r <= '0';
debug_tlp_hdri_length_r <= (others => '0');
debug_tlp_hdri_addr_size_r <= '0';
debug_tlp_hdri_not_qword_aligned_r <= '0';
-- synthesis translate_on
elsif (clk_pcie'event and clk_pcie = '1') then
-- tag_fifo_re_r <= '0';
if ((tlp_hdri_is_other = '1') or (tlp_hdri_is_other_r = '1') or ((tlp_header_fifo_cnt <= TLP_HEADER_FIFO_CNT_LIMIT)
and (tlp_data_fifo_wcnt <= TLP_DATA_FIFO_CNT_LIMIT))) then
if ( (tlp_hdri_is_other = '1') or (tlp_hdri_is_other_r = '1') or ((tlp_header_fifo_cnt <= TLP_HEADER_FIFO_CNT_LIMIT)
and (tlp_data_fifo_wcnt <= TLP_DATA_FIFO_CNT_LIMIT)) ) then
pcie_rx_ready_r <= '1';
else
pcie_rx_ready_r <= '0';
637,31 → 626,11
tlp_data_fifo_wdata_r <= pcie_rx_data;
tlp_header_fifo_we_r <= '0';
-- synthesis translate_off
if (ENABLE_SIM = 1) then
debug_pcie_rx_sop_r <= pcie_rx_sop;
end if;
-- synthesis translate_on
if ((pcie_rx_valid = '1') and (pcie_rx_sop = '1') and (tlp_hdri_is_other = '0')) then
tlp_header_fifo_we_r <= '1';
-- if (tlp_hdri_is_rdata = '1') then
-- tag_fifo_re_r <= '1';
-- end if;
tlp_hdri_not_qword_aligned_r <= tlp_hdri_not_qword_aligned;
-- synthesis translate_off
if (ENABLE_SIM = 1) then
debug_tlp_hdri_length_r <= tlp_hdri_length_1;
debug_tlp_hdri_addr_size_r <= tlp_hdri_addr_size;
debug_tlp_hdri_not_qword_aligned_r <= tlp_hdri_not_qword_aligned;
end if;
-- synthesis translate_on
else
tlp_header_fifo_we_r <= '0';
end if;
if ( (pcie_rx_valid = '1') and ( (pcie_rx_sop = '0') or ((tlp_hdri_has_data and pcie_rx_sop and tlp_hdri_not_qword_aligned) = '1') )
672,102 → 641,10
end if;
if ((pcie_rx_sop = '1') or (ENABLE_SIM = 0)) then
-- if (tlp_hdri_is_rdata = '0') then
tlp_hdri_length_r <= tlp_hdri_length_1;
-- else
-- tlp_hdri_length_r <= tlp_hdri_byte_cnt_0;
-- end if;
end if;
-- synthesis translate_off
if (ENABLE_SIM = 1) then
if (tlp_hdri_not_qword_aligned_0 = '1') then
if ((pcie_rx_sop = '1') and (tlp_hdri_addr_size = '0')) then
tlp_data_fifo_wdata_r(95 downto 0) <= (others => 'X');
end if;
end if;
if (tlp_hdri_not_qword_aligned_0 = '1') then
if ((debug_pcie_rx_sop_r = '1') and (pcie_rx_sop = '0') and (debug_tlp_hdri_addr_size = '1')) then
tlp_data_fifo_wdata_r(31 downto 0) <= (others => 'X');
end if;
if (debug_tlp_hdri_addr_size = '0') then
if (pcie_rx_eop = '1') then
if (tlp_hdri_length_r(1 downto 0) = "00") then
if (tlp_hdri_length_r(3 downto 2) = "10") then
tlp_data_fifo_wdata_r(127 downto 32) <= (others => 'X');
elsif (tlp_hdri_length_r(3 downto 2) = "11") then
tlp_data_fifo_wdata_r(127 downto 64) <= (others => 'X');
elsif (tlp_hdri_length_r(3 downto 2) = "00") then
tlp_data_fifo_wdata_r(127 downto 96) <= (others => 'X');
end if;
else
if (tlp_hdri_length_r(3 downto 2) = "01") then
tlp_data_fifo_wdata_r(127 downto 32) <= (others => 'X');
elsif (tlp_hdri_length_r(3 downto 2) = "10") then
tlp_data_fifo_wdata_r(127 downto 64) <= (others => 'X');
elsif (tlp_hdri_length_r(3 downto 2) = "11") then
tlp_data_fifo_wdata_r(127 downto 96) <= (others => 'X');
end if;
end if;
end if;
else
if (pcie_rx_eop = '1') then
if (tlp_hdri_length_r(1 downto 0) = "00") then
if (tlp_hdri_length_r(3 downto 2) = "00") then
tlp_data_fifo_wdata_r(127 downto 32) <= (others => 'X');
elsif (tlp_hdri_length_r(3 downto 2) = "01") then
tlp_data_fifo_wdata_r(127 downto 64) <= (others => 'X');
elsif (tlp_hdri_length_r(3 downto 2) = "10") then
tlp_data_fifo_wdata_r(127 downto 96) <= (others => 'X');
end if;
else
if (tlp_hdri_length_r(3 downto 2) = "11") then
tlp_data_fifo_wdata_r(127 downto 32) <= (others => 'X');
elsif (tlp_hdri_length_r(3 downto 2) = "00") then
tlp_data_fifo_wdata_r(127 downto 64) <= (others => 'X');
elsif (tlp_hdri_length_r(3 downto 2) = "01") then
tlp_data_fifo_wdata_r(127 downto 96) <= (others => 'X');
end if;
end if;
end if;
end if;
else
if (pcie_rx_eop = '1') then
if (tlp_hdri_length_r(1 downto 0) = "00") then
if (tlp_hdri_length_r(3 downto 2) = "01") then
tlp_data_fifo_wdata_r(127 downto 32) <= (others => 'X');
elsif (tlp_hdri_length_r(3 downto 2) = "10") then
tlp_data_fifo_wdata_r(127 downto 64) <= (others => 'X');
elsif (tlp_hdri_length_r(3 downto 2) = "11") then
tlp_data_fifo_wdata_r(127 downto 96) <= (others => 'X');
end if;
else
if (tlp_hdri_length_r(3 downto 2) = "00") then
tlp_data_fifo_wdata_r(127 downto 32) <= (others => 'X');
elsif (tlp_hdri_length_r(3 downto 2) = "01") then
tlp_data_fifo_wdata_r(127 downto 64) <= (others => 'X');
elsif (tlp_hdri_length_r(3 downto 2) = "10") then
tlp_data_fifo_wdata_r(127 downto 96) <= (others => 'X');
end if;
end if;
end if;
end if;
end if;
-- synthesis translate_on
tlp_hdri_addr_r <= tlp_hdri_addr;
-- if (tlp_hdri_is_rdata = '1') then
-- tlp_hdri_addr_r(6 downto 0) <= tlp_hdri_cmp_id & tlp_hdri_lower_addr;
-- end if;
-- if (tlp_hdri_is_rdata = '0') then
-- tlp_hdri_tag_r <= '0' & tlp_hdri_tag;
-- else
-- tlp_hdri_tag_r <= tag_fifo_data_in;
-- end if;
tlp_hdri_req_id_r <= tlp_hdri_req_id;
tlp_hdri_tag_r <= tlp_hdri_tag;
tlp_hdri_bar_r <= pcie_rx_bar;
780,9 → 657,6
tlp_hdri_addr_size_r <= tlp_hdri_addr_size;
end if;
-- tlp_hdri_relax_ord_r <= tlp_hdri_relax_ord;
-- tlp_hdri_not_qword_aligned_r <= tlp_hdri_not_qword_aligned;
-- tlp_hdri_pcie_dma_r <= tlp_hdri_pcie_dma;
end if;
end process;
905,7 → 779,6
tlp_data_part_cnt_r <= (others => '0');
tlp_first_empty_part_cnt_r <= (others => '0');
tlp_last_empty_part_cnt_r <= (others => '0');
-- tlp_first_part_r <= '0';
tlp_last_part_r <= '0';
tlp_data_fifo_section_r <= (others => '0');
tlp_data_fifo_section_end_r <= '0';
914,10 → 787,13
ipkt_valid_r <= '0';
-- ipkt_re_stall_r <= '0';
tlp_part_state_r <= NO_PACKET;
tag_release_state_r <= WAIT_HEADER;
tag_release_r <= '0';
ipkt_tag_r <= (others => '0');
elsif (clk'event and clk = '1') then
-- tlp_first_part_r <= tlp_first_part_r;
tlp_last_part_r <= tlp_last_part_r;
tlp_data_fifo_re_r <= '0';
if ( (tlp_header_fifo_empty = '0') and (tlp_data_fifo_empty = '0') and not((tlp_data_fifo_one_d = '1') and (tlp_data_fifo_re_r = '1')) ) then
932,14 → 808,11
when NO_PACKET =>
if ((tlp_header_fifo_empty = '0') and (tlp_hdro_has_data = '0')) then
tlp_new_packet_r <= '0';
-- tlp_data_part_cnt_r <= "00000000000"
-- tlp_first_part_r <= '1';
tlp_last_part_r <= '1';
tlp_part_state_r <= LAST_PART;
ipkt_valid_r <= '1';
elsif ((tlp_header_fifo_empty = '0') and (tlp_data_fifo_empty = '0')) then
elsif ( (tlp_header_fifo_empty = '0') and (tlp_data_fifo_empty = '0') and not((tag_release_state_r = WAIT_HEADER) and (tlp_hdro_is_rdata = '1')) ) then
tlp_new_packet_r <= '0';
if ((tlp_first_empty_part_cnt > 0) and (tlp_new_packet_r = '1')) then
957,11 → 830,9
tlp_last_empty_part_cnt_r <= tlp_last_empty_part_cnt;
if (tlp_hdro_length <= HIBI_DATA_BYTE_WIDTH) then
-- tlp_first_part_r <= '1';
tlp_last_part_r <= '1';
tlp_part_state_r <= LAST_PART;
else
-- tlp_first_part_r <= '1';
tlp_last_part_r <= '0';
tlp_part_state_r <= FIRST_PART;
end if;
968,7 → 839,6
ipkt_valid_r <= '1';
end if;
else
tlp_new_packet_r <= '1';
end if;
979,7 → 849,6
else
tlp_data_fifo_re_r <= '1';
end if;
tlp_first_empty_part_cnt_r <= tlp_first_empty_part_cnt_r - 1;
when READ_LAST_EMPTY_PARTS =>
988,101 → 857,45
else
tlp_data_fifo_re_r <= '1';
end if;
tlp_last_empty_part_cnt_r <= tlp_last_empty_part_cnt_r - 1;
when FIRST_PART =>
if ((ipkt_re_in = '1') and (ipkt_valid_r = '1')) then
-- if (tlp_hdro_has_data = '1') then
-- tlp_data_fifo_re_r <= '1';
-- end if;
if (tlp_data_part_cnt_r = 2) then
-- tlp_first_part_r <= '0';
tlp_last_part_r <= '1';
tlp_part_state_r <= LAST_PART;
else
-- tlp_first_part_r <= '0';
tlp_part_state_r <= MIDDLE_PART;
end if;
tlp_data_part_cnt_r <= tlp_data_part_cnt_r - 1;
end if;
ipkt_valid_r <= ipkt_valid_v;
when MIDDLE_PART =>
if ((ipkt_re_in = '1') and (ipkt_valid_r = '1')) then
-- if (tlp_hdro_has_data = '1') then
-- tlp_data_fifo_re_r <= '1';
-- end if;
if (tlp_data_part_cnt_r = 2) then
tlp_last_part_r <= '1';
tlp_part_state_r <= LAST_PART;
end if;
tlp_data_part_cnt_r <= tlp_data_part_cnt_r - 1;
end if;
ipkt_valid_r <= ipkt_valid_v;
when LAST_PART =>
tlp_new_packet_r <= '1';
if ((ipkt_re_in = '1') and (ipkt_valid_r = '1')) then
-- if (tlp_hdro_has_data = '1') then
-- tlp_data_fifo_re_r <= '1';
-- end if;
if ((tlp_last_empty_part_cnt_r > 0) and (tlp_hdro_has_data = '1')) then
tlp_part_state_r <= READ_LAST_EMPTY_PARTS;
else
tlp_part_state_r <= NO_PACKET;
-- if ((tlp_header_fifo_cnt = 1) or (tlp_data_fifo_rcnt = 1)) then
-- tlp_first_part_r <= '0';
-- tlp_last_part_r <= '0';
--
-- tlp_part_state_r <= NO_PACKET;
--
-- else
-- if (tlp_hdro_has_data = '0') then
-- -- tlp_data_part_cnt_r <= "00000000000";
-- tlp_first_part_r <= '1';
-- tlp_last_part_r <= '1';
-- -- tlp_part_state_r <= LAST_PART;
--
-- else
-- if (tlp_hdro_length(HIBI_DATA_WORD_ADDR_WIDTH-1 downto 0) = 0) then
-- tlp_data_part_cnt_r <= tlp_hdro_length(PCIE_RW_LENGTH_WIDTH-1 downto HIBI_DATA_WORD_ADDR_WIDTH);
-- else
-- tlp_data_part_cnt_r <= tlp_hdro_length(PCIE_RW_LENGTH_WIDTH-1 downto HIBI_DATA_WORD_ADDR_WIDTH) + 1; -- this addition isn't needed and can be optimized
-- end if;
--
-- if (tlp_hdro_length <= HIBI_DATA_BYTE_WIDTH) then
-- tlp_first_part_r <= '1';
-- tlp_last_part_r <= '1';
-- -- tlp_part_state_r <= LAST_PART;
-- else
-- tlp_first_part_r <= '1';
-- tlp_last_part_r <= '0';
-- tlp_part_state_r <= FIRST_PART;
-- end if;
-- end if;
-- end if;
end if;
else
ipkt_valid_r <= '1';
end if;
end case;
if (tlp_data_fifo_re = '1') then
tlp_data_fifo_section_r <= tlp_data_fifo_section_r + 1;
if (tlp_data_fifo_section_r = 2) then
tlp_data_fifo_section_end_r <= '1';
else
1089,6 → 902,26
tlp_data_fifo_section_end_r <= '0';
end if;
end if;
tag_release_r <= '0';
case tag_release_state_r is
when WAIT_HEADER =>
if ((tlp_header_fifo_empty = '0') and (tlp_hdro_is_rdata = '1') and (tag_release_ready_in = '1')) then
tag_release_r <= '1';
tag_release_state_r <= WRITE_TAG;
end if;
when WRITE_TAG =>
ipkt_tag_r <= tag_release_data_in;
tag_release_state_r <= WAIT_HEADER_READ;
when WAIT_HEADER_READ =>
if (tlp_header_fifo_re = '1') then
tag_release_state_r <= WAIT_HEADER;
end if;
end case;
end if;
end process;
1103,7 → 936,7
-- output read: tlp_header_fifo_re
-----------------------------------------------------------------------------------------
tlp_header_fifo : entity work.fifo_dc_dw
tlp_header_fifo : entity work.alt_fifo_dc_dw
generic map ( DATA_WIDTH => TLP_HEADER_FIFO_DATA_WIDTH,
FIFO_LENGTH => TLP_HEADER_FIFO_SIZE,
CNT_WIDTH => TLP_HEADER_FIFO_CNT_WIDTH,
1124,7 → 957,7
rdata_out => tlp_header_fifo_rdata,
wcount_out => tlp_header_fifo_cnt );
tlp_header_fifo_re <= (ipkt_re_in and ipkt_valid_r and not(tlp_hdro_has_data)) or (tlp_data_fifo_re and tlp_data_fifo_section_end_r and tlp_last_part_r);
-- tlp_header_fifo_re <= (ipkt_re_in and ipkt_valid_r and not(tlp_hdro_has_data)) or (tlp_data_fifo_re and tlp_data_fifo_section_end_r and tlp_last_part_r);
tlp_header_fifo_wdata(TLP_HDR_LENGTH_U downto TLP_HDR_LENGTH_L) <= tlp_hdri_length_r;
tlp_header_fifo_wdata(TLP_HDR_TAG_U downto TLP_HDR_TAG_L) <= tlp_hdri_tag_r;
1163,7 → 996,7
-- output read: tlp_header_fifo_re
-----------------------------------------------------------------------------------------
tlp_data_fifo : entity work.fifo_dc_dw
tlp_data_fifo : entity work.alt_fifo_dc_dw
generic map ( DATA_WIDTH => PCIE_DATA_WIDTH,
FIFO_LENGTH => TLP_DATA_FIFO_SIZE,
CNT_WIDTH => TLP_DATA_FIFO_CNT_WIDTH,
/funbase_ip_library/trunk/TUT/ip.hwp.interface/pcie/pcie_to_hibi.comp/2.0/hdl/pkt_buf.vhd
1,37 → 1,44
-------------------------------------------------------------------------------
-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
-------------------------------------------------------------------------------
-- Title : Generic packet buffer
-- Project :
-- Project : Funbase
-------------------------------------------------------------------------------
-- File : pkt_buf.vhd
-- Author :
-- Company :
-- Last update: 27.05.2011
-- Version : 0.6
-- Author : Juha Arvio
-- Company : TUT
-- Last update: 05.10.2011
-- Version : 0.91
-- Platform :
-------------------------------------------------------------------------------
-- Description:
--
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 25.11.2010 0.1 arvio Created
-- 05.10.2011 0.91 arvio
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This file is a part of a free IP-block: you can redistribute it and/or modify
-- it under the terms of the Lesser GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This IP-block is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- Lesser GNU General Public License for more details.
--
-- You should have received a copy of the Lesser GNU General Public License
-- along with Transaction Generator. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
295,7 → 302,7
end process;
free_pkt_buf_fifo : entity work.fifo_sc
free_pkt_buf_fifo : entity work.alt_fifo_sc
generic map ( DATA_WIDTH => BUFFERS_WIDTH,
FIFO_LENGTH => BUFFERS,
CNT_WIDTH => log2_ceil(BUFFERS-1) )
313,7 → 320,7
buf_filled_we <= buf_part_filled or buf_filled;
buf_filled_wdata <= buf_part_filled_size & buf_part_filled_index & buf_part_filled_type;
pkt_buf_filled_fifo : entity work.fifo_sc
pkt_buf_filled_fifo : entity work.alt_fifo_sc
generic map ( DATA_WIDTH => BUF_PART_SIZE_WIDTH+1+BUFFERS_WIDTH+BUF_TYPE_WIDTH,
FIFO_LENGTH => BUFFERS*BUF_PARTS,
CNT_WIDTH => log2_ceil(BUFFERS*BUF_PARTS-1) )
383,7 → 390,7
------------------------------------------------------------------------------------------
-- packet buffer memory
------------------------------------------------------------------------------------------
pkt_buf_mem : entity work.onchip_mem_sc --work.onchip_mem_dc_dw
pkt_buf_mem : entity work.alt_mem_sc --work.alt_mem_dc_dw
generic map ( --MEM_PORTS => 2,
DATA_WIDTH => DATA_WIDTH,
--DATA_1_WIDTH => RDATA_WIDTH,
/funbase_ip_library/trunk/TUT/ip.hwp.interface/pcie/pcie_to_hibi.comp/2.0/hdl/pcie_tx.vhd
1,37 → 1,46
-------------------------------------------------------------------------------
-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
-------------------------------------------------------------------------------
-- Title : PCIe TX
-- Project :
-- Project : Funbase
-------------------------------------------------------------------------------
-- File : pcie_tx.vhd
-- Author :
-- Company :
-- Last update: 15.03.2011
-- Version : 0.1
-- Author : Juha Arvio
-- Company : TUT
-- Last update: 05.10.2011
-- Version : 0.91
-- Platform :
-------------------------------------------------------------------------------
-- Description:
--
-- converts a packet interface into a
-- PCIe TX interface (Altera PCIe compiler's Avalon ST interface)
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 11.11.2010 0.1 arvio Created
-- 05.10.2011 0.91 arvio
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This file is a part of a free IP-block: you can redistribute it and/or modify
-- it under the terms of the Lesser GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This IP-block is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- Lesser GNU General Public License for more details.
--
-- You should have received a copy of the Lesser GNU General Public License
-- along with Transaction Generator. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
49,7 → 58,7
PCIE_RW_LENGTH_WIDTH : integer := 13;
PCIE_ID_WIDTH : integer := 16;
PCIE_TAG_WIDTH : integer := 6;
-- PKT_TAG_WIDTH : integer := 9;
PKT_TAG_WIDTH : integer := 8;
PCIE_CRED_WIDTH : integer := 66;
PCIE_DATA_WIDTH : integer := 128;
56,6 → 65,7
PCIE_ADDR_WIDTH : integer := 32;
PCIE_FORCE_MAX_RW_LENGTH : integer := 0;
PCIE_MAX_RW_LENGTH : integer := 256;
PCIE_RD_LENGTH_WIDTH : integer := 9;
BURST_LATENCY : integer := 2;
PCIE_IRQ_WIDTH : integer := 5;
PCIE_TC_WIDTH : integer := 3 );
73,7 → 83,6
pcie_tx_cred_in : in std_logic_vector(PCIE_CRED_WIDTH-1 downto 0);
pcie_tx_ready_in : in std_logic;
opkt_is_write_in : in std_logic;
opkt_is_read_req_in : in std_logic;
opkt_is_rdata_in : in std_logic;
84,7 → 93,7
-- opkt_byte_cnt_in : in std_logic_vector(PCIE_RW_LENGTH_WIDTH-1 downto 0);
opkt_req_id_in : in std_logic_vector(PCIE_ID_WIDTH-1 downto 0);
-- opkt_cmp_id_in : in std_logic_vector(PCIE_ID_WIDTH-1 downto 0);
opkt_tag_in : in std_logic_vector(PCIE_TAG_WIDTH-1 downto 0);
opkt_tag_in : in std_logic_vector(PKT_TAG_WIDTH-1 downto 0);
-- opkt_first_be_in : in std_logic_vector(3 downto 0);
-- opkt_last_be_in : in std_logic_vector(3 downto 0);
118,12 → 127,15
lmi_we_out : out std_logic;
lmi_ack_in : in std_logic;
lmi_addr_out : out std_logic_vector(11 downto 0);
lmi_data_out : out std_logic_vector(31 downto 0)
lmi_data_out : out std_logic_vector(31 downto 0);
-- tag_fifo_we_out : out std_logic;
-- tag_fifo_full_in : in std_logic;
-- tag_fifo_data_out : out std_logic_vector(PKT_TAG_WIDTH-1 downto 0)
);
debug_ready_error_out : out std_logic;
tag_reserve_out : out std_logic;
tag_reserve_ready_in : in std_logic;
tag_reserve_res_in : in std_logic_vector(PCIE_TAG_WIDTH-1 downto 0);
tag_reserve_amount_out : out std_logic_vector(PCIE_RD_LENGTH_WIDTH-1 downto 0);
tag_reserve_data_out : out std_logic_vector(PKT_TAG_WIDTH-1 downto 0) );
 
end pcie_tx;
 
198,7 → 210,7
constant TLP_HDR_LENGTH_L : integer := 0;
constant TLP_HDR_LENGTH_U : integer := TLP_HDR_LENGTH_L + PCIE_RW_LENGTH_WIDTH - 1;
constant TLP_HDR_TAG_L : integer := TLP_HDR_LENGTH_U + 1;
constant TLP_HDR_TAG_U : integer := TLP_HDR_TAG_L + PCIE_TAG_WIDTH - 1;
constant TLP_HDR_TAG_U : integer := TLP_HDR_TAG_L + PKT_TAG_WIDTH - 1;
constant TLP_HDR_IS_WRITE_L : integer := TLP_HDR_TAG_U + 1;
constant TLP_HDR_IS_WRITE_U : integer := TLP_HDR_IS_WRITE_L;
constant TLP_HDR_IS_READ_REQ_L : integer := TLP_HDR_IS_WRITE_U + 1;
241,7 → 253,7
signal tlp_hdro_length : std_logic_vector(PCIE_RW_LENGTH_WIDTH-1 downto 0);
signal tlp_hdro_word_length : std_logic_vector(PCIE_RW_LENGTH_WIDTH-3 downto 0);
signal tlp_hdro_byte_cnt : std_logic_vector(11 downto 0);
signal tlp_hdro_tag : std_logic_vector(PCIE_TAG_WIDTH-1 downto 0);
signal tlp_hdro_tag : std_logic_vector(PKT_TAG_WIDTH-1 downto 0);
signal tlp_hdro_req_id : std_logic_vector(PCIE_ID_WIDTH-1 downto 0);
-- signal tlp_hdro_cmp_id : std_logic_vector(PCIE_ID_WIDTH-1 downto 0);
signal tlp_hdro_addr_size : std_logic;
258,7 → 270,7
signal tlp_hdri_addr_size_r : std_logic;
signal tlp_hdri_not_qword_aligned : std_logic;
signal tlp_hdri_not_qword_aligned_r : std_logic;
signal tlp_hdri_tag_r : std_logic_vector(PCIE_TAG_WIDTH-1 downto 0);
signal tlp_hdri_tag_r : std_logic_vector(PKT_TAG_WIDTH-1 downto 0);
signal tlp_hdri_req_id_r : std_logic_vector(PCIE_ID_WIDTH-1 downto 0);
signal tlp_hdri_is_write_r : std_logic;
signal tlp_hdri_is_read_req_r : std_logic;
266,6 → 278,7
signal tl_cfg_ctl_wr_d1_r : std_logic;
signal tl_cfg_ctl_wr_d1_0_r : std_logic;
signal tl_cfg_ctl_wr_d2_0_r : std_logic;
signal tlp_header_fifo_wdata : std_logic_vector(TLP_HEADER_FIFO_DATA_WIDTH-1 downto 0);
signal tlp_header_fifo_rdata : std_logic_vector(TLP_HEADER_FIFO_DATA_WIDTH-1 downto 0);
277,10 → 290,10
type tlp_part_state_t is (WAIT_OPKT, BURST_DELAY, WRITE_FIRST_EMPTY_PARTS, WRITE_LAST_EMPTY_PARTS, FIRST_PART, MIDDLE_PART, LAST_PART);
signal tlp_part_state_r : tlp_part_state_t;
type pcie_tx_state_t is (WAIT_TX, WRITE_TX_DATA);
type pcie_tx_state_t is (WAIT_TX, READ_REQ, WRITE_TX_DATA);
signal pcie_tx_state_r : pcie_tx_state_t;
type pcie_irq_state_t is (WAIT_IRQ, WAIT_ACK);
type pcie_irq_state_t is (WAIT_IRQ, WAIT_ACK, IRQ_FIFO_DELAY);
signal pcie_irq_state_r : pcie_irq_state_t;
signal pcie_length_r : std_logic_vector(PCIE_RW_LENGTH_WIDTH-1 downto 0);
303,10 → 316,10
signal pcie_tx_empty_r : std_logic;
-- signal tag_fifo_we_r : std_logic;
signal pcie_tag : std_logic_vector(PCIE_TAG_WIDTH-3 downto 0);
signal pcie_wr_req_tag_r : std_logic_vector(PCIE_TAG_WIDTH-3 downto 0);
signal pcie_rd_req_tag_r : std_logic_vector(PCIE_TAG_WIDTH-3 downto 0);
signal pcie_rd_cpl_tag_r : std_logic_vector(PCIE_TAG_WIDTH-3 downto 0);
signal pcie_tag : std_logic_vector(PCIE_TAG_WIDTH-1 downto 0);
-- signal pcie_wr_req_tag_r : std_logic_vector(PCIE_TAG_WIDTH-3 downto 0);
signal pcie_rd_req_tag_r : std_logic_vector(PCIE_TAG_WIDTH-1 downto 0);
-- signal pcie_rd_cpl_tag_r : std_logic_vector(PCIE_TAG_WIDTH-1 downto 0);
signal pcie_tx_ready : std_logic;
signal pcie_tx_data_half_r : std_logic;
383,8 → 396,14
signal hdr_done_r : std_logic;
signal data_done_r : std_logic;
signal tag_reserve_r : std_logic;
signal tag_reserve_ready_r : std_logic;
-- signal debug_0_r : std_logic_vector(7 downto 0);
-- signal debug_1_r : std_logic;
signal debug_ready_cnt_r : std_logic_vector(6 downto 0);
signal debug_ready_error_r : std_logic;
begin
tlp_hdri_has_data <= opkt_is_write_in or opkt_is_rdata_in;
tlp_hdro_has_data <= tlp_hdro_is_write or tlp_hdro_is_rdata;
427,6 → 446,35
lmi_addr_out <= (others => '0');
lmi_data_out <= (others => '0');
tag_reserve_out <= tag_reserve_r;
tag_reserve_amount_out <= tlp_hdro_length(PCIE_RD_LENGTH_WIDTH-1 downto 0);
tag_reserve_data_out <= tlp_hdro_tag;
-- tag_reserve_res_out <= tlp_hdro_tag(PCIE_TAG_WIDTH-1 downto PCIE_TAG_WIDTH-2) & pcie_rd_req_tag_r;
debug_ready_error_out <= debug_ready_error_r;
process (clk_pcie, rst_n)
begin
if (rst_n = '0') then
debug_ready_cnt_r <= (others => '0');
debug_ready_error_r <= '0';
elsif (clk_pcie'event and clk_pcie = '1') then
if (pcie_tx_ready_in = '0') then
debug_ready_cnt_r <= debug_ready_cnt_r + 1;
else
debug_ready_cnt_r <= (others => '0');
end if;
if (debug_ready_cnt_r > 64) then
debug_ready_error_r <= '1';
else
debug_ready_error_r <= '0';
end if;
end if;
end process;
pcie_data_128 : if (PCIE_DATA_WIDTH = 128) generate
process (pcie_tx_data, pcie_tx_ready_in, pcie_tx_sop_r, pcie_tx_eop_r) --, debug_1_r)
begin
497,8 → 545,8
process (opkt_addr_in, tlp_data_fifo_rdata, tlp_hdro_length, tlp_hdro_extra_data, tlp_hdro_type, tlp_hdro_addr_size, tlp_hdro_has_data, pcie_id_r, tlp_hdro_is_rdata,
tlp_hdro_first_be, tlp_hdro_last_be, tlp_hdro_tag, tlp_hdro_req_id, pcie_tx_sop_r, tlp_hdro_not_qword_aligned, opkt_length_left_r, tlp_hdro_word_length, opkt_addr_r,
opkt_is_rdata_in, opkt_is_read_req_in, opkt_ready_r, opkt_ready_d1_r, opkt_burst_we_in, tlp_data_fifo_we_r, tlp_data_fifo_burst_we_r, pcie_wr_req_tag_r, pcie_rd_req_tag_r,
pcie_rd_cpl_tag_r, tlp_hdro_is_write, tlp_hdro_is_read_req, pcie_tag)
opkt_is_rdata_in, opkt_is_read_req_in, opkt_ready_r, opkt_ready_d1_r, opkt_burst_we_in, tlp_data_fifo_we_r, tlp_data_fifo_burst_we_r, pcie_rd_req_tag_r,
tlp_hdro_is_write, tlp_hdro_is_read_req, pcie_tag)
begin
if (tlp_hdro_length = 0) then
tlp_hdro_first_be <= "0000";
624,7 → 672,7
pcie_tx_data(35 downto 32) <= tlp_hdro_first_be;
pcie_tx_data(39 downto 36) <= tlp_hdro_last_be;
pcie_tx_data(47 downto 40) <= (others => '0');
pcie_tx_data(39 + PCIE_TAG_WIDTH downto 40) <= tlp_hdro_tag(PCIE_TAG_WIDTH-1 downto PCIE_TAG_WIDTH-2) & pcie_tag;
pcie_tx_data(39 + PCIE_TAG_WIDTH downto 40) <= pcie_tag;
if (tlp_hdro_addr_size = '0') then
pcie_tx_data(95 downto 64) <= tlp_hdro_extra_data(31 downto 2) & "00";
if ((tlp_hdro_has_data = '1') and (tlp_hdro_not_qword_aligned = '1')) then
683,12 → 731,12
opkt_ready_0 <= opkt_ready_r;
end if;
if (tlp_hdro_is_write = '1') then
pcie_tag <= pcie_wr_req_tag_r;
elsif (tlp_hdro_is_read_req = '1') then
-- if (tlp_hdro_is_write = '1') then
-- pcie_tag <= pcie_wr_req_tag_r;
if (tlp_hdro_is_read_req = '1') then
pcie_tag <= pcie_rd_req_tag_r;
else
pcie_tag <= pcie_rd_cpl_tag_r;
pcie_tag <= (others => '0');
end if;
end process;
804,6 → 852,7
if (rst_n = '0') then
pcie_id_r <= (others => '0');
tl_cfg_ctl_wr_d1_0_r <= '0';
tl_cfg_ctl_wr_d2_0_r <= '0';
app_msi_req_r <= '0';
pcie_irq_re_r <= '0';
pcie_irq_state_r <= WAIT_IRQ;
810,8 → 859,9
elsif (clk_pcie'event and clk_pcie = '1') then
tl_cfg_ctl_wr_d1_0_r <= tl_cfg_ctl_wr;
tl_cfg_ctl_wr_d2_0_r <= tl_cfg_ctl_wr_d1_0_r;
if (tl_cfg_ctl_wr_d1_0_r /= tl_cfg_ctl_wr) then
if (tl_cfg_ctl_wr_d2_0_r /= tl_cfg_ctl_wr_d1_0_r) then
if (tl_cfg_add = 15) then
pcie_id_r <= tl_cfg_ctl(12 downto 0) & "000";
end if;
819,17 → 869,20
case pcie_irq_state_r is
when WAIT_IRQ =>
-- pcie_irq_re_r <= '0';
if (pcie_irq_empty = '0') then
pcie_irq_re_r <= '1';
app_msi_req_r <= '1';
pcie_irq_state_r <= WAIT_ACK;
end if;
when WAIT_ACK =>
pcie_irq_re_r <= '0';
if (app_msi_ack_in = '1') then
pcie_irq_re_r <= '1';
app_msi_req_r <= '0';
pcie_irq_state_r <= WAIT_IRQ;
pcie_irq_state_r <= IRQ_FIFO_DELAY;
end if;
when IRQ_FIFO_DELAY =>
pcie_irq_re_r <= '0';
pcie_irq_state_r <= WAIT_IRQ;
end case;
-- if (app_msi_req_t_d1_r /= app_msi_req_t_r) then
899,10 → 952,13
pcie_tx_empty_r <= '0';
-- tag_fifo_we_r <= '0';
pcie_wr_req_tag_r <= (others => '0');
-- pcie_wr_req_tag_r <= (others => '0');
pcie_rd_req_tag_r <= (others => '0');
pcie_rd_cpl_tag_r <= (others => '0');
-- pcie_rd_cpl_tag_r <= (others => '0');
tag_reserve_r <= '0';
tag_reserve_ready_r <= '0';
elsif (clk_pcie'event and clk_pcie = '1') then
pcie_tx_valid_r <= '0';
tlp_header_fifo_re_r <= '0';
918,32 → 974,24
case pcie_tx_state_r is
when WAIT_TX =>
if ( not((tlp_header_fifo_two_d = '1') and (tlp_header_fifo_re_r = '1')) ) then
if ( (pcie_tx_ready = '1') and (tlp_header_fifo_empty = '0') and (tlp_hdro_is_read_req = '1') and (cred_np_hdr >= 1) ) then --tlp_hdro_length) ) then
pcie_tx_sop_r <= '1';
pcie_tx_eop_r <= '1';
pcie_tx_valid_r <= '1';
pcie_rd_req_tag_r <= pcie_rd_req_tag_r + 1;
-- tag_fifo_we_r <= '1';
tlp_header_fifo_re_r <= '1';
if ( not((tlp_header_fifo_two_d = '1') and (tlp_header_fifo_re_r = '1')) and (tlp_header_fifo_re_r = '0') ) then
if ((tlp_header_fifo_empty = '0') and (tlp_hdro_is_read_req = '1')) then --tlp_hdro_length) ) then
tag_reserve_r <= '1';
pcie_tx_state_r <= READ_REQ;
-- if ((pcie_tx_ready = '0') or (pcie_tx_valid_r = '0')) then
-- pcie_tx_state_r <= READ_REQ;
-- end if;
elsif ( (pcie_tx_ready = '1') and (tlp_header_fifo_empty = '0') and (tlp_data_fifo_empty = '0') and not((tlp_data_fifo_one_d = '1') and (tlp_data_fifo_re_r = '1'))
and ( ((tlp_hdro_is_rdata = '1') and (cred_cpl_data >= tlp_hdro_word_length)) or ((tlp_hdro_is_write = '1') and (cred_p_data >= tlp_hdro_word_length)) ) ) then
elsif ( (pcie_tx_ready = '1') and (tlp_header_fifo_empty = '0') and (tlp_data_fifo_empty = '0') and not((tlp_data_fifo_rcnt <= 2) and (tlp_data_fifo_re_r = '1'))
and ( ((tlp_hdro_is_rdata = '1') and (cred_cpl_data >= tlp_hdro_word_length)) or ((tlp_hdro_is_write = '1') and (cred_p_data >= tlp_hdro_word_length)) )
and ( (tlp_data_fifo_rcnt > tlp_hdro_word_length(PCIE_RW_LENGTH_WIDTH-3 downto 2)) or
((tlp_data_fifo_rcnt = tlp_hdro_word_length(PCIE_RW_LENGTH_WIDTH-3 downto 2)) and (tlp_hdro_word_length(1 downto 0) = "00")) ) ) then
pcie_tx_sop_r <= '1';
pcie_tx_eop_r <= '0';
pcie_tx_valid_r <= '1';
if (tlp_hdro_is_rdata = '1') then
pcie_rd_cpl_tag_r <= pcie_rd_cpl_tag_r + 1;
else
pcie_wr_req_tag_r <= pcie_wr_req_tag_r + 1;
end if;
-- if (tlp_hdro_is_rdata = '1') then
-- pcie_rd_cpl_tag_r <= pcie_rd_cpl_tag_r + 1;
-- else
-- pcie_wr_req_tag_r <= pcie_wr_req_tag_r + 1;
-- end if;
if (tlp_hdro_not_qword_aligned = '1') then
tlp_data_fifo_re_r <= '1';
961,14 → 1009,24
tlp_header_fifo_re_r <= '1';
end if;
end if;
when READ_REQ =>
if (tag_reserve_ready_in = '1') then
pcie_rd_req_tag_r <= tag_reserve_res_in;
tag_reserve_r <= '0';
tag_reserve_ready_r <= '1';
end if;
-- when READ_REQ =>
-- pcie_tx_valid_r <= '1';
--
-- if (pcie_tx_ready = '1') then
-- pcie_tx_valid_r <= '0';
-- pcie_tx_state_r <= WAIT_TX;
-- end if;
if ( ((tag_reserve_ready_in = '1') or (tag_reserve_ready_r = '1')) and ((pcie_tx_ready = '1') and (cred_np_hdr >= 1)) ) then
tlp_header_fifo_re_r <= '1';
tag_reserve_ready_r <= '0';
pcie_tx_sop_r <= '1';
pcie_tx_eop_r <= '1';
pcie_tx_valid_r <= '1';
-- pcie_rd_req_tag_r <= pcie_rd_req_tag_r + 1;
pcie_tx_state_r <= WAIT_TX;
end if;
when WRITE_TX_DATA =>
pcie_tx_sop_r <= '0';
977,12 → 1035,13
pcie_tx_valid_r <= '1';
tlp_data_fifo_re_r <= '1';
if ( ((pcie_tx_sop_r = '1') and (tlp_hdro_word_length <= 2)) or (((pcie_tx_sop_r = '0')) and (pcie_data_part_cnt_r <= (PCIE_DATA_BYTE_WIDTH/2))) ) then
pcie_tx_empty_r <= '1';
end if;
if (pcie_data_part_cnt_r <= PCIE_DATA_BYTE_WIDTH) then
pcie_packet_cnt_r <= pcie_packet_cnt_r - 1;
if (pcie_data_part_cnt_r <= (PCIE_DATA_BYTE_WIDTH/2)) then
pcie_tx_empty_r <= '1';
end if;
if (pcie_packet_cnt_r = 0) then
pcie_tx_eop_r <= '1';
pcie_tx_state_r <= WAIT_TX;
1483,7 → 1542,7
end if;
end process;
irq_fifo : entity work.fifo_dc_dw
irq_fifo : entity work.alt_fifo_dc_dw
generic map ( DATA_WIDTH => PCIE_IRQ_WIDTH+PCIE_TC_WIDTH,
FIFO_LENGTH => 2,
CNT_WIDTH => 1,
1518,7 → 1577,7
-- output read: tlp_header_fifo_re
-----------------------------------------------------------------------------------------
tlp_header_fifo : entity work.fifo_dc_dw
tlp_header_fifo : entity work.alt_fifo_dc_dw
generic map ( DATA_WIDTH => TLP_HEADER_FIFO_DATA_WIDTH,
FIFO_LENGTH => TLP_HEADER_FIFO_SIZE,
CNT_WIDTH => TLP_HEADER_FIFO_CNT_WIDTH,
1573,7 → 1632,7
-- output read: tlp_header_fifo_re
-----------------------------------------------------------------------------------------
tlp_data_fifo : entity work.fifo_dc_dw
tlp_data_fifo : entity work.alt_fifo_dc_dw
generic map ( DATA_WIDTH => HIBI_DATA_WIDTH,
FIFO_LENGTH => TLP_DATA_FIFO_SIZE,
CNT_WIDTH => TLP_DATA_FIFO_CNT_WIDTH,
/funbase_ip_library/trunk/TUT/ip.hwp.interface/pcie/pcie_to_hibi.comp/2.0/hdl/req_ctrl.vhd
1,37 → 1,44
-------------------------------------------------------------------------------
-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
-------------------------------------------------------------------------------
-- Title : Generic request controller
-- Project :
-- Project : Funbase
-------------------------------------------------------------------------------
-- File : req_ctrl.vhd
-- Author :
-- Company :
-- Last update: 04.02.2011
-- Version : 0.6
-- Author : Juha Arvio
-- Company : TUT
-- Last update: 05.10.2011
-- Version : 0.91
-- Platform :
-------------------------------------------------------------------------------
-- Description:
--
-------------------------------------------------------------------------------
-- Copyright (c) 2010
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 20.10.2010 0.1 arvio Created
-- 05.10.2011 0.91 arvio
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This file is a part of a free IP-block: you can redistribute it and/or modify
-- it under the terms of the Lesser GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This IP-block is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- Lesser GNU General Public License for more details.
--
-- You should have received a copy of the Lesser GNU General Public License
-- along with Transaction Generator. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
499,7 → 506,7
-- - use 1: write req count
-- - write enable: req_cnt_we_p3_r
 
req_cnt_mem : entity work.onchip_mem_sc
req_cnt_mem : entity work.alt_mem_sc
generic map ( DATA_WIDTH => MIN_COMP_REQS_WIDTH+1,
ADDR_WIDTH => COMPONENTS_WIDTH,
MEM_SIZE => COMPONENTS )
530,7 → 537,7
-- - use 1: write valid ack count for the corresponding released ack
-- - write enable: req_cnt_we_p3_r
 
valid_ack_cnt_mem : entity work.onchip_mem_sc
valid_ack_cnt_mem : entity work.alt_mem_sc
generic map ( DATA_WIDTH => MIN_COMP_REQS_WIDTH+1,
ADDR_WIDTH => COMPONENTS_WIDTH,
MEM_SIZE => COMPONENTS )
555,7 → 562,7
valid_ack_data_addr_1 <= ack_rx_comp_p2_r & valid_ack_cnt_p2_r(MIN_COMP_REQS_WIDTH-1 downto 0);
valid_ack_we_1 <= ack_rx_valid_p2_r and ack_rx_p2_r;
valid_ack_data_mem : entity work.onchip_mem_sc
valid_ack_data_mem : entity work.alt_mem_sc
generic map ( DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => COMPONENTS_WIDTH + MIN_COMP_REQS_WIDTH,
MEM_SIZE => COMPONENTS*MIN_COMP_REQS )
573,7 → 580,7
-- rdata_1_out => req_cnt_rdata_p2_1 );
valid_ack_release_fifo : entity work.fifo_sc
valid_ack_release_fifo : entity work.alt_fifo_sc
generic map ( DATA_WIDTH => COMPONENTS_WIDTH,
FIFO_LENGTH => TOTAL_REQS,
CNT_WIDTH => log2_ceil(TOTAL_REQS-1) )
/funbase_ip_library/trunk/TUT/ip.hwp.interface/pcie/pcie_to_hibi.comp/2.0/hdl/multi_mutex.vhd
0,0 → 1,205
-------------------------------------------------------------------------------
-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
-------------------------------------------------------------------------------
-- Title : Multi mutex
-- Project : Funbase
-------------------------------------------------------------------------------
-- File : multi_mutex.vhd
-- Author : Juha Arvio
-- Company : TUT
-- Last update: 14.10.2011
-- Version : 0.1
-- Platform :
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 14.10.2011 0.1 arvio Created
-- 14.10.2011 0.1 arvio
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
-- synthesis translate_off
use std.textio.all;
use work.txt_util.all;
-- synthesis translate_on
 
entity multi_mutex is
generic ( RESOURCES : integer := 64;
RESOURCES_WIDTH : integer := 6;
RES_DATA_WIDTH : integer := 8;
RES_AMOUNT_WIDTH : integer := 8 );
 
port (
clk_rsv : in std_logic;
clk_rls : in std_logic;
rst_n : in std_logic;
reserve_in : in std_logic;
reserve_ready_out : out std_logic;
reserve_res_out : out std_logic_vector(RESOURCES_WIDTH-1 downto 0);
reserve_amount_in : in std_logic_vector(RES_AMOUNT_WIDTH-1 downto 0);
reserve_data_in : in std_logic_vector(RES_DATA_WIDTH-1 downto 0);
release_in : in std_logic;
release_ready_out : out std_logic;
release_res_in : in std_logic_vector(RESOURCES_WIDTH-1 downto 0);
release_amount_in : in std_logic_vector(RES_AMOUNT_WIDTH-1 downto 0);
release_data_out : out std_logic_vector(RES_DATA_WIDTH-1 downto 0) );
 
end multi_mutex;
 
architecture rtl of multi_mutex is
function i2s(value : integer; width : integer) return std_logic_vector is
begin
return conv_std_logic_vector(value, width);
end;
function s2i(value : std_logic_vector) return integer is
begin
return conv_integer(value);
end;
type release_state_t is (WAIT_RELEASE, READ_RES);
signal release_state_r : release_state_t;
type reserve_state_t is (WAIT_RESERVE, WRITE_RESDATA, DELAY, SEARCH_FREE_RES);
signal reserve_state_r : reserve_state_t;
signal reserve_ready_r : std_logic;
signal release_ready_r : std_logic;
signal res_we_0_r : std_logic;
signal res_we_1_r : std_logic;
signal res_amount_r : std_logic_vector(RES_AMOUNT_WIDTH-1 downto 0);
signal res_data_r : std_logic_vector(RES_DATA_WIDTH-1 downto 0);
signal res_rdata_0 : std_logic_vector(RES_DATA_WIDTH+RES_AMOUNT_WIDTH-1 downto 0);
signal res_wdata_0 : std_logic_vector(RES_DATA_WIDTH+RES_AMOUNT_WIDTH-1 downto 0);
signal res_addr_0_r : std_logic_vector(RESOURCES_WIDTH-1 downto 0);
-- signal free_res_addr_r : std_logic_vector(RESOURCES_WIDTH-1 downto 0);
signal res_rdata_1 : std_logic_vector(RES_DATA_WIDTH+RES_AMOUNT_WIDTH-1 downto 0);
signal res_wdata_1 : std_logic_vector(RES_DATA_WIDTH+RES_AMOUNT_WIDTH-1 downto 0);
begin
reserve_ready_out <= reserve_ready_r;
release_ready_out <= release_ready_r;
process (clk_rsv, rst_n)
begin
if (rst_n = '0') then
reserve_ready_r <= '0';
res_we_0_r <= '0';
res_addr_0_r <= (others => '0');
elsif (clk_rsv'event and clk_rsv = '1') then
reserve_ready_r <= '0';
res_we_0_r <= '0';
case reserve_state_r is
when WAIT_RESERVE =>
if (reserve_in = '1') then
res_we_0_r <= '1';
reserve_ready_r <= '1';
reserve_state_r <= WRITE_RESDATA;
end if;
when WRITE_RESDATA =>
res_addr_0_r <= res_addr_0_r + 1;
reserve_state_r <= DELAY;
when DELAY =>
reserve_state_r <= SEARCH_FREE_RES;
when others => --SEARCH_FREE_RES =>
if (res_rdata_0(RES_AMOUNT_WIDTH+RES_DATA_WIDTH-1 downto RES_DATA_WIDTH) = 0) then
reserve_state_r <= WAIT_RESERVE;
-- free_res_addr_r <= res_addr_0_r;
else
reserve_state_r <= DELAY;
res_addr_0_r <= res_addr_0_r + 1;
end if;
end case;
end if;
end process;
process (clk_rls, rst_n)
begin
if (rst_n = '0') then
release_ready_r <= '0';
res_we_1_r <= '0';
res_amount_r <= (others => '0');
res_data_r <= (others => '0');
elsif (clk_rls'event and clk_rls = '1') then
release_ready_r <= '0';
res_we_1_r <= '0';
case release_state_r is
when WAIT_RELEASE =>
release_ready_r <= '1';
if (release_in = '1') then
release_state_r <= READ_RES;
end if;
when others => --READ_RES =>
res_amount_r <= res_rdata_1(RES_AMOUNT_WIDTH+RES_DATA_WIDTH-1 downto RES_DATA_WIDTH) - release_amount_in;
res_data_r <= res_rdata_1(RES_DATA_WIDTH-1 downto 0);
res_we_1_r <= '1';
release_state_r <= WAIT_RELEASE;
end case;
end if;
end process;
release_data_out <= res_rdata_1(RES_DATA_WIDTH-1 downto 0);
res_wdata_0 <= reserve_amount_in & reserve_data_in;
res_wdata_1 <= res_amount_r & res_data_r;
reserve_res_out <= res_addr_0_r;
resource_mem : entity work.alt_mem_dc_dw
generic map ( DATA_0_WIDTH => RES_DATA_WIDTH + RES_AMOUNT_WIDTH,
DATA_1_WIDTH => RES_DATA_WIDTH + RES_AMOUNT_WIDTH,
ADDR_0_WIDTH => RESOURCES_WIDTH,
ADDR_1_WIDTH => RESOURCES_WIDTH,
MEM_SIZE => RESOURCES )
port map ( clk_0 => clk_rsv,
clk_1 => clk_rls,
addr_0_in => res_addr_0_r,
addr_1_in => release_res_in,
wdata_0_in => res_wdata_0,
wdata_1_in => res_wdata_1,
we_0_in => res_we_0_r,
we_1_in => res_we_1_r,
-- be_0_in => (others => '1'),
-- be_1_in => (others => '1'),
rdata_0_out => res_rdata_0,
rdata_1_out => res_rdata_1 );
end rtl;
/funbase_ip_library/trunk/TUT/ip.hwp.interface/pcie/pcie_to_hibi.comp/2.0/hdl/pcie_to_hibi.vhd
1,37 → 1,45
-------------------------------------------------------------------------------
-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
-------------------------------------------------------------------------------
-- Title : PCIe to HIBI
-- Project :
-- Project : Funbase
-------------------------------------------------------------------------------
-- File : pcie_to_hibi.vhd
-- Author :
-- Company :
-- Last update: 27.05.2011
-- Version : 0.9
-- Author : Juha Arvio
-- Company : TUT
-- Last update: 05.10.2011
-- Version : 0.91
-- Platform :
-------------------------------------------------------------------------------
-- Description:
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 13.10.2010 0.1 arvio Created
-- 05.10.2011 0.91 arvio
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This file is a part of a free IP-block: you can redistribute it and/or modify
-- it under the terms of the Lesser GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This IP-block is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- Lesser GNU General Public License for more details.
--
-- You should have received a copy of the Lesser GNU General Public License
-- along with Transaction Generator. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
61,7 → 69,7
PCIE_ID_WIDTH : integer := 16;
PCIE_FUNC_WIDTH : integer := 3;
PCIE_TAG_WIDTH : integer := 6;
-- PKT_TAG_WIDTH : integer := 9;
PKT_TAG_WIDTH : integer := 8;
PCIE_CRED_WIDTH : integer := 66;
PCIE_CPL_LENGTH_MIN : integer := 128;
110,7 → 118,8
H2P_RD_CHANS : integer := 128;
P2H_WR_CHANS : integer := 128;
P2H_RD_CHANS : integer := 32;
USE_PCIE_DMA : integer := 1 );
USE_PCIE_DMA : integer := 1;
USE_PERF_REGS : integer := 1 );
 
port (
clk : in std_logic;
180,6 → 189,8
hibi_msg_comm_out : out std_logic_vector(HIBI_COM_WIDTH-1 downto 0);
hibi_msg_full_in : in std_logic;
hibi_msg_we_out : out std_logic;
dummy_debug_out : out std_logic;
debug_out : out std_logic );
 
end pcie_to_hibi;
213,6 → 224,12
end if;
end;
constant ENABLE_SIM : integer := 0
-- synthesis translate_off
+ 1
-- synthesis translate_on
;
constant HCOM_WR : std_logic_vector(HIBI_COM_WIDTH-1 downto 0) := HIBI_COM_WR(HIBI_COM_WIDTH-1 downto 0);
constant HCOM_RD : std_logic_vector(HIBI_COM_WIDTH-1 downto 0) := HIBI_COM_RD(HIBI_COM_WIDTH-1 downto 0);
constant HCOM_MSG_WR : std_logic_vector(HIBI_COM_WIDTH-1 downto 0) := HIBI_COM_MSG_WR(HIBI_COM_WIDTH-1 downto 0);
219,7 → 236,14
-- constant HCOM_MSG_RD : std_logic_vector(HIBI_COM_WIDTH-1 downto 0) := HIBI_COM_MSG_RD(HIBI_COM_WIDTH-1 downto 0);
constant PCIE_TAGS : integer := 2**PCIE_TAG_WIDTH;
constant PCIE_RD_LENGTH_WIDTH : integer := log2_ceil(256);
constant CYCLES_IN_SEC : integer := 100000000;
constant CYCLES_IN_SEC_WIDTH : integer := log2_ceil(CYCLES_IN_SEC);
constant IN_SYS_PROBE_WIDTH : integer := CYCLES_IN_SEC_WIDTH*2;
constant IN_SYS_SOURCE_WIDTH : integer := 0;
signal hibi_if_init_done : std_logic;
229,7 → 253,7
signal ipkt_addr : std_logic_vector(HIBI_DATA_WIDTH-1 downto 0);
signal ipkt_dma_addr_to_limit : std_logic_vector(ADDR_TO_LIMIT_WIDTH-1 downto 0);
signal ipkt_length : std_logic_vector(PCIE_RW_LENGTH_WIDTH-1 downto 0);
signal ipkt_tag : std_logic_vector(PCIE_TAG_WIDTH-1 downto 0);
signal ipkt_tag : std_logic_vector(PKT_TAG_WIDTH-1 downto 0);
signal ipkt_bar : std_logic_vector(2 downto 0);
signal ipkt_req_id : std_logic_vector(PCIE_ID_WIDTH-1 downto 0);
signal ipkt_valid : std_logic;
241,7 → 265,7
signal ipkt_dma_is_rdata : std_logic;
signal ipkt_dma_addr : std_logic_vector(HIBI_DATA_WIDTH-1 downto 0);
signal ipkt_dma_length : std_logic_vector(PCIE_RW_LENGTH_WIDTH-1 downto 0);
signal ipkt_dma_tag : std_logic_vector(PCIE_TAG_WIDTH-1 downto 0);
signal ipkt_dma_tag : std_logic_vector(PKT_TAG_WIDTH-1 downto 0);
signal ipkt_dma_req_id : std_logic_vector(PCIE_ID_WIDTH-1 downto 0);
signal ipkt_dma_valid : std_logic;
signal ipkt_dma_re : std_logic;
252,7 → 276,7
signal opkt_is_rdata : std_logic;
signal opkt_addr : std_logic_vector(PCIE_ADDR_WIDTH-1 downto 0);
signal opkt_length : std_logic_vector(PCIE_RW_LENGTH_WIDTH-1 downto 0);
signal opkt_tag : std_logic_vector(PCIE_TAG_WIDTH-1 downto 0);
signal opkt_tag : std_logic_vector(PKT_TAG_WIDTH-1 downto 0);
signal opkt_req_id : std_logic_vector(PCIE_ID_WIDTH-1 downto 0);
signal opkt_ready : std_logic;
signal opkt_wdata_req : std_logic;
265,7 → 289,7
signal opkt_dma_is_rdata : std_logic;
signal opkt_dma_addr : std_logic_vector(PCIE_ADDR_WIDTH-1 downto 0);
signal opkt_dma_length : std_logic_vector(PCIE_RW_LENGTH_WIDTH-1 downto 0);
signal opkt_dma_tag : std_logic_vector(PCIE_TAG_WIDTH-1 downto 0);
signal opkt_dma_tag : std_logic_vector(PKT_TAG_WIDTH-1 downto 0);
signal opkt_dma_req_id : std_logic_vector(PCIE_ID_WIDTH-1 downto 0);
signal opkt_dma_ready : std_logic;
signal opkt_dma_wdata_req : std_logic;
290,14 → 314,23
signal debug_ena_r : std_logic;
--synthesis translate_on
signal tag_reserve : std_logic;
signal tag_reserve_ready : std_logic;
signal tag_reserve_res : std_logic_vector(PCIE_TAG_WIDTH-1 downto 0);
signal tag_reserve_amount : std_logic_vector(PCIE_RD_LENGTH_WIDTH-1 downto 0);
signal tag_reserve_data : std_logic_vector(PKT_TAG_WIDTH-1 downto 0);
-- signal tag_fifo_we : std_logic;
-- signal tag_fifo_re : std_logic;
-- signal tag_fifo_empty : std_logic;
-- signal tag_fifo_full : std_logic;
-- signal tag_fifo_wdata : std_logic_vector(PKT_TAG_WIDTH-1 downto 0);
-- signal tag_fifo_rdata : std_logic_vector(PKT_TAG_WIDTH-1 downto 0);
signal tag_release : std_logic;
signal tag_release_ready : std_logic;
signal tag_release_res : std_logic_vector(PCIE_TAG_WIDTH-1 downto 0);
signal tag_release_amount : std_logic_vector(PCIE_RD_LENGTH_WIDTH-1 downto 0);
signal tag_release_data : std_logic_vector(PKT_TAG_WIDTH-1 downto 0);
signal in_sys_probe : std_logic_vector(CYCLES_IN_SEC_WIDTH*3-1 downto 0);
-- signal in_sys_source : std_logic_vector(CYCLES_IN_SEC_WIDTH-1 downto 0);
signal dma_writes_in_sec : std_logic_vector(CYCLES_IN_SEC_WIDTH-1 downto 0);
signal dma_reads_in_sec : std_logic_vector(CYCLES_IN_SEC_WIDTH-1 downto 0);
signal dma_write_to_read_cycles : std_logic_vector(CYCLES_IN_SEC_WIDTH-1 downto 0);
begin
--synthesis translate_off
315,6 → 348,19
-- end generate;
--synthesis translate_on
gen_in_sys_sp : if ((USE_PCIE_DMA = 1) and (ENABLE_SIM = 0)) generate
in_sys_probe <= dma_write_to_read_cycles & dma_reads_in_sec & dma_writes_in_sec;
alt_in_sys_sp_0 : entity work.alt_in_sys_sp
generic map (
INSTANCE_INDEX => 1,
PROBE_WIDTH => CYCLES_IN_SEC_WIDTH*3,
SOURCE_WIDTH => 0 )
port map (
probe => in_sys_probe );
-- source => in_sys_source );
end generate;
--synthesis translate_off
process (clk_pcie, rst_n)
begin
346,7 → 392,9
generic map ( HIBI_DATA_WIDTH => HIBI_DATA_WIDTH,
PCIE_DATA_WIDTH => PCIE_DATA_WIDTH,
PCIE_ADDR_WIDTH => PCIE_ADDR_WIDTH,
PCIE_RW_LENGTH_WIDTH => PCIE_RW_LENGTH_WIDTH )
PKT_TAG_WIDTH => PKT_TAG_WIDTH,
PCIE_RW_LENGTH_WIDTH => PCIE_RW_LENGTH_WIDTH,
PCIE_RD_LENGTH_WIDTH => PCIE_RD_LENGTH_WIDTH )
 
port map (
clk_pcie => clk_pcie,
377,7 → 425,13
ipkt_bar_out => ipkt_bar,
ipkt_valid_out => ipkt_valid,
ipkt_re_in => ipkt_dma_re,
ipkt_data_out => ipkt_data );
ipkt_data_out => ipkt_data,
tag_release_out => tag_release,
tag_release_ready_in => tag_release_ready,
tag_release_res_out => tag_release_res,
tag_release_amount_out => tag_release_amount,
tag_release_data_in => tag_release_data );
-- debug_out => debug_out );
pcie_tx_0 : entity work.pcie_tx
385,9 → 439,11
PCIE_DATA_WIDTH => PCIE_DATA_WIDTH,
PCIE_ADDR_WIDTH => PCIE_ADDR_WIDTH,
PCIE_CRED_WIDTH => PCIE_CRED_WIDTH,
PKT_TAG_WIDTH => PKT_TAG_WIDTH,
PCIE_RW_LENGTH_WIDTH => PCIE_RW_LENGTH_WIDTH,
PCIE_FORCE_MAX_RW_LENGTH => PCIE_FORCE_MAX_RW_LENGTH,
PCIE_MAX_RW_LENGTH => PCIE_MAX_RW_LENGTH )
PCIE_MAX_RW_LENGTH => PCIE_MAX_RW_LENGTH,
PCIE_RD_LENGTH_WIDTH => PCIE_RD_LENGTH_WIDTH )
port map (
clk_pcie => clk_pcie,
444,7 → 500,13
lmi_we_out => lmi_we_out,
lmi_ack_in => lmi_ack_in,
lmi_addr_out => lmi_addr_out,
lmi_data_out => lmi_data_out );
lmi_data_out => lmi_data_out,
tag_reserve_out => tag_reserve,
tag_reserve_ready_in => tag_reserve_ready,
tag_reserve_res_in => tag_reserve_res,
tag_reserve_amount_out => tag_reserve_amount,
tag_reserve_data_out => tag_reserve_data );
gen_0 : if (USE_PCIE_DMA = 0) generate
ipkt_dma_is_write <= ipkt_is_write;
480,11 → 542,16
PCIE_RW_LENGTH_WIDTH => PCIE_RW_LENGTH_WIDTH,
PCIE_ID_WIDTH => PCIE_ID_WIDTH,
PCIE_TAG_WIDTH => PCIE_TAG_WIDTH,
PKT_TAG_WIDTH => PKT_TAG_WIDTH,
PCIE_DATA_WIDTH => PCIE_DATA_WIDTH,
PCIE_ADDR_WIDTH => PCIE_ADDR_WIDTH,
PCIE_LOWER_ADDR_WIDTH => PCIE_LOWER_ADDR_WIDTH,
DMA_BAR => 2 )
DMA_BAR => 2,
CYCLES_IN_SEC => CYCLES_IN_SEC,
CYCLES_IN_SEC_WIDTH => CYCLES_IN_SEC_WIDTH,
PERF_REGS => USE_PERF_REGS )
port map ( clk => clk,
rst_n => rst_n,
549,7 → 616,12
dma_irq_info_out => pcie_dma_irq_tc,
irq_full_in => pcie_irq_full,
debug_out => debug_out );
dummy_debug_out => dummy_debug_out,
debug_out => debug_out,
dma_writes_in_sec_out => dma_writes_in_sec,
dma_reads_in_sec_out => dma_reads_in_sec,
dma_write_to_read_cycles_out => dma_write_to_read_cycles );
-- dma_irq_ack_out => pcie_dma_irq_ack );
end generate;
571,6 → 643,7
PCIE_ID_WIDTH => PCIE_ID_WIDTH,
PCIE_FUNC_WIDTH => PCIE_FUNC_WIDTH,
PCIE_TAG_WIDTH => PCIE_TAG_WIDTH,
PKT_TAG_WIDTH => PKT_TAG_WIDTH,
ADDR_TO_LIMIT_WIDTH => ADDR_TO_LIMIT_WIDTH,
673,19 → 746,27
hibi_msg_comm_out => hibi_msg_comm_out,
hibi_msg_full_in => hibi_msg_full_in,
hibi_msg_we_out => hibi_msg_we_out );
tag_mutex : entity work.multi_mutex
generic map ( RESOURCES => PCIE_TAGS,
RESOURCES_WIDTH => PCIE_TAG_WIDTH,
RES_DATA_WIDTH => PKT_TAG_WIDTH,
RES_AMOUNT_WIDTH => PCIE_RD_LENGTH_WIDTH )
port map ( clk_rsv => clk_pcie,
clk_rls => clk,
rst_n => rst_n,
reserve_in => tag_reserve,
reserve_ready_out => tag_reserve_ready,
reserve_res_out => tag_reserve_res,
reserve_amount_in => tag_reserve_amount,
reserve_data_in => tag_reserve_data,
release_in => tag_release,
release_ready_out => tag_release_ready,
release_res_in => tag_release_res,
release_amount_in => tag_release_amount,
release_data_out => tag_release_data );
 
-- tag_fifo : entity work.fifo_sc
-- generic map ( DATA_WIDTH => PKT_TAG_WIDTH,
-- FIFO_LENGTH => PCIE_TAGS,
-- CNT_WIDTH => PCIE_TAG_WIDTH )
--
-- port map ( clk => clk_pcie,
-- rst_n => rst_n,
-- wdata_in => tag_fifo_wdata,
-- rdata_out => tag_fifo_rdata,
-- re_in => tag_fifo_re,
-- we_in => tag_fifo_we,
-- empty_out => tag_fifo_empty,
-- full_out => tag_fifo_full );
 
end rtl;

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