URL
https://opencores.org/ocsvn/pci/pci/trunk
Subversion Repositories pci
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- from Rev 110 to Rev 111
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Rev 110 → Rev 111
/trunk/rtl/verilog/synchronizer_flop.v
File deleted
/trunk/rtl/verilog/pci_sync_module.v
42,6 → 42,11
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2003/03/26 13:16:18 mihad |
// Added the reset value parameter to the synchronizer flop module. |
// Added resets to all synchronizer flop instances. |
// Repaired initial sync value in fifos. |
// |
// Revision 1.1 2003/01/27 16:49:31 mihad |
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. |
// |
101,7 → 106,7
assign block_set_out = del_bit; |
|
// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability |
synchronizer_flop #(1, 0) delete_sync |
pci_synchronizer_flop #(1, 0) delete_sync |
( |
.data_in (del_bit), |
.clk_out (set_clk_in), |
130,7 → 135,7
assign delete_set_out = !delayed_del_bit && sync_del_bit; |
|
// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability |
synchronizer_flop #(1, 0) clear_delete_sync |
pci_synchronizer_flop #(1, 0) clear_delete_sync |
( |
.data_in (sync_del_bit), |
.clk_out (delete_clk_in), |
/trunk/rtl/verilog/pci_wbr_fifo_control.v
42,6 → 42,10
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2003/07/29 08:20:11 mihad |
// Found and simulated the problem in the synchronization logic. |
// Repaired the synchronization logic in the FIFOs. |
// |
// Revision 1.2 2003/03/26 13:16:18 mihad |
// Added the reset value parameter to the synchronizer flop module. |
// Added resets to all synchronizer flop instances. |
243,7 → 247,7
--------------------------------------------------------------------------------------------------------------------------------*/ |
wire [(ADDR_LENGTH - 1):0] rclk_sync_wgrey_addr ; |
reg [(ADDR_LENGTH - 1):0] rclk_wgrey_addr ; |
synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_wgrey_addr |
pci_synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_wgrey_addr |
( |
.data_in (wgrey_addr), |
.clk_out (rclock_in), |
/trunk/rtl/verilog/pci_pcir_fifo_control.v
42,6 → 42,10
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2003/07/29 08:20:11 mihad |
// Found and simulated the problem in the synchronization logic. |
// Repaired the synchronization logic in the FIFOs. |
// |
// Revision 1.2 2003/03/26 13:16:18 mihad |
// Added the reset value parameter to the synchronizer flop module. |
// Added resets to all synchronizer flop instances. |
281,7 → 285,7
--------------------------------------------------------------------------------------------------------------------------------*/ |
wire [(ADDR_LENGTH - 1):0] wclk_sync_rgrey_addr ; |
reg [(ADDR_LENGTH - 1):0] wclk_rgrey_addr ; |
synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_rgrey_addr |
pci_synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_rgrey_addr |
( |
.data_in (rgrey_addr), |
.clk_out (wclock_in), |
307,7 → 311,7
--------------------------------------------------------------------------------------------------------------------------------*/ |
wire [(ADDR_LENGTH - 1):0] rclk_sync_wgrey_addr ; |
reg [(ADDR_LENGTH - 1):0] rclk_wgrey_addr ; |
synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_wgrey_addr |
pci_synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_wgrey_addr |
( |
.data_in (wgrey_addr), |
.clk_out (rclock_in), |
/trunk/rtl/verilog/pci_conf_space.v
43,6 → 43,11
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2003/03/26 13:16:18 mihad |
// Added the reset value parameter to the synchronizer flop module. |
// Added resets to all synchronizer flop instances. |
// Repaired initial sync value in fifos. |
// |
// Revision 1.1 2003/01/27 16:49:31 mihad |
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. |
// |
2462,7 → 2467,7
set_status_bit8 && !block_set_status_bit8 } ; |
wire [5:0] meta_status_bits ; |
// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability |
synchronizer_flop #(6, 0) status_bits_sync |
pci_synchronizer_flop #(6, 0) status_bits_sync |
( |
.data_in (status_bits), |
.clk_out (wb_clk), |
2624,7 → 2629,7
wire pci_err_cs_bits = set_pci_err_cs_bit8 && !block_set_pci_err_cs_bit8 ; |
wire meta_pci_err_cs_bits ; |
// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability |
synchronizer_flop #(1,0) pci_err_cs_bits_sync |
pci_synchronizer_flop #(1,0) pci_err_cs_bits_sync |
( |
.data_in (pci_err_cs_bits), |
.clk_out (pci_clk), |
2726,7 → 2731,7
wire wb_err_cs_bits = set_wb_err_cs_bit8 && !block_set_wb_err_cs_bit8 ; |
wire meta_wb_err_cs_bits ; |
// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability |
synchronizer_flop #(1,0) wb_err_cs_bits_sync |
pci_synchronizer_flop #(1,0) wb_err_cs_bits_sync |
( |
.data_in (wb_err_cs_bits), |
.clk_out (wb_clk), |
2883,7 → 2888,7
set_isr_bit4_3[3] && !block_set_isr_bit3 } ; |
wire [4:3] meta_isr_bits4_3 ; |
// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability |
synchronizer_flop #(2, 0) isr_bits_sync |
pci_synchronizer_flop #(2, 0) isr_bits_sync |
( |
.data_in (isr_bits4_3), |
.clk_out (wb_clk), |
2962,7 → 2967,7
wire isr_bit1 = set_isr_bit1 && !block_set_isr_bit1 ; |
wire meta_isr_bit1 ; |
// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability |
synchronizer_flop #(1, 0) isr_bit1_sync |
pci_synchronizer_flop #(1, 0) isr_bit1_sync |
( |
.data_in (isr_bit1), |
.clk_out (wb_clk), |
3035,7 → 3040,7
wire isr_bit2 = set_isr_bit2 && !block_set_isr_bit2 ; |
wire meta_isr_bit2 ; |
// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability |
synchronizer_flop #(1, 0) isr_bit2_sync |
pci_synchronizer_flop #(1, 0) isr_bit2_sync |
( |
.data_in (isr_bit2), |
.clk_out (pci_clk), |
3057,7 → 3062,7
wire isr_int_prop_bit = isr_int_prop && icr_bit2_0[0] ; |
wire meta_isr_int_prop_bit ; |
// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability |
synchronizer_flop #(1, 0) isr_bit0_sync |
pci_synchronizer_flop #(1, 0) isr_bit0_sync |
( |
.data_in (isr_int_prop_bit), |
.clk_out (wb_clk), |
3085,7 → 3090,7
wire isr_int_prop_bit = isr_int_prop && icr_bit2_0[0] ; |
wire meta_isr_int_prop_bit ; |
// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability |
synchronizer_flop #(1, 0) isr_bit0_sync |
pci_synchronizer_flop #(1, 0) isr_bit0_sync |
( |
.data_in (isr_int_prop_bit), |
.clk_out (pci_clk), |
3113,7 → 3118,7
assign int_in = isr_int_prop_bit || isr_bit1 || isr_bit2_0[2] || isr_bits4_3[3] || isr_bits4_3[4]; |
`endif |
// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability |
synchronizer_flop #(1, 0) int_pin_sync |
pci_synchronizer_flop #(1, 0) int_pin_sync |
( |
.data_in (int_in), |
.clk_out (wb_clk), |
3134,7 → 3139,7
assign int_in = isr_int_prop_bit || isr_bit2_0[1] || isr_bit2; |
`endif |
// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability |
synchronizer_flop #(1, 0) int_pin_sync |
pci_synchronizer_flop #(1, 0) int_pin_sync |
( |
.data_in (int_in), |
.clk_out (pci_clk), |
3159,7 → 3164,7
wire [3:0] command_bits = {command_bit8, command_bit6, command_bit2_0[1:0]} ; |
wire [3:0] meta_command_bits ; |
reg [3:0] sync_command_bits ; |
synchronizer_flop #(4, 0) command_bits_sync |
pci_synchronizer_flop #(4, 0) command_bits_sync |
( |
.data_in (command_bits), |
.clk_out (pci_clk), |
3182,7 → 3187,7
wire command_bit = command_bit2_0[2] ; |
wire meta_command_bit ; |
reg sync_command_bit ; |
synchronizer_flop #(1, 0) command_bit_sync |
pci_synchronizer_flop #(1, 0) command_bit_sync |
( |
.data_in (command_bit), |
.clk_out (pci_clk), |
3218,7 → 3223,7
wire [7:2] cache_lsize_to_pci_bits = { cache_line_size_reg[7:2] } ; |
wire [7:2] meta_cache_lsize_to_pci_bits ; |
reg [7:2] sync_cache_lsize_to_pci_bits ; |
synchronizer_flop #(6, 0) cache_lsize_to_pci_bits_sync |
pci_synchronizer_flop #(6, 0) cache_lsize_to_pci_bits_sync |
( |
.data_in (cache_lsize_to_pci_bits), |
.clk_out (pci_clk), |
3239,7 → 3244,7
wire [7:0] latency_timer_bits = latency_timer ; |
wire [7:0] meta_latency_timer_bits ; |
reg [7:0] sync_latency_timer_bits ; |
synchronizer_flop #(8, 0) latency_timer_bits_sync |
pci_synchronizer_flop #(8, 0) latency_timer_bits_sync |
( |
.data_in (latency_timer_bits), |
.clk_out (pci_clk), |
3258,7 → 3263,7
wire [8:2] cache_lsize_to_wb_bits = { cache_lsize_not_zero, cache_line_size_reg[7:2] } ; |
wire [8:2] meta_cache_lsize_to_wb_bits ; |
reg [8:2] sync_cache_lsize_to_wb_bits ; |
synchronizer_flop #(7, 0) cache_lsize_to_wb_bits_sync |
pci_synchronizer_flop #(7, 0) cache_lsize_to_wb_bits_sync |
( |
.data_in (cache_lsize_to_wb_bits), |
.clk_out (wb_clk), |
/trunk/rtl/verilog/pci_delayed_sync.v
42,6 → 42,11
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2003/03/26 13:16:18 mihad |
// Added the reset value parameter to the synchronizer flop module. |
// Added resets to all synchronizer flop instances. |
// Repaired initial sync value in fifos. |
// |
// Revision 1.1 2003/01/27 16:49:31 mihad |
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. |
// |
219,7 → 224,7
|
// interemediate stage request synchronization flip - flop - this one is prone to metastability |
// and should have setup and hold times disabled during simulation |
synchronizer_flop #(1, 0) req_sync |
pci_synchronizer_flop #(1, 0) req_sync |
( |
.data_in (req_req_pending), |
.clk_out (comp_clk_in), |
273,7 → 278,7
assign comp_comp_pending_out = comp_comp_pending ; |
|
// interemediate stage completion synchronization flip - flop - this one is prone to metastability |
synchronizer_flop #(1, 0) comp_sync |
pci_synchronizer_flop #(1, 0) comp_sync |
( |
.data_in (comp_comp_pending), |
.clk_out (req_clk_in), |
331,7 → 336,7
req_done_reg <= #`FF_DELAY 1'b1 ; |
end |
|
synchronizer_flop #(1, 0) done_sync |
pci_synchronizer_flop #(1, 0) done_sync |
( |
.data_in (req_done_reg), |
.clk_out (comp_clk_in), |
379,7 → 384,7
end |
|
// interemediate stage retry expired synchronization flip - flop - this one is prone to metastability |
synchronizer_flop #(1, 0) rty_exp_sync |
pci_synchronizer_flop #(1, 0) rty_exp_sync |
( |
.data_in (comp_rty_exp_reg), |
.clk_out (req_clk_in), |
404,7 → 409,7
req_rty_exp_clr <= #`FF_DELAY req_rty_exp_reg ; |
end |
|
synchronizer_flop #(1, 0) rty_exp_back_prop_sync |
pci_synchronizer_flop #(1, 0) rty_exp_back_prop_sync |
( |
.data_in (req_rty_exp_reg && req_rty_exp_clr), |
.clk_out (comp_clk_in), |
/trunk/rtl/verilog/pci_wb_tpram.v
62,6 → 62,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2003/01/27 16:49:31 mihad |
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. |
// |
// Revision 1.7 2002/10/18 03:36:37 tadejm |
// Changed wrong signal name scanb_sen into scanb_en. |
// |
196,24 → 199,48
// |
// Artisan Synchronous Double-Port RAM (ra2sh) |
// |
art_hsdp_256x40 /*#(dw, 1<<aw, aw) */ artisan_sdp |
( |
.qa(do_a), |
.clka(clk_a), |
.cena(~ce_a), |
.wena(~we_a), |
.aa(addr_a), |
.da(di_a), |
.oena(~oe_a), |
.qb(do_b), |
.clkb(clk_b), |
.cenb(~ce_b), |
.wenb(~we_b), |
.ab(addr_b), |
.db(di_b), |
.oenb(~oe_b) |
); |
|
`ifdef PCI_BIST |
art_hsdp_64x40_bist /*#(dw, 1<<aw, aw) */ artisan_sdp |
( |
.QA(do_a), |
.CLKA(clk_a), |
.CENA(~ce_a), |
.WENA(~we_a), |
.AA(addr_a), |
.DA(di_a), |
.OENA(~oe_a), |
.QB(do_b), |
.CLKB(clk_b), |
.CENB(~ce_b), |
.WENB(~we_b), |
.AB(addr_b), |
.DB(di_b), |
.OENB(~oe_b), |
.scanb_rst (scanb_rst), |
.scanb_clk (scanb_clk), |
.scanb_si (scanb_si), |
.scanb_so (scanb_so), |
.scanb_en (scanb_en) |
); |
`else |
art_hsdp_64x40 /*#(dw, 1<<aw, aw) */ artisan_sdp |
( |
.QA(do_a), |
.CLKA(clk_a), |
.CENA(~ce_a), |
.WENA(~we_a), |
.AA(addr_a), |
.DA(di_a), |
.OENA(~oe_a), |
.QB(do_b), |
.CLKB(clk_b), |
.CENB(~ce_b), |
.WENB(~we_b), |
.AB(addr_b), |
.DB(di_b), |
.OENB(~oe_b) |
); |
`endif |
`endif |
|
`ifdef AVANT_ATP |
/trunk/rtl/verilog/pci_synchronizer_flop.v
0,0 → 1,100
//=========================================================================== |
// $Id: pci_synchronizer_flop.v,v 1.1 2003-08-14 13:08:58 simons Exp $ |
// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// pci_synchronizer_flop //// |
//// //// |
//// This file is part of the general opencores effort. //// |
//// <http://www.opencores.org/cores/misc/> //// |
//// //// |
//// Module Description: //// |
//// //// |
//// Make a rising-edge triggered flop with async reset with a //// |
//// distinguished name so that it can be replaced with a flop //// |
//// which does not make X's during simulation. //// |
//// //// |
//// This flop should be used instead of a regular flop for ALL //// |
//// cross-clock-domain flops. Manually instantiating this //// |
//// flop for all signals which must NEVER go to 1'bX during //// |
//// simulation will make it possible for the user to //// |
//// substitute a simulation model which does NOT have setup //// |
//// and hold checks. //// |
//// //// |
//// If a target device library has a component which is //// |
//// especially well suited to perform this function, it should //// |
//// be instantiated by name in this file. Otherwise, the //// |
//// behaviorial version of this module will be used. //// |
//// //// |
//// To Do: //// |
//// Nothing //// |
//// //// |
//// Author(s): //// |
//// - anynomous //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from <http://www.opencores.org/lgpl.shtml> //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
|
// If the vendor has a flop which is particularly good at settling out of |
// metastability, it should be used here. |
module pci_synchronizer_flop ( |
data_in, clk_out, sync_data_out, async_reset |
); |
parameter width = 1 ; |
parameter reset_val = 0 ; |
|
input [width-1:0] data_in; |
input clk_out; |
output [width-1:0] sync_data_out; |
input async_reset; |
|
reg [width-1:0] sync_data_out; |
|
always @(posedge clk_out or posedge async_reset) |
begin |
if (async_reset == 1'b1) |
begin |
sync_data_out <= reset_val; |
end |
else |
begin |
// In gate-level simulation, must only go to 1'bX if the input is 1'bX or 1'bZ. |
// This should NEVER go to 1'bX due to setup or hold violations. |
sync_data_out <= data_in; |
end |
end |
endmodule |
|
/trunk/rtl/verilog/pci_pci_tpram.v
62,6 → 62,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2003/01/27 16:49:31 mihad |
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. |
// |
// Revision 1.7 2002/10/18 03:36:37 tadejm |
// Changed wrong signal name scanb_sen into scanb_en. |
// |
196,23 → 199,48
// |
// Artisan Synchronous Double-Port RAM (ra2sh) |
// |
art_hsdp_256x40 /*#(dw, 1<<aw, aw) */ artisan_sdp |
( |
.qa(do_a), |
.clka(clk_a), |
.cena(~ce_a), |
.wena(~we_a), |
.aa(addr_a), |
.da(di_a), |
.oena(~oe_a), |
.qb(do_b), |
.clkb(clk_b), |
.cenb(~ce_b), |
.wenb(~we_b), |
.ab(addr_b), |
.db(di_b), |
.oenb(~oe_b) |
); |
`ifdef PCI_BIST |
art_hsdp_64x40_bist /*#(dw, 1<<aw, aw) */ artisan_sdp |
( |
.QA(do_a), |
.CLKA(clk_a), |
.CENA(~ce_a), |
.WENA(~we_a), |
.AA(addr_a), |
.DA(di_a), |
.OENA(~oe_a), |
.QB(do_b), |
.CLKB(clk_b), |
.CENB(~ce_b), |
.WENB(~we_b), |
.AB(addr_b), |
.DB(di_b), |
.OENB(~oe_b), |
.scanb_rst (scanb_rst), |
.scanb_clk (scanb_clk), |
.scanb_si (scanb_si), |
.scanb_so (scanb_so), |
.scanb_en (scanb_en) |
); |
`else |
art_hsdp_64x40 /*#(dw, 1<<aw, aw) */ artisan_sdp |
( |
.QA(do_a), |
.CLKA(clk_a), |
.CENA(~ce_a), |
.WENA(~we_a), |
.AA(addr_a), |
.DA(di_a), |
.OENA(~oe_a), |
.QB(do_b), |
.CLKB(clk_b), |
.CENB(~ce_b), |
.WENB(~we_b), |
.AB(addr_b), |
.DB(di_b), |
.OENB(~oe_b) |
); |
`endif |
`endif |
|
`ifdef AVANT_ATP |
/trunk/rtl/verilog/pci_wbw_wbr_fifos.v
42,6 → 42,11
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2003/03/26 13:16:18 mihad |
// Added the reset value parameter to the synchronizer flop module. |
// Added resets to all synchronizer flop instances. |
// Repaired initial sync value in fifos. |
// |
// Revision 1.2 2003/01/30 22:01:09 mihad |
// Updated synchronization in top level fifo modules. |
// |
538,7 → 543,7
|
wire [(WBW_ADDR_LENGTH-2):0] pci_clk_sync_inGreyCount ; |
reg [(WBW_ADDR_LENGTH-2):0] pci_clk_inGreyCount ; |
synchronizer_flop #((WBW_ADDR_LENGTH - 1), 0) i_synchronizer_reg_inGreyCount |
pci_synchronizer_flop #((WBW_ADDR_LENGTH - 1), 0) i_synchronizer_reg_inGreyCount |
( |
.data_in (inGreyCount), |
.clk_out (pci_clock_in), |
/trunk/rtl/verilog/pci_wbw_fifo_control.v
42,6 → 42,10
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2003/07/29 08:20:11 mihad |
// Found and simulated the problem in the synchronization logic. |
// Repaired the synchronization logic in the FIFOs. |
// |
// Revision 1.2 2003/03/26 13:16:18 mihad |
// Added the reset value parameter to the synchronizer flop module. |
// Added resets to all synchronizer flop instances. |
242,7 → 246,7
wire [(ADDR_LENGTH - 1):0] wclk_sync_rgrey_minus1 ; |
reg [(ADDR_LENGTH - 1):0] wclk_rgrey_minus1 ; |
|
synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_rgrey_minus1 |
pci_synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_rgrey_minus1 |
( |
.data_in (rgrey_minus1), |
.clk_out (wclock_in), |
272,7 → 276,7
--------------------------------------------------------------------------------------------------------------------------------*/ |
wire [(ADDR_LENGTH - 1):0] rclk_sync_wgrey_next ; |
reg [(ADDR_LENGTH - 1):0] rclk_wgrey_next ; |
synchronizer_flop #(ADDR_LENGTH, 3) i_synchronizer_reg_wgrey_next |
pci_synchronizer_flop #(ADDR_LENGTH, 3) i_synchronizer_reg_wgrey_next |
( |
.data_in (wgrey_next), |
.clk_out (rclock_in), |
/trunk/rtl/verilog/pci_pciw_pcir_fifos.v
42,6 → 42,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.4 2003/08/08 16:36:33 tadejm |
// Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. |
// |
// Revision 1.3 2003/03/26 13:16:18 mihad |
// Added the reset value parameter to the synchronizer flop module. |
// Added resets to all synchronizer flop instances. |
576,7 → 579,7
|
wire [(PCIW_ADDR_LENGTH-2):0] wb_clk_sync_inGreyCount ; |
reg [(PCIW_ADDR_LENGTH-2):0] wb_clk_inGreyCount ; |
synchronizer_flop #((PCIW_ADDR_LENGTH - 1), 0) i_synchronizer_reg_inGreyCount |
pci_synchronizer_flop #((PCIW_ADDR_LENGTH - 1), 0) i_synchronizer_reg_inGreyCount |
( |
.data_in (inGreyCount), |
.clk_out (wb_clock_in), |
/trunk/rtl/verilog/pci_pciw_fifo_control.v
42,6 → 42,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.4 2003/08/08 16:36:33 tadejm |
// Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. |
// |
// Revision 1.3 2003/07/29 08:20:11 mihad |
// Found and simulated the problem in the synchronization logic. |
// Repaired the synchronization logic in the FIFOs. |
258,7 → 261,7
wire [(ADDR_LENGTH - 1):0] wclk_sync_rgrey_minus2 ; |
reg [(ADDR_LENGTH - 1):0] wclk_rgrey_minus2 ; |
|
synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_rgrey_minus2 |
pci_synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_rgrey_minus2 |
( |
.data_in (rgrey_minus2), |
.clk_out (wclock_in), |
296,7 → 299,7
--------------------------------------------------------------------------------------------------------------------------------*/ |
wire [(ADDR_LENGTH - 1):0] rclk_sync_wgrey_addr ; |
reg [(ADDR_LENGTH - 1):0] rclk_wgrey_addr ; |
synchronizer_flop #(ADDR_LENGTH, 3) i_synchronizer_reg_wgrey_addr |
pci_synchronizer_flop #(ADDR_LENGTH, 3) i_synchronizer_reg_wgrey_addr |
( |
.data_in (wgrey_addr), |
.clk_out (rclock_in), |