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/versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_defines.v
0,0 → 1,313
//=tab Main
 
// Number of WB groups
//=select
//`define WB_GRPS_1 // 1
//`define WB_GRPS_2 // 2
`define WB_GRPS_3 // 3
//`define WB_GRPS_4 // 4
//`define WB_GRPS_5 // 5
//`define WB_GRPS_6 // 6
//`define WB_GRPS_7 // 7
//`define WB_GRPS_8 // 8
//=end
 
`ifdef WB_GRPS_2
`define WB_GRPS_1
`define NR_OF_WB_GRPS 2
`define NR_OF_PORTS 2
`endif
`ifdef WB_GRPS_3
`define WB_GRPS_1
`define WB_GRPS_2
`define NR_OF_WB_GRPS 3
`define NR_OF_PORTS 3
`endif
`ifdef WB_GRPS_4
`define WB_GRPS_1
`define WB_GRPS_2
`define WB_GRPS_3
`define NR_OF_WB_GRPS 4
`define NR_OF_PORTS 4
`endif
`ifdef WB_GRPS_5
`define WB_GRPS_1
`define WB_GRPS_2
`define WB_GRPS_3
`define WB_GRPS_4
`define NR_OF_WB_GRPS 5
`define NR_OF_PORTS 5
`endif
`ifdef WB_GRPS_6
`define WB_GRPS_1
`define WB_GRPS_2
`define WB_GRPS_3
`define WB_GRPS_4
`define WB_GRPS_5
`define NR_OF_WB_GRPS 6
`define NR_OF_PORTS 6
`endif
`ifdef WB_GRPS_7
`define WB_GRPS_1
`define WB_GRPS_2
`define WB_GRPS_3
`define WB_GRPS_4
`define WB_GRPS_5
`define WB_GRPS_6
`define NR_OF_WB_GRPS 7
`define NR_OF_PORTS 7
`endif
`ifdef WB_GRPS_8
`define WB_GRPS_1
`define WB_GRPS_2
`define WB_GRPS_3
`define WB_GRPS_4
`define WB_GRPS_5
`define WB_GRPS_6
`define WB_GRPS_7
`define NR_OF_WB_GRPS 8
`define NR_OF_PORTS 8
`endif
 
// Clock domain crossing WB1
//=select
//`define WB1_MEM_CLK // mem clk domain
`define WB1_CLK // wb1 clk domain
//=end
// Clock domain crossing WB1
//=select
//`define WB2_MEM_CLK // mem clk domain
`define WB2_CLK // wb2 clk domain
//=end
// Clock domain crossing WB1
//=select
`define WB3_MEM_CLK // mem clk domain
//`define WB3_CLK // wb3 clk domain
//=end
// Clock domain crossing WB1
//=select
//`define WB4_MEM_CLK // mem clk domain
`define WB4_CLK // wb4 clk domain
//=end
// Clock domain crossing WB1
//=select
//`define WB5_MEM_CLK // mem clk domain
`define WB5_CLK // wb5 clk domain
//=end
// Clock domain crossing WB1
//=select
//`define WB6_MEM_CLK // mem clk domain
`define WB6_CLK // wb6 clk domain
//=end
// Clock domain crossing WB1
//=select
//`define WB7_MEM_CLK // mem clk domain
`define WB7_CLK // wb7 clk domain
//=end
// Clock domain crossing WB1
//=select
//`define WB8_MEM_CLK // mem clk domain
`define WB8_CLK // wb8 clk domain
//=end
 
// Module base name
`define BASE versatile_mem_ctrl_
 
// Memory type
//=select
//`define RAM // RAM
`define SDR // SDR
//`define DDR2 // DDR2
//`define DDR3 // DDR3
//=end
 
// Shadow RAM
`define SHADOW_RAM
 
//=tab RAM
// Number of bits in address
`define RAM_ADR_SIZE 16
// Capacity in KBytes
`define RAM_MEM_SIZE_KB 48
`ifdef RAM_MEM_SIZE_KB
`define RAM_MEM_SIZE `RAM_MEM_SIZE_KB*1024
`endif
 
// Memory init
`define RAM_MEM_INIT_DUMMY
`ifndef RAM_MEM_INIT_DUMMY
`define RAM_MEM_INIT 0
`else
`define RAM_MEM_INIT 1
`endif
 
// Memory init file
`define RAM_MEM_INIT_FILE "ram_init.v"
 
`ifdef RAM
`define WB_ADR_SIZE `RAM_ADR_SIZE
`endif
 
//=tab SDR SDRAM
 
// External data bus size
`define SDR_EXT_DAT_SIZE 16
 
// Memory part
//=select Memory part
//`define MT48LC4M16 // Micron 4M16, 8MB
`define MT48LC16M16 // Micron 16M16, 32MB
//`define MT48LC32M16 // Micron 32M16, 64MB
//=end
 
// SDRAM clock frequency
// set refresh counter timeout
// all rows should be refreshed every 64 ms
// SDRAM CLK frequency
//=select SDRAM CLK
`define SDR_SDRAM_CLK_64 // SDRAM_CLK_64
//`define SDR_SDRAM_CLK_75 // SDRAM_CLK_75
//`define SDR_SDRAM_CLK_125 // SDRAM_CLK_125
//`define SDR_SDRAM_CLK_133 // SDRAM_CLK_133
//`define SDR_SDRAM_CLK_154 // SDRAM_CLK_154
//=end
 
`ifdef MT48LC4M16
// using 1 of MT48LC4M16
// SDRAM data width is 16
`define SDR_SDRAM_DATA_WIDTH 16
`define SDR_SDRAM_DATA_WIDTH_16
`define SDR_COL_SIZE 8
`define SDR_ROW_SIZE 12
`define SDR_ROW_SIZE_12
`define SDR_BA_SIZE 2
`endif // `ifdef MT48LC4M16
 
`ifdef MT48LC16M16
// using 1 of MT48LC16M16
// SDRAM data width is 16
`define SDR_SDRAM_DATA_WIDTH 16
`define SDR_SDRAM_DATA_WIDTH_16
`define SDR_COL_SIZE 9
`define SDR_ROW_SIZE 13
`define SDR_ROW_SIZE_13
`define SDR_BA_SIZE 2
`endif // `ifdef MT48LC16M16
 
`ifdef MT48LC32M16
// using 1 of MT48LC32M16
// SDRAM data width is 16
`define SDR_SDRAM_DATA_WIDTH 16
`define SDR_SDRAM_DATA_WIDTH_16
`define SDR_COL_SIZE 10
`define SDR_ROW_SIZE 13
`define SDR_ROW_SIZE_13
`define SDR_BA_SIZE 2
`endif // `ifdef MT48LC16M16
 
// Refresh whole memory every 64 ms
// Refresh each row every 64 ms
// refresh timeout = 64 ms / Tperiod / number_of_rows
 
// 64 MHz, row_size=12
// 64ms / (1/64MHz) / 2^12 = 1000
// ./VersatileCounter.php 10 1000
// 0101100100
 
`ifdef SDR_SDRAM_CLK_64
`ifdef SDR_ROW_SIZE_12
`define SDR_RFR_LENGTH 10
`define SDR_RFR_WRAP_VALUE 0101100100
`endif
`ifdef SDR_ROW_SIZE_13
`define SDR_RFR_LENGTH 9
`define SDR_RFR_WRAP_VALUE 001000011
`endif
`endif
`ifdef SDR_SDRAM_CLK_75
`ifdef SDR_ROW_SIZE_12
`define SDR_RFR_LENGTH 11
`define SDR_RFR_WRAP_VALUE 00110001101
`endif
`ifdef SDR_ROW_SIZE_13
`define SDR_RFR_LENGTH 10
`define SDR_RFR_WRAP_VALUE 0110111101
`endif
`endif
`ifdef SDR_SDRAM_CLK_125
`ifdef SDR_ROW_SIZE_12
`define SDR_RFR_LENGTH 11
`define SDR_RFR_WRAP_VALUE 10001000001
`endif
`ifdef SDR_ROW_SIZE_13
`define SDR_RFR_LENGTH 10
`define SDR_RFR_WRAP_VALUE 1010000111
`endif
`endif
`ifdef SDR_SDRAM_CLK_133
`ifdef SDR_ROW_SIZE_12
`define SDR_RFR_LENGTH 12
`define SDR_RFR_WRAP_VALUE 101100000111
`endif
`ifdef SDR_ROW_SIZE_13
`define SDR_RFR_LENGTH 11
`define SDR_RFR_WRAP_VALUE 11111111010
`endif
`endif
`ifdef SDR_SDRAM_CLK_154
`ifdef SDR_ROW_SIZE_12
`define SDR_RFR_LENGTH 12
`define SDR_RFR_WRAP_VALUE 000101011110
`endif
`ifdef SDR_ROW_SIZE_13
`define SDR_RFR_LENGTH 11
`define SDR_RFR_WRAP_VALUE 00111101010
`endif
`endif
 
 
// Disable burst
//`define SDR_NO_BURST
// Enable 4 beat wishbone busrt
`define SDR_BEAT4
// Enable 8 beat wishbone busrt
`define SDR_BEAT8
// Enable 16 beat wishbone busrt
`define SDR_BEAT16
 
// tRFC
`define SDR_TRFC 9
// tRP
`define SDR_TRP 2
// tRCD
`define SDR_TRCD 2
// tMRD
`define SDR_TMRD 2
 
// LMR
// [12:10] reserved
// [9] WB, write burst; 0 - programmed burst length, 1 - single location
// [8:7] OP Mode, 2'b00
// [6:4] CAS Latency; 3'b010 - 2, 3'b011 - 3
// [3] BT, Burst Type; 1'b0 - sequential, 1'b1 - interleaved
// [2:0] Burst length; 3'b000 - 1, 3'b001 - 2, 3'b010 - 4, 3'b011 - 8, 3'b111 - full page
// LMR: Write burst
`define SDR_INIT_WB 1'b0
// LMR: CAS latency
`define SDR_INIT_CL 3'b010
// LMR: Burst type
`define SDR_INIT_BT 1'b0
// LMR: Burst length
`define SDR_INIT_BL 3'b001
 
`ifdef SDR
`ifdef SDR_SDRAM_DATA_WIDTH_16
`define WB_ADR_SIZE `SDR_BA_SIZE+`SDR_COL_SIZE+`SDR_ROW_SIZE+1
`endif
`endif
//=tab DDR2 SDRAM
 
// Use existing Avalon compatible IP
`define DDR2_AVALON
// IP module name
`define DDR2_IP_NAME ALTERA_DDR2
/versatile_mem_ctrl/trunk/rtl/verilog/sdr_sdram_ctrl.v
0,0 → 1,364
//`include "versatile_mem_ctrl_defines.v"
`ifdef SDR
`timescale 1ns/1ns
`define MODULE sdr16
module `BASE`MODULE (
`undef MODULE
// wisbone i/f
`ifdef SDR_NO_BURST
dat_i, adr_i, sel_i, we_i, cyc_i, stb_i, dat_o, ack_o,
`else
dat_i, adr_i, sel_i, bte_i, we_i, cyc_i, stb_i, dat_o, ack_o,
`endif
// SDR SDRAM
ba, a, cmd, cke, cs_n, dqm, dq_i, dq_o, dq_oe,
// system
clk, rst);
 
// external data bus size
parameter dat_size = `SDR_SDRAM_DATA_WIDTH;
// memory geometry parameters
parameter ba_size = `SDR_BA_SIZE;
parameter row_size = `SDR_ROW_SIZE;
parameter col_size = `SDR_COL_SIZE;
parameter cl = `SDR_INIT_CL;
// memory timing parameters
parameter tRFC = `SDR_TRFC;
parameter tRP = `SDR_TRP;
parameter tRCD = `SDR_TRCD;
parameter tMRD = `SDR_TMRD;
// LMR
// [12:10] reserved
// [9] WB, write burst; 0 - programmed burst length, 1 - single location
// [8:7] OP Mode, 2'b00
// [6:4] CAS Latency; 3'b010 - 2, 3'b011 - 3
// [3] BT, Burst Type; 1'b0 - sequential, 1'b1 - interleaved
// [2:0] Burst length; 3'b000 - 1, 3'b001 - 2, 3'b010 - 4, 3'b011 - 8, 3'b111 - full page
parameter init_wb = `SDR_INIT_WB;
parameter init_cl = `SDR_INIT_CL;
parameter init_bt = `SDR_INIT_BT;
parameter init_bl = `SDR_INIT_BL;
input [31:0] dat_i;
input [ba_size+col_size+row_size:1] adr_i;
input [3:0] sel_i;
`ifndef SDR_NO_BURST
input [1:0] bte_i;
`endif
input we_i, cyc_i, stb_i;
output [31:0] dat_o;
output ack_o;
 
output [ba_size-1:0] ba;
output reg [12:0] a;
output reg [2:0] cmd; // {ras,cas,we}
output cke, cs_n;
output reg [1:0] dqm;
output [dat_size-1:0] dq_o;
output reg dq_oe;
input [dat_size-1:0] dq_i;
 
input clk, rst;
 
wire [ba_size-1:0] bank;
wire [row_size-1:0] row;
wire [col_size-1:0] col;
wire [12:0] col_a10_fix;
`ifdef SDR_BEAT16
parameter col_reg_width = 5;
reg [4:0] col_reg;
`else
`ifdef SDR_BEAT8
parameter col_reg_width = 4;
reg [3:0] col_reg;
`else
`ifdef SDR_BEAT4
parameter col_reg_width = 3;
reg [2:0] col_reg;
`endif
`endif
`endif
wire [0:31] shreg;
wire count0;
wire stall; // active if write burst need data
wire ref_cnt_zero;
reg refresh_req;
 
wire ack_rd, rd_ack_emptyflag;
wire ack_wr;
 
// to keep track of open rows per bank
reg [row_size-1:0] open_row[0:3];
reg [0:3] open_ba;
reg current_bank_closed, current_row_open;
 
`ifndef SDR_RFR_WRAP_VALUE
parameter rfr_length = 10;
parameter rfr_wrap_value = 1010;
`else
parameter rfr_length = `SDR_RFR_LENGTH;
parameter rfr_wrap_value = `SDR_RFR_WRAP_VALUE;
`endif
 
// cti
parameter [2:0] classic = 3'b000,
endofburst = 3'b111;
 
// bte
parameter [1:0] linear = 2'b00,
beat4 = 2'b01,
beat8 = 2'b10,
beat16 = 2'b11;
 
parameter [2:0] cmd_nop = 3'b111,
cmd_act = 3'b011,
cmd_rd = 3'b101,
cmd_wr = 3'b100,
cmd_pch = 3'b010,
cmd_rfr = 3'b001,
cmd_lmr = 3'b000;
 
// ctrl FSM
`define FSM_INIT 3'b000
`define FSM_IDLE 3'b001
`define FSM_RFR 3'b010
`define FSM_ADR 3'b011
`define FSM_PCH 3'b100
`define FSM_ACT 3'b101
`define FSM_RW 3'b111
 
assign cke = 1'b1;
assign cs_n = 1'b0;
reg [2:0] state, next;
 
function [12:0] a10_fix;
input [col_size-1:0] a;
integer i;
begin
for (i=0;i<13;i=i+1) begin
if (i<10)
if (i<col_size)
a10_fix[i] = a[i];
else
a10_fix[i] = 1'b0;
else if (i==10)
a10_fix[i] = 1'b0;
else
if (i<col_size)
a10_fix[i] = a[i-1];
else
a10_fix[i] = 1'b0;
end
end
endfunction
 
assign {bank,row,col} = adr_i;
 
always @ (posedge clk or posedge rst)
if (rst)
state <= `FSM_INIT;
else
state <= next;
always @*
begin
next = state;
case (state)
`FSM_INIT:
if (shreg[3+tRP+tRFC+tRFC+tMRD]) next = `FSM_IDLE;
`FSM_IDLE:
if (refresh_req) next = `FSM_RFR;
else if (cyc_i & stb_i & rd_ack_emptyflag) next = `FSM_ADR;
`FSM_RFR:
if (shreg[tRP+tRFC-2]) next = `FSM_IDLE; // take away two cycles because no cmd will be issued in idle and adr
`FSM_ADR:
if (current_bank_closed) next = `FSM_ACT;
else if (current_row_open) next = `FSM_RW;
else next = `FSM_PCH;
`FSM_PCH:
if (shreg[tRP]) next = `FSM_ACT;
`FSM_ACT:
if (shreg[tRCD]) next = `FSM_RW;
`FSM_RW:
`ifdef SDR_NO_BURST
if (shreg[1]) next = `FSM_IDLE;
`else
if (bte_i==linear & shreg[1]) next = `FSM_IDLE;
`ifdef SDR_BEAT4
else if (bte_i==beat4 & shreg[7]) next = `FSM_IDLE;
`endif
`ifdef SDR_BEAT8
else if (bte_i==beat8 & shreg[15]) next = `FSM_IDLE;
`endif
`ifdef SDR_BEAT16
else if (bte_i==beat16 & shreg[31]) next = `FSM_IDLE;
`endif
`endif
endcase
end
 
// active if write burst need data
assign stall = state==`FSM_RW & next==`FSM_RW & ~stb_i & count0 & we_i;
// counter
`define MODULE cnt_shreg_ce_clear
`VLBASE`MODULE # ( .length(32))
`undef MODULE
cnt0 (
.cke(!stall),
.clear(state!=next),
.q(shreg),
.rst(rst),
.clk(clk));
 
`define MODULE dff_ce_clear
`VLBASE`MODULE
`undef MODULE
dff_count0 (
.d(!count0),
.ce(!stall),
.clear(state!=next),
.q(count0),
.rst(rst),
.clk(clk));
 
// ba, a, cmd
// col_reg_a10 has bit [10] set to zero to disable auto precharge
`ifdef SDR_NO_BURST
assign col_a10_fix = a10_fix(col);
`else
assign col_a10_fix = a10_fix({col[col_size-1:col_reg_width],col_reg});
`endif
 
// outputs dependent on state vector
always @ (*)
begin
{a,cmd} = {13'd0,cmd_nop};
dqm = 2'b11;
dq_oe = 1'b0;
case (state)
`FSM_INIT:
if (shreg[3]) begin
{a,cmd} = {13'b0010000000000, cmd_pch};
end else if (shreg[3+tRP] | shreg[3+tRP+tRFC])
{a,cmd} = {13'd0, cmd_rfr};
else if (shreg[3+tRP+tRFC+tRFC])
{a,cmd} = {3'b000,init_wb,2'b00,init_cl,init_bt,init_bl,cmd_lmr};
`FSM_RFR:
if (shreg[0])
{a,cmd} = {13'b0010000000000, cmd_pch};
else if (shreg[tRP])
{a,cmd} = {13'd0, cmd_rfr};
`FSM_PCH:
if (shreg[0])
{a,cmd} = {13'd0,cmd_pch};
`FSM_ACT:
if (shreg[0])
{a[row_size-1:0],cmd} = {row,cmd_act};
`FSM_RW:
begin
if (we_i & !count0)
cmd = cmd_wr;
else if (!count0)
cmd = cmd_rd;
else
cmd = cmd_nop;
if (we_i & !count0)
dqm = ~sel_i[3:2];
else if (we_i & count0)
dqm = ~sel_i[1:0];
else
dqm = 2'b00;
if (we_i)
dq_oe = 1'b1;
if (~stall)
a = col_a10_fix;
end
endcase
end
 
assign ba = bank;
// precharge individual bank A10=0
// precharge all bank A10=1
genvar i;
generate
for (i=0;i<2<<ba_size-1;i=i+1) begin
always @ (posedge clk or posedge rst)
if (rst)
{open_ba[i],open_row[i]} <= {1'b0,{row_size{1'b0}}};
else
if (cmd==cmd_pch & (a[10] | bank==i))
open_ba[i] <= 1'b0;
else if (cmd==cmd_act & bank==i)
{open_ba[i],open_row[i]} <= {1'b1,row};
 
end
endgenerate
 
`ifndef SDR_NO_BURST
always @ (posedge clk or posedge rst)
if (rst)
col_reg <= {col_reg_width{1'b0}};
else
case (state)
`FSM_IDLE:
col_reg <= col[col_reg_width-1:0];
`FSM_RW:
if (~stall)
case (bte_i)
`ifdef SDR_BEAT4
beat4: col_reg[2:0] <= col_reg[2:0] + 3'd1;
`endif
`ifdef SDR_BEAT8
beat8: col_reg[3:0] <= col_reg[3:0] + 4'd1;
`endif
`ifdef SDR_BEAT16
beat16: col_reg[4:0] <= col_reg[4:0] + 5'd1;
`endif
endcase
endcase
`endif
 
// bank and row open ?
always @ (posedge clk or posedge rst)
if (rst)
{current_bank_closed, current_row_open} <= {1'b1, 1'b0};
else
{current_bank_closed, current_row_open} <= {!(open_ba[bank]), open_row[bank]==row};
 
// refresh counter
`define MODULE cnt_lfsr_zq
`VLBASE`MODULE # ( .length(rfr_length), .wrap_value (rfr_wrap_value)) ref_counter0( .zq(ref_cnt_zero), .rst(rst), .clk(clk));
`undef MODULE
 
always @ (posedge clk or posedge rst)
if (rst)
refresh_req <= 1'b0;
else
if (ref_cnt_zero)
refresh_req <= 1'b1;
else if (state==`FSM_RFR)
refresh_req <= 1'b0;
 
assign dat_o[15:0] = dq_i;
`define MODULE dff
`VLBASE`MODULE # ( .width(16)) wb_dat_dff ( .d(dat_o[15:0]), .q(dat_o[31:16]), .clk(clk), .rst(rst));
`undef MODULE
 
assign ack_wr = (state==`FSM_RW & count0 & we_i);
 
`define MODULE delay_emptyflag
`VLBASE`MODULE # ( .depth(cl+2)) delay0 ( .d(state==`FSM_RW & count0 & !we_i), .q(ack_rd), .emptyflag(rd_ack_emptyflag), .clk(clk), .rst(rst));
`undef MODULE
 
assign ack_o = ack_rd | ack_wr;
 
assign dq_o = (!count0) ? dat_i[31:16] : dat_i[15:0];
 
endmodule
`endif
/versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_top.v
0,0 → 1,956
/*
module `BASE`MODULE (
`undef MODULE
// wishbone slave side
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
// wishbone master side
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
 
`ifdef WB3_ARBITER_TYPE1
`define MODULE wb3_arbiter_type1
module `BASE`MODULE (
`undef MODULE
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
wb_clk, wb_rst
);
*/
//`include "versatile_mem_ctrl_defines.v"
`define MODULE top
module `BASE`MODULE (
`undef MODULE
input [31:0] wbs_1_dat_i,
input [`WB_ADR_SIZE-1:2] wbs_1_adr_i,
input [3:0] wbs_1_sel_i,
input [2:0] wbs_1_cti_i,
input [1:0] wbs_1_bte_i,
input wbs_1_we_i,
input wbs_1_stb_i,
input wbs_1_cyc_i,
output [31:0] wbs_1_dat_o,
output wbs_1_ack_o,
input wbs_1_clk_i,
input wbs_1_rst_i,
`ifdef WB_GRPS_2
input [31:0] wbs_2_dat_i,
input [`WB_ADR_SIZE-1:2] wbs_2_adr_i,
input [3:0] wbs_2_sel_i,
input [2:0] wbs_2_cti_i,
input [1:0] wbs_2_bte_i,
input wbs_2_we_i,
input wbs_2_stb_i,
input wbs_2_cyc_i,
output [31:0] wbs_2_dat_o,
output wbs_2_ack_o,
input wbs_2_clk_i,
input wbs_2_rst_i,
`endif
`ifdef WB_GRPS_3
input [31:0] wbs_3_dat_i,
input [`WB_ADR_SIZE-1:2] wbs_3_adr_i,
input [3:0] wbs_3_sel_i,
input [2:0] wbs_3_cti_i,
input [1:0] wbs_3_bte_i,
input wbs_3_we_i,
input wbs_3_stb_i,
input wbs_3_cyc_i,
output [31:0] wbs_3_dat_o,
output wbs_3_ack_o,
input wbs_3_clk_i,
input wbs_3_rst_i,
`endif
`ifdef WB_GRPS_4
input [31:0] wbs_4_dat_i,
input [`WB_ADR_SIZE-1:2] wbs_4_adr_i,
input [3:0] wbs_4_sel_i,
input [2:0] wbs_4_cti_i,
input [1:0] wbs_4_bte_i,
input wbs_4_we_i,
input wbs_4_stb_i,
input wbs_4_cyc_i,
output [31:0] wbs_4_dat_o,
output wbs_4_ack_o,
input wbs_4_clk_i,
input wbs_4_rst_i,
`endif
`ifdef WB_GRPS_5
input [31:0] wbs_5_dat_i,
input [`WB_ADR_SIZE-1:2] wbs_5_adr_i,
input [3:0] wbs_5_sel_i,
input [2:0] wbs_5_cti_i,
input [1:0] wbs_5_bte_i,
input wbs_5_we_i,
input wbs_5_stb_i,
input wbs_5_cyc_i,
output [31:0] wbs_5_dat_o,
output wbs_5_ack_o,
input wbs_5_clk_i,
input wbs_5_rst_i,
`endif
`ifdef WB_GRPS_6
input [31:0] wbs_6_dat_i,
input [`WB_ADR_SIZE-1:2] wbs_6_adr_i,
input [3:0] wbs_6_sel_i,
input [2:0] wbs_6_cti_i,
input [1:0] wbs_6_bte_i,
input wbs_6_we_i,
input wbs_6_stb_i,
input wbs_6_cyc_i,
output [31:0] wbs_6_dat_o,
output wbs_6_ack_o,
input wbs_6_clk_i,
input wbs_6_rst_i,
`endif
`ifdef WB_GRPS_7
input [31:0] wbs_7_dat_i,
input [`WB_ADR_SIZE-1:2] wbs_7_adr_i,
input [3:0] wbs_7_sel_i,
input [2:0] wbs_7_cti_i,
input [1:0] wbs_7_bte_i,
input wbs_7_we_i,
input wbs_7_stb_i,
input wbs_7_cyc_i,
output [31:0] wbs_7_dat_o,
output wbs_7_ack_o,
input wbs_7_clk_i,
input wbs_7_rst_i,
`endif
`ifdef WB_GRPS_8
input [31:0] wbs_8_dat_i,
input [`WB_ADR_SIZE-1:2] wbs_8_adr_i,
input [3:0] wbs_8_sel_i,
input [2:0] wbs_8_cti_i,
input [1:0] wbs_8_bte_i,
input wbs_8_we_i,
input wbs_8_stb_i,
input wbs_8_cyc_i,
output [31:0] wbs_8_dat_o,
output wbs_8_ack_o,
input wbs_8_clk_i,
input wbs_8_rst_i,
`endif
`ifdef SDR
output [1:0] ba,
output [12:0] a,
output [2:0] cmd,
output cke,
output cs_n,
output [`SDR_SDRAM_DATA_WIDTH/8-1:0] dqm,
output [`SDR_SDRAM_DATA_WIDTH-1:0] dq_o,
input [`SDR_SDRAM_DATA_WIDTH-1:0] dq_i,
output dq_oe,
`endif
input mem_clk_i,
input mem_rst_i
);
 
wire [31:0] wbm_1_dat_o;
wire [`WB_ADR_SIZE-1:2] wbm_1_adr_o;
wire [3:0] wbm_1_sel_o;
wire [2:0] wbm_1_cti_o;
wire [1:0] wbm_1_bte_o;
wire wbm_1_we_o;
wire wbm_1_stb_o;
wire wbm_1_cyc_o;
wire [31:0] wbm_1_dat_i;
wire wbm_1_ack_i;
`ifdef WB_GRPS_2
wire [31:0] wbm_2_dat_o;
wire [`WB_ADR_SIZE-1:2] wbm_2_adr_o;
wire [3:0] wbm_2_sel_o;
wire [2:0] wbm_2_cti_o;
wire [1:0] wbm_2_bte_o;
wire wbm_2_we_o;
wire wbm_2_stb_o;
wire wbm_2_cyc_o;
wire [31:0] wbm_2_dat_i;
wire wbm_2_ack_i;
`endif
`ifdef WB_GRPS_3
wire [31:0] wbm_3_dat_o;
wire [`WB_ADR_SIZE-1:2] wbm_3_adr_o;
wire [3:0] wbm_3_sel_o;
wire [2:0] wbm_3_cti_o;
wire [1:0] wbm_3_bte_o;
wire wbm_3_we_o;
wire wbm_3_stb_o;
wire wbm_3_cyc_o;
wire [31:0] wbm_3_dat_i;
wire wbm_3_ack_i;
`endif
`ifdef WB_GRPS_4
wire [31:0] wbm_4_dat_o;
wire [`WB_ADR_SIZE-1:2] wbm_4_adr_o;
wire [3:0] wbm_4_sel_o;
wire [2:0] wbm_4_cti_o;
wire [1:0] wbm_4_bte_o;
wire wbm_4_we_o;
wire wbm_4_stb_o;
wire wbm_4_cyc_o;
wire [31:0] wbm_4_dat_i;
wire wbm_4_ack_i;
`endif
`ifdef WB_GRPS_5
wire [31:0] wbm_5_dat_o;
wire [`WB_ADR_SIZE-1:2] wbm_5_adr_o;
wire [3:0] wbm_5_sel_o;
wire [2:0] wbm_5_cti_o;
wire [1:0] wbm_5_bte_o;
wire wbm_5_we_o;
wire wbm_5_stb_o;
wire wbm_5_cyc_o;
wire [31:0] wbm_5_dat_i;
wire wbm_5_ack_i;
`endif
`ifdef WB_GRPS_6
wire [31:0] wbm_6_dat_o;
wire [`WB_ADR_SIZE-1:2] wbm_6_adr_o;
wire [3:0] wbm_6_sel_o;
wire [2:0] wbm_6_cti_o;
wire [1:0] wbm_6_bte_o;
wire wbm_6_we_o;
wire wbm_6_stb_o;
wire wbm_6_cyc_o;
wire [31:0] wbm_6_dat_i;
wire wbm_6_ack_i;
`endif
`ifdef WB_GRPS_7
wire [31:0] wbm_7_dat_o;
wire [`WB_ADR_SIZE-1:2] wbm_7_adr_o;
wire [3:0] wbm_7_sel_o;
wire [2:0] wbm_7_cti_o;
wire [1:0] wbm_7_bte_o;
wire wbm_7_we_o;
wire wbm_7_stb_o;
wire wbm_7_cyc_o;
wire [31:0] wbm_7_dat_i;
wire wbm_7_ack_i;
`endif
`ifdef WB_GRPS_8
wire [31:0] wbm_8_dat_o;
wire [`WB_ADR_SIZE-1:2] wbm_8_adr_o;
wire [3:0] wbm_8_sel_o;
wire [2:0] wbm_8_cti_o;
wire [1:0] wbm_8_bte_o;
wire wbm_8_we_o;
wire wbm_8_stb_o;
wire wbm_8_cyc_o;
wire [31:0] wbm_8_dat_i;
wire wbm_8_ack_i;
`endif
wire [31:0] wbs_dat_i;
wire [`WB_ADR_SIZE-1:2] wbs_adr_i;
wire [3:0] wbs_sel_i;
wire [2:0] wbs_cti_i;
wire [1:0] wbs_bte_i;
wire wbs_we_i;
wire wbs_stb_i;
wire wbs_cyc_i;
wire [31:0] wbs_dat_o;
wire wbs_ack_o;
 
`define MODULE wb3wb3_bridge
 
`ifdef WB1_CLK
wire [31-(`WB_ADR_SIZE):0] dummy1;
`VLBASE`MODULE wbwb1 (
// wishbone slave side
.wbs_dat_i(wbs_1_dat_i),
.wbs_adr_i({{32-(`WB_ADR_SIZE){1'b0}},wbs_1_adr_i}),
.wbs_sel_i(wbs_1_sel_i),
.wbs_bte_i(wbs_1_bte_i),
.wbs_cti_i(wbs_1_cti_i),
.wbs_we_i (wbs_1_we_i),
.wbs_cyc_i(wbs_1_cyc_i),
.wbs_stb_i(wbs_1_stb_i),
.wbs_dat_o(wbs_1_dat_o),
.wbs_ack_o(wbs_1_ack_o),
.wbs_clk(wbs_1_clk_i),
.wbs_rst(wbs_1_rst_i),
// wishbone master side
.wbm_dat_o(wbm_1_dat_o),
.wbm_adr_o({dummy1,wbm_1_adr_o}),
.wbm_sel_o(wbm_1_sel_o),
.wbm_bte_o(wbm_1_bte_o),
.wbm_cti_o(wbm_1_cti_o),
.wbm_we_o(wbm_1_we_o),
.wbm_cyc_o(wbm_1_cyc_o),
.wbm_stb_o(wbm_1_stb_o),
.wbm_dat_i(wbm_1_dat_i),
.wbm_ack_i(wbm_1_ack_i),
.wbm_clk(mem_clk_i),
.wbm_rst(mem_rst_i));
`endif
`ifdef WB1_MEM_CLK
assign wbm_1_dat_o = wbs_1_dat_i;
assign wbm_1_adr_o = wbs_1_adr_i;
assign wbm_1_sel_o = wbs_1_sel_i;
assign wbm_1_bte_o = wbs_1_bte_i;
assign wbm_1_cti_o = wbs_1_cti_i;
assign wbm_1_we_o = wbs_1_we_i;
assign wbm_1_cyc_o = wbs_1_cyc_i;
assign wbm_1_stb_o = wbs_1_stb_i;
assign wbs_1_dat_o = wbm_1_dat_i;
assign wbs_1_ack_o = wbm_1_ack_i;
`endif
 
`ifdef WB_GRPS_2
`ifdef WB2_CLK
wire [31-(`WB_ADR_SIZE):0] dummy2;
`VLBASE`MODULE wbwb2 (
// wishbone slave side
.wbs_dat_i(wbs_2_dat_i),
.wbs_adr_i({{32-(`WB_ADR_SIZE){1'b0}},wbs_2_adr_i}),
.wbs_sel_i(wbs_2_sel_i),
.wbs_bte_i(wbs_2_bte_i),
.wbs_cti_i(wbs_2_cti_i),
.wbs_we_i (wbs_2_we_i),
.wbs_cyc_i(wbs_2_cyc_i),
.wbs_stb_i(wbs_2_stb_i),
.wbs_dat_o(wbs_2_dat_o),
.wbs_ack_o(wbs_2_ack_o),
.wbs_clk(wbs_2_clk_i),
.wbs_rst(wbs_2_rst_i),
// wishbone master side
.wbm_dat_o(wbm_2_dat_o),
.wbm_adr_o({dummy2,wbm_2_adr_o}),
.wbm_sel_o(wbm_2_sel_o),
.wbm_bte_o(wbm_2_bte_o),
.wbm_cti_o(wbm_2_cti_o),
.wbm_we_o(wbm_2_we_o),
.wbm_cyc_o(wbm_2_cyc_o),
.wbm_stb_o(wbm_2_stb_o),
.wbm_dat_i(wbm_2_dat_i),
.wbm_ack_i(wbm_2_ack_i),
.wbm_clk(mem_clk_i),
.wbm_rst(mem_rst_i));
`endif
`ifdef WB2_MEM_CLK
assign wbm_2_dat_o = wbs_2_dat_i;
assign wbm_2_adr_o = wbs_2_adr_i;
assign wbm_2_sel_o = wbs_2_sel_i;
assign wbm_2_bte_o = wbs_2_bte_i;
assign wbm_2_cti_o = wbs_2_cti_i;
assign wbm_2_we_o = wbs_2_we_i;
assign wbm_2_cyc_o = wbs_2_cyc_i;
assign wbm_2_stb_o = wbs_2_stb_i;
assign wbs_2_dat_o = wbm_2_dat_i;
assign wbs_2_ack_o = wbm_2_ack_i;
`endif
`endif
 
`ifdef WB_GRPS_3
`ifdef WB3_CLK
wire [31-(`WB_ADR_SIZE):0] dummy3;
`VLBASE`MODULE wbwb3 (
// wishbone slave side
.wbs_dat_i(wbs_3_dat_i),
.wbs_adr_i({{32-(`WB_ADR_SIZE){1'b0}},wbs_3_adr_i}),
.wbs_sel_i(wbs_3_sel_i),
.wbs_bte_i(wbs_3_bte_i),
.wbs_cti_i(wbs_3_cti_i),
.wbs_we_i (wbs_3_we_i),
.wbs_cyc_i(wbs_3_cyc_i),
.wbs_stb_i(wbs_3_stb_i),
.wbs_dat_o(wbs_3_dat_o),
.wbs_ack_o(wbs_3_ack_o),
.wbs_clk(wbs_3_clk_i),
.wbs_rst(wbs_3_rst_i),
// wishbone master side
.wbm_dat_o(wbm_3_dat_o),
.wbm_adr_o({dummy3,wbm_3_adr_o}),
.wbm_sel_o(wbm_3_sel_o),
.wbm_bte_o(wbm_3_bte_o),
.wbm_cti_o(wbm_3_cti_o),
.wbm_we_o(wbm_3_we_o),
.wbm_cyc_o(wbm_3_cyc_o),
.wbm_stb_o(wbm_3_stb_o),
.wbm_dat_i(wbm_3_dat_i),
.wbm_ack_i(wbm_3_ack_i),
.wbm_clk(mem_clk_i),
.wbm_rst(mem_rst_i));
`endif
`ifdef WB3_MEM_CLK
assign wbm_3_dat_o = wbs_3_dat_i;
assign wbm_3_adr_o = wbs_3_adr_i;
assign wbm_3_sel_o = wbs_3_sel_i;
assign wbm_3_bte_o = wbs_3_bte_i;
assign wbm_3_cti_o = wbs_3_cti_i;
assign wbm_3_we_o = wbs_3_we_i;
assign wbm_3_cyc_o = wbs_3_cyc_i;
assign wbm_3_stb_o = wbs_3_stb_i;
assign wbs_3_dat_o = wbm_3_dat_i;
assign wbs_3_ack_o = wbm_3_ack_i;
`endif
`endif
 
`ifdef WB_GRPS_4
`ifdef WB4_CLK
wire [31-(`WB_ADR_SIZE):0] dummy4;
`VLBASE`MODULE wbwb4 (
// wishbone slave side
.wbs_dat_i(wbs_4_dat_i),
.wbs_adr_i({{32-(`WB_ADR_SIZE){1'b0}},wbs_4_adr_i}),
.wbs_sel_i(wbs_4_sel_i),
.wbs_bte_i(wbs_4_bte_i),
.wbs_cti_i(wbs_4_cti_i),
.wbs_we_i (wbs_4_we_i),
.wbs_cyc_i(wbs_4_cyc_i),
.wbs_stb_i(wbs_4_stb_i),
.wbs_dat_o(wbs_4_dat_o),
.wbs_ack_o(wbs_4_ack_o),
.wbs_clk(wbs_4_clk_i),
.wbs_rst(wbs_4_rst_i),
// wishbone master side
.wbm_dat_o(wbm_4_dat_o),
.wbm_adr_o({dummy4,wbm_4_adr_o}),
.wbm_sel_o(wbm_4_sel_o),
.wbm_bte_o(wbm_4_bte_o),
.wbm_cti_o(wbm_4_cti_o),
.wbm_we_o(wbm_4_we_o),
.wbm_cyc_o(wbm_4_cyc_o),
.wbm_stb_o(wbm_4_stb_o),
.wbm_dat_i(wbm_4_dat_i),
.wbm_ack_i(wbm_4_ack_i),
.wbm_clk(mem_clk_i),
.wbm_rst(mem_rst_i));
`endif
`ifdef WB4_MEM_CLK
assign wbm_4_dat_o = wbs_4_dat_i;
assign wbm_4_adr_o = wbs_4_adr_i;
assign wbm_4_sel_o = wbs_4_sel_i;
assign wbm_4_bte_o = wbs_4_bte_i;
assign wbm_4_cti_o = wbs_4_cti_i;
assign wbm_4_we_o = wbs_4_we_i;
assign wbm_4_cyc_o = wbs_4_cyc_i;
assign wbm_4_stb_o = wbs_4_stb_i;
assign wbs_4_dat_o = wbm_4_dat_i;
assign wbs_4_ack_o = wbm_4_ack_i;
`endif
`endif
 
`ifdef WB_GRPS_5
`ifdef WB5_CLK
wire [31-(`WB_ADR_SIZE):0] dummy5;
`VLBASE`MODULE wbwb5 (
// wishbone slave side
.wbs_dat_i(wbs_5_dat_i),
.wbs_adr_i({{32-(`WB_ADR_SIZE){1'b0}},wbs_5_adr_i}),
.wbs_sel_i(wbs_5_sel_i),
.wbs_bte_i(wbs_5_bte_i),
.wbs_cti_i(wbs_5_cti_i),
.wbs_we_i (wbs_5_we_i),
.wbs_cyc_i(wbs_5_cyc_i),
.wbs_stb_i(wbs_5_stb_i),
.wbs_dat_o(wbs_5_dat_o),
.wbs_ack_o(wbs_5_ack_o),
.wbs_clk(wbs_5_clk_i),
.wbs_rst(wbs_5_rst_i),
// wishbone master side
.wbm_dat_o(wbm_5_dat_o),
.wbm_adr_o({dummy5,wbm_5_adr_o}),
.wbm_sel_o(wbm_5_sel_o),
.wbm_bte_o(wbm_5_bte_o),
.wbm_cti_o(wbm_5_cti_o),
.wbm_we_o(wbm_5_we_o),
.wbm_cyc_o(wbm_5_cyc_o),
.wbm_stb_o(wbm_5_stb_o),
.wbm_dat_i(wbm_5_dat_i),
.wbm_ack_i(wbm_5_ack_i),
.wbm_clk(mem_clk_i),
.wbm_rst(mem_rst_i));
`endif
`ifdef WB5_MEM_CLK
assign wbm_5_dat_o = wbs_5_dat_i;
assign wbm_5_adr_o = wbs_5_adr_i;
assign wbm_5_sel_o = wbs_5_sel_i;
assign wbm_5_bte_o = wbs_5_bte_i;
assign wbm_5_cti_o = wbs_5_cti_i;
assign wbm_5_we_o = wbs_5_we_i;
assign wbm_5_cyc_o = wbs_5_cyc_i;
assign wbm_5_stb_o = wbs_5_stb_i;
assign wbs_5_dat_o = wbm_5_dat_i;
assign wbs_5_ack_o = wbm_5_ack_i;
`endif
`endif
 
`ifdef WB_GRPS_6
`ifdef WB6_CLK
wire [31-(`WB_ADR_SIZE):0] dummy6;
`VLBASE`MODULE wbwb6 (
// wishbone slave side
.wbs_dat_i(wbs_6_dat_i),
.wbs_adr_i({{32-(`WB_ADR_SIZE){1'b0}},wbs_6_adr_i}),
.wbs_sel_i(wbs_6_sel_i),
.wbs_bte_i(wbs_6_bte_i),
.wbs_cti_i(wbs_6_cti_i),
.wbs_we_i (wbs_6_we_i),
.wbs_cyc_i(wbs_6_cyc_i),
.wbs_stb_i(wbs_6_stb_i),
.wbs_dat_o(wbs_6_dat_o),
.wbs_ack_o(wbs_6_ack_o),
.wbs_clk(wbs_6_clk_i),
.wbs_rst(wbs_6_rst_i),
// wishbone master side
.wbm_dat_o(wbm_6_dat_o),
.wbm_adr_o({dummy6,wbm_6_adr_o}),
.wbm_sel_o(wbm_6_sel_o),
.wbm_bte_o(wbm_6_bte_o),
.wbm_cti_o(wbm_6_cti_o),
.wbm_we_o(wbm_6_we_o),
.wbm_cyc_o(wbm_6_cyc_o),
.wbm_stb_o(wbm_6_stb_o),
.wbm_dat_i(wbm_6_dat_i),
.wbm_ack_i(wbm_6_ack_i),
.wbm_clk(mem_clk_i),
.wbm_rst(mem_rst_i));
`endif
`ifdef WB6_MEM_CLK
assign wbm_6_dat_o = wbs_6_dat_i;
assign wbm_6_adr_o = wbs_6_adr_i;
assign wbm_6_sel_o = wbs_6_sel_i;
assign wbm_6_bte_o = wbs_6_bte_i;
assign wbm_6_cti_o = wbs_6_cti_i;
assign wbm_6_we_o = wbs_6_we_i;
assign wbm_6_cyc_o = wbs_6_cyc_i;
assign wbm_6_stb_o = wbs_6_stb_i;
assign wbs_6_dat_o = wbm_6_dat_i;
assign wbs_6_ack_o = wbm_6_ack_i;
`endif
`endif
 
`ifdef WB_GRPS_7
`ifdef WB7_CLK
wire [31-(`WB_ADR_SIZE):0] dummy7;
`VLBASE`MODULE wbwb7 (
// wishbone slave side
.wbs_dat_i(wbs_7_dat_i),
.wbs_adr_i({{32-(`WB_ADR_SIZE){1'b0}},wbs_7_adr_i}),
.wbs_sel_i(wbs_7_sel_i),
.wbs_bte_i(wbs_7_bte_i),
.wbs_cti_i(wbs_7_cti_i),
.wbs_we_i (wbs_7_we_i),
.wbs_cyc_i(wbs_7_cyc_i),
.wbs_stb_i(wbs_7_stb_i),
.wbs_dat_o(wbs_7_dat_o),
.wbs_ack_o(wbs_7_ack_o),
.wbs_clk(wbs_7_clk_i),
.wbs_rst(wbs_7_rst_i),
// wishbone master side
.wbm_dat_o(wbm_7_dat_o),
.wbm_adr_o({dummy7,wbm_7_adr_o}),
.wbm_sel_o(wbm_7_sel_o),
.wbm_bte_o(wbm_7_bte_o),
.wbm_cti_o(wbm_7_cti_o),
.wbm_we_o(wbm_7_we_o),
.wbm_cyc_o(wbm_7_cyc_o),
.wbm_stb_o(wbm_7_stb_o),
.wbm_dat_i(wbm_7_dat_i),
.wbm_ack_i(wbm_7_ack_i),
.wbm_clk(mem_clk_i),
.wbm_rst(mem_rst_i));
`endif
`ifdef WB7_MEM_CLK
assign wbm_7_dat_o = wbs_7_dat_i;
assign wbm_7_adr_o = wbs_7_adr_i;
assign wbm_7_sel_o = wbs_7_sel_i;
assign wbm_7_bte_o = wbs_7_bte_i;
assign wbm_7_cti_o = wbs_7_cti_i;
assign wbm_7_we_o = wbs_7_we_i;
assign wbm_7_cyc_o = wbs_7_cyc_i;
assign wbm_7_stb_o = wbs_7_stb_i;
assign wbs_7_dat_o = wbm_7_dat_i;
assign wbs_7_ack_o = wbm_7_ack_i;
`endif
`endif
 
`ifdef WB_GRPS_8
`ifdef WB8_CLK
wire [31-(`WB_ADR_SIZE):0] dummy8;
`VLBASE`MODULE wbwb8 (
// wishbone slave side
.wbs_dat_i(wbs_8_dat_i),
.wbs_adr_i({{32-(`WB_ADR_SIZE){1'b0}},wbs_8_adr_i}),
.wbs_sel_i(wbs_8_sel_i),
.wbs_bte_i(wbs_8_bte_i),
.wbs_cti_i(wbs_8_cti_i),
.wbs_we_i (wbs_8_we_i),
.wbs_cyc_i(wbs_8_cyc_i),
.wbs_stb_i(wbs_8_stb_i),
.wbs_dat_o(wbs_8_dat_o),
.wbs_ack_o(wbs_8_ack_o),
.wbs_clk(wbs_8_clk_i),
.wbs_rst(wbs_8_rst_i),
// wishbone master side
.wbm_dat_o(wbm_8_dat_o),
.wbm_adr_o({dummy8,wbm_8_adr_o}),
.wbm_sel_o(wbm_8_sel_o),
.wbm_bte_o(wbm_8_bte_o),
.wbm_cti_o(wbm_8_cti_o),
.wbm_we_o(wbm_8_we_o),
.wbm_cyc_o(wbm_8_cyc_o),
.wbm_stb_o(wbm_8_stb_o),
.wbm_dat_i(wbm_8_dat_i),
.wbm_ack_i(wbm_8_ack_i),
.wbm_clk(mem_clk_i),
.wbm_rst(mem_rst_i));
`endif
`ifdef WB8_MEM_CLK
assign wbm_8_dat_o = wbs_8_dat_i;
assign wbm_8_adr_o = wbs_8_adr_i;
assign wbm_8_sel_o = wbs_8_sel_i;
assign wbm_8_bte_o = wbs_8_bte_i;
assign wbm_8_cti_o = wbs_8_cti_i;
assign wbm_8_we_o = wbs_8_we_i;
assign wbm_8_cyc_o = wbs_8_cyc_i;
assign wbm_8_stb_o = wbs_8_stb_i;
assign wbs_8_dat_o = wbm_8_dat_i;
assign wbs_8_ack_o = wbm_8_ack_i;
`endif
`endif
 
`undef MODULE
 
`ifdef WB_GRPS_2
// we have at least two ports and need an arbiter
`define MODULE wb3_arbiter_type1
`VLBASE`MODULE
# (.nr_of_ports(`NR_OF_PORTS), .adr_size(`WB_ADR_SIZE))
wb0(
`undef MODULE
.wbm_dat_o({wbm_1_dat_o,wbm_2_dat_o
`ifdef WB_GRPS_3
,wbm_3_dat_o
`endif
`ifdef WB_GRPS_4
,wbm_4_dat_o
`endif
`ifdef WB_GRPS_5
,wbm_5_dat_o
`endif
`ifdef WB_GRPS_6
,wbm_6_dat_o
`endif
`ifdef WB_GRPS_7
,wbm_7_dat_o
`endif
`ifdef WB_GRPS_8
,wbm_8_dat_o
`endif
}),
.wbm_adr_o({wbm_1_adr_o,wbm_2_adr_o
`ifdef WB_GRPS_3
,wbm_3_adr_o
`endif
`ifdef WB_GRPS_4
,wbm_4_adr_o
`endif
`ifdef WB_GRPS_5
,wbm_5_adr_o
`endif
`ifdef WB_GRPS_6
,wbm_6_adr_o
`endif
`ifdef WB_GRPS_7
,wbm_7_adr_o
`endif
`ifdef WB_GRPS_8
,wbm_8_adr_o
`endif
}),
.wbm_sel_o({wbm_1_sel_o,wbm_2_sel_o
`ifdef WB_GRPS_3
,wbm_3_sel_o
`endif
`ifdef WB_GRPS_4
,wbm_4_sel_o
`endif
`ifdef WB_GRPS_5
,wbm_5_sel_o
`endif
`ifdef WB_GRPS_6
,wbm_6_sel_o
`endif
`ifdef WB_GRPS_7
,wbm_7_sel_o
`endif
`ifdef WB_GRPS_8
,wbm_8_sel_o
`endif
}),
.wbm_cti_o({wbm_1_cti_o,wbm_2_cti_o
`ifdef WB_GRPS_3
,wbm_3_cti_o
`endif
`ifdef WB_GRPS_4
,wbm_4_cti_o
`endif
`ifdef WB_GRPS_5
,wbm_5_cti_o
`endif
`ifdef WB_GRPS_6
,wbm_6_cti_o
`endif
`ifdef WB_GRPS_7
,wbm_7_cti_o
`endif
`ifdef WB_GRPS_8
,wbm_8_cti_o
`endif
}),
.wbm_bte_o({wbm_1_bte_o,wbm_2_bte_o
`ifdef WB_GRPS_3
,wbm_3_bte_o
`endif
`ifdef WB_GRPS_4
,wbm_4_bte_o
`endif
`ifdef WB_GRPS_5
,wbm_5_bte_o
`endif
`ifdef WB_GRPS_6
,wbm_6_bte_o
`endif
`ifdef WB_GRPS_7
,wbm_7_bte_o
`endif
`ifdef WB_GRPS_8
,wbm_8_bte_o
`endif
}),
.wbm_we_o({wbm_1_we_o,wbm_2_we_o
`ifdef WB_GRPS_3
,wbm_3_we_o
`endif
`ifdef WB_GRPS_4
,wbm_4_we_o
`endif
`ifdef WB_GRPS_5
,wbm_5_we_o
`endif
`ifdef WB_GRPS_6
,wbm_6_we_o
`endif
`ifdef WB_GRPS_7
,wbm_7_we_o
`endif
`ifdef WB_GRPS_8
,wbm_8_we_o
`endif
}),
.wbm_stb_o({wbm_1_stb_o,wbm_2_stb_o
`ifdef WB_GRPS_3
,wbm_3_stb_o
`endif
`ifdef WB_GRPS_4
,wbm_4_stb_o
`endif
`ifdef WB_GRPS_5
,wbm_5_stb_o
`endif
`ifdef WB_GRPS_6
,wbm_6_stb_o
`endif
`ifdef WB_GRPS_7
,wbm_7_stb_o
`endif
`ifdef WB_GRPS_8
,wbm_8_stb_o
`endif
}),
.wbm_cyc_o({wbm_1_cyc_o,wbm_2_cyc_o
`ifdef WB_GRPS_3
,wbm_3_cyc_o
`endif
`ifdef WB_GRPS_4
,wbm_4_cyc_o
`endif
`ifdef WB_GRPS_5
,wbm_5_cyc_o
`endif
`ifdef WB_GRPS_6
,wbm_6_cyc_o
`endif
`ifdef WB_GRPS_7
,wbm_7_cyc_o
`endif
`ifdef WB_GRPS_8
,wbm_8_cyc_o
`endif
}),
.wbm_dat_i({wbm_1_dat_i,wbm_2_dat_i
`ifdef WB_GRPS_3
,wbm_3_dat_i
`endif
`ifdef WB_GRPS_4
,wbm_4_dat_i
`endif
`ifdef WB_GRPS_5
,wbm_5_dat_i
`endif
`ifdef WB_GRPS_6
,wbm_6_dat_i
`endif
`ifdef WB_GRPS_7
,wbm_7_dat_i
`endif
`ifdef WB_GRPS_8
,wbm_8_dat_i
`endif
}),
.wbm_ack_i({wbm_1_ack_i,wbm_2_ack_i
`ifdef WB_GRPS_3
,wbm_3_ack_i
`endif
`ifdef WB_GRPS_4
,wbm_4_ack_i
`endif
`ifdef WB_GRPS_5
,wbm_5_ack_i
`endif
`ifdef WB_GRPS_6
,wbm_6_ack_i
`endif
`ifdef WB_GRPS_7
,wbm_7_ack_i
`endif
`ifdef WB_GRPS_8
,wbm_8_ack_i
`endif
}),
.wbm_err_i({wbm_1_err_i,wbm_2_err_i
`ifdef WB_GRPS_3
,wbm_3_err_i
`endif
`ifdef WB_GRPS_4
,wbm_4_err_i
`endif
`ifdef WB_GRPS_5
,wbm_5_err_i
`endif
`ifdef WB_GRPS_6
,wbm_6_err_i
`endif
`ifdef WB_GRPS_7
,wbm_7_err_i
`endif
`ifdef WB_GRPS_8
,wbm_8_err_i
`endif
}),
.wbm_rty_i({wbm_1_rty_i,wbm_2_rty_i
`ifdef WB_GRPS_3
,wbm_3_rty_i
`endif
`ifdef WB_GRPS_4
,wbm_4_rty_i
`endif
`ifdef WB_GRPS_5
,wbm_5_rty_i
`endif
`ifdef WB_GRPS_6
,wbm_6_rty_i
`endif
`ifdef WB_GRPS_7
,wbm_7_rty_i
`endif
`ifdef WB_GRPS_8
,wbm_8_rty_i
`endif
}),
.wbs_dat_i(wbs_dat_i),
.wbs_adr_i(wbs_adr_i),
.wbs_sel_i(wbs_sel_i),
.wbs_cti_i(wbs_cti_i),
.wbs_bte_i(wbs_bte_i),
.wbs_we_i(wbs_we_i),
.wbs_stb_i(wbs_stb_i),
.wbs_cyc_i(wbs_cyc_i),
.wbs_dat_o(wbs_dat_o),
.wbs_ack_o(wbs_ack_o),
.wbs_err_o(wbs_err_o),
.wbs_rty_o(wbs_rty_o),
.wb_clk(mem_clk),
.wb_rst(mem_clk)
);
 
`else
// only one external port an no need for arbiter
assign wbs_dat_i = wbm_dat_i;
assign wbs_adr_i = wbm_adr_i;
assign wbs_sel_i = wbm_sel_i;
assign wbs_cti_i = wbm_cti_i;
assign wbs_bte_i = wbm_bte_i;
assign wbs_we_i = wbm_we_i;
assign wbs_stb_i = wbm_stb_i;
assign wbs_cyc_i = wbm_cyc_i;
assign wbm_dat_o = wbs_dat_o;
assign wbm_ack_o = wbs_ack_o;
`endif
 
`ifdef RAM
`define MODULE wb_b3_ram_be
`VLBASE`MODULE
`undef MODULE
# (
.adr_size(`RAM_ADR_SIZE),
.mem_size(`RAM_MEM_SIZE),
.memory_init(`RAM_MEM_INIT),
.memory_file(`RAM_MEM_INIT_FILE)
)
ram0 (
.wbs_dat_i(wbs_dat_i),
.wbs_adr_i(wbs_adr_i),
.wbs_cti_i(wbs_cti_i),
.wbs_bte_i(wbs_bte_i),
.wbs_sel_i(wbs_sel_i),
.wbs_we_i(wbs_we_i),
.wbs_stb_i(wbs_stb_i),
.wbs_cyc_i(wbs_cyc_i),
.wbs_dat_o(wbs_dat_o),
.wbs_ack_o(wbs_ack_o),
.wb_clk(mem_clk),
.wb_rst(mem_rst));
 
`endif
 
`ifdef SDR
`define MODULE sdr16
`BASE`MODULE sdr16_0(
`undef MODULE
// wisbone i/f
.dat_i(wbs_dat_i),
.adr_i({wbs_adr_i,1'b0}),
.sel_i(wbs_sel_i),
`ifndef SDR_NO_BURST
.bte_i(wbs_bte_i),
`endif
.we_i(wbs_we_i),
.cyc_i(wbs_cyc_i),
.stb_i(wbs_stb_i),
.dat_o(wbs_dat_o),
.ack_o(wbs_ack_o),
// SDR SDRAM
.ba(ba),
.a(a),
.cmd(cmd),
.cke(cke),
.cs_n(cs_n),
.dqm(dqm),
.dq_i(dq_i),
.dq_o(dq_o),
.dq_oe(dq_oe),
// system
.clk(mem_clk),
.rst(mem_rst));
`endif
 
`ifdef DDR2
`endif
 
`ifdef DDR3
`endif
 
endmodule
/versatile_mem_ctrl/trunk/rtl/verilog/copyright.v
15,7 → 15,7
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// Copyright (C) 2011 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
1,17 → 1,57
sdr_sdram_16_ctrl_actel.v:
vppreproc --noline --noblank +define+RFR_LENGTH+10 +define+RFR_WRAP_VALUE+1001 +define+ACTEL sdr_sdram_16_ctrl.v > sdr_sdram_16_ctrl_actel.v
VLIB_BASE = vmemctrl_vl_
VLIB_DEFINES = +define+BASE+$(VLIB_BASE)
VLIB_DEFINES += +define+WB3WB3_BRIDGE
VLIB_DEFINES += +define+WB3_ARBITER_TYPE1
VLIB_DEFINES += +define+CNT_LFSR_ZQ
VLIB_DEFINES += +define+DELAY_EMPTYFLAG
VLIB_DEFINES += +define+DFF_CE_CLEAR
VLIB_DEFINES += +define+WB_B3_RAM_BE
#VLIB_DEFINES += +define+SYSTEMVERILOG
VLIB_ALTERA = vmemctrl_vl_altera.v
VLIB_ACTEL = vmemctrl_vl_actel.v
VLIB = versatile_library.v
VLIB += $(VLIB_ALTERA)
VLIB += $(VLIB_ACTEL)
RTL_FILES = versatile_mem_ctrl_defines.v
RTL_FILES += sdr_sdram_ctrl.v
RTL_FILES += versatile_mem_ctrl_top.v
OUT_FILE = vmemctrl.v
 
VCOUNT_FILES = VersatileCounter.class.php
VCOUNT_FILES += VersatileCounter.php
$(VCOUNT_FILES):
for file in $(VCOUNT_FILES) ; do \
svn export http://opencores.org/ocsvn/versatile_library/versatile_library/trunk/misc/$$file ; \
done
refresh: $(VCOUNT_FILES)
./VersatileCounter.php 10 1000
./VersatileCounter.php 9 500
./VersatileCounter.php 11 1172
./VersatileCounter.php 10 586
./VersatileCounter.php 11 1954
./VersatileCounter.php 10 977
./VersatileCounter.php 12 2079
./VersatileCounter.php 11 1040
./VersatileCounter.php 12 2407
./VersatileCounter.php 11 1204
export:
svn export http://opencores.org/ocsvn/versatile_library/versatile_library/trunk/rtl/verilog/versatile_library.v
vppreproc --noline --noblank +define+ALTERA $(VLIB_DEFINES) versatile_library.v | sed -r -e 's/\/\/E2_([a-z]+)/`\1/' > $(VLIB_ALTERA)
vppreproc --noline --noblank +define+ACTEL $(VLIB_DEFINES) versatile_library.v | sed -r -e 's/\/\/E2_([a-z]+)/`\1/' > $(VLIB_ACTEL)
 
config:
configurator versatile_mem_ctrl_defines.v
 
versatile_mem_ctrl: config
vppreproc --simple +define+VLBASE+$(VLIB_BASE) $(RTL_FILES) | cat copyright.v - > $(OUT_FILE)
 
test: versatile_mem_ctrl
iverilog -tnull lpm_ff.v $(VLIB_ALTERA) $(OUT_FILE)
iverilog -tnull $(VLIB_ACTEL) $(OUT_FILE)
 
# the single all rule
all: sdr_sdram_16_ctrl_actel.v
all: export versatile_mem_ctrl test
 
clean:
rm -rf $(VERSATILE_FIFO_PROJECT_FILES) $(VERSATILE_COUNTER_PROJECT_FILES)
rm -rf fifo_fill.v sdr_16.v ddr_16.v
rm -f versatile_fifo_dual_port_ram_dc_dw.v ddr_16_generated.v
rm -rf *_counter.v
rm -rf *.csv
rm -rf *~
rm -rf sdr_sdram_16_ctrl_actel.v
rm -rf $(VLIB) $(OUT_FILE) $(VCOUNT_FILES)

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