URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 1102 to Rev 1103
- ↔ Reverse comparison
Rev 1102 → Rev 1103
/trunk/or1ksim/cuc/verilog.c
222,8 → 222,8
} |
|
/* output header */ |
GEN ("/* %s -- generated by FLEXelerator\n", tmp); |
GEN (" (C) 2002 Flextronics http://www.flextronics.com/\n"); |
GEN ("/* %s -- generated by Custom Unit Compiler\n", tmp); |
GEN (" (C) 2002 Opencores\n"); |
GEN (" function \"%s\"\n", funcname); |
GEN (" at %08x - %08x\n", f->start_addr, f->end_addr); |
GEN (" num BBs %i */\n\n", f->num_bb); |
551,6 → 551,7
} |
|
/* Generate load and store state machine */ |
#if 0 |
GEN ("\n/* Load&store state machine */\n"); |
GEN ("always @(posedge clk or posedge rst)\n"); |
GEN (" if (rst) begin\n"); |
558,6 → 559,7
if (nstores) GEN (" s_stb <= #Tp %i'h0;\n", nstores); |
GEN (" end else begin\n"); |
for (i = 0; i < f->nmsched; i++) if (f->mtype[i] & MT_LOAD || f->mtype[i] & MT_STORE) { |
int cur = 0; |
dep_list *dep = f->INSN(f->msched[i]).dep; |
assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER)); |
GEN (" if ("); |
569,6 → 571,7
} |
GEN (" if (%c_end[%i]) %c_stb <= #Tp %i'h0;\n", c, cur - 1, c, cur); |
GEN (" end\n"); |
#endif |
|
/* Generate state generator machine */ |
for (j = 0; j < 2; j++) { |
736,7 → 739,7
|
/* output header */ |
GEN ("/* %s -- generated by Custom Unit Compiler\n", tmp); |
GEN (" (C) 2002 Marko Mlinar */\n\n"); |
GEN (" (C) 2002 Opencores */\n\n"); |
GEN ("/* Includes %i functions:", nrf); |
for (i = 0; i < nfuncs; i++) if (f[i]) |
GEN ("\n%s", prof_func[i].name); |