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Rev 111 → Rev 112
/trunk/vhdl/wb_stage.vhd
39,13 → 39,68
clear_reg_lock1 : out std_logic; |
lock_reg_addr1 : out REGISTER_ADDR_T); |
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end wb_stage; |
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architecture wb_stage_rtl of wb_stage is |
signal address :std_logic_vector(2 downto 0); |
signal wr_data :std_logic_vector(15 downto 0); |
signal rd :std_logic; |
signal wr :std_logic; |
signal rd_data :std_logic_vector(15 downto 0); |
signal rdy_cnt :std_logic_vector(1 downto 0); |
signal txd :std_logic; |
signal rxd :std_logic; |
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component sc_uart is |
generic (ADDR_BITS : integer; |
CLK_FREQ : integer; |
BAUD_RATE : integer; |
TXF_DEPTH : integer; |
TXF_THRES : integer; |
RXF_DEPTH : integer; |
RXF_THRES : integer); |
port (CLK : in std_logic; |
RESET : in std_logic; |
ADDRESS : in std_logic_vector(addr_bits-1 downto 0); |
WR_DATA : in std_logic_vector(15 downto 0); |
RD, WR : in std_logic; |
RD_DATA : out std_logic_vector(15 downto 0); |
RDY_CNT : out IEEE.NUMERIC_STD.unsigned(1 downto 0); |
TXD : out std_logic; |
RXD : in std_logic; |
NCTS : in std_logic; |
NRTS : out std_logic); |
end component; |
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begin -- wb_stage_rtl |
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-- Uart modul einbinden |
UART : sc_uart generic map ( |
ADDR_BITS => 2, |
CLK_FREQ => CLK_FREQ, |
BAUD_RATE => 115200, |
TXF_DEPTH => 2, |
TXF_THRES => 1, |
RXF_DEPTH => 2, |
RXF_THRES => 1 |
) |
port map( |
CLK => clk, |
RESET => reset, |
ADDRESS => address(1 downto 0), |
WR_DATA => wr_data, |
RD => rd, |
WR => wr, |
RD_DATA => rd_data, |
RDY_CNT => rdy_cnt, |
TXD => txd, |
RXD => rxd, |
NCTS => '0', |
NRTS => open |
); |
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clear_out <= '0'; -- clear_out output is unused at the moment. |
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process (reset, mem_wb_register) |