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URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

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Rev 111 → Rev 112

/versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_defines.v
116,9 → 116,9
// Memory type
//=select
//`define RAM // RAM
`define SDR // SDR
//`define SDR // SDR
//`define DDR2 // DDR2
//`define DDR3 // DDR3
`define DDR3 // DDR3
//=end
 
// Shadow RAM
147,7 → 147,9
`ifdef RAM
`define WB_ADR_SIZE `RAM_ADR_SIZE
`endif
 
`ifdef SHADOW_RAM
`define WB_RAM_ADR_SIZE `RAM_ADR_SIZE
`endif
//=tab SDR SDRAM
 
// External data bus size
305,6 → 307,7
`define WB_ADR_SIZE `SDR_BA_SIZE+`SDR_COL_SIZE+`SDR_ROW_SIZE+1
`endif
`endif
 
//=tab DDR2 SDRAM
 
// Use existing Avalon compatible IP
311,3 → 314,19
`define DDR2_AVALON
// IP module name
`define DDR2_IP_NAME ALTERA_DDR2
 
`ifdef DDR2
`define WB_ADR_SIZE 24
`endif
 
//=tab DDR3 SDRAM
 
// Board
//=select
`define DDR3_BOARD_2AGX125N // ARRIAII BOARD 2AGX125N
//=end
`ifdef DDR3
`ifdef DDR3_BOARD_2AGX125N
`define WB_ADR_SIZE 30
`endif
`endif
/versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_top.v
142,6 → 142,24
input [`SDR_SDRAM_DATA_WIDTH-1:0] dq_i,
output dq_oe,
`endif
`ifdef DDR3
output [12:0] mem_addr,
output [2:0] mem_ba,
output mem_cas_n,
output mem_cke,
inout mem_clk,
inout mem_clk_n,
output mem_cs_n,
output [1:0] mem_dm,
inout [15:0] mem_dq,
inout [1:0] mem_dqs,
inout [1:0] mem_dqsn,
output mem_odt,
output mem_ras_n,
input mem_reset_n,
output mem_we_n,
input mem_ref_clk, /* 100MHz */
`endif
input mem_clk_i,
input mem_rst_i
);
890,6 → 908,16
assign wbm_ack_o = wbs_ack_o;
`endif
 
`ifdef SHADOW_RAM
wire [31:0] wbs_ram_dat_o;
wire wbs_ram_ack_o;
wire [31:0] wbs_sdram_dat_o;
wire wbs_sdram_ack_o;
assign select_sdram = wbs_adr_i > (`RAM_MEM_SIZE-1);
assign wbs_dat_o = select_sdram ? wbs_sdram_dat_o : wbs_ram_dat_o;
assign wbs_ack_o = select_sdram ? wbs_sdram_ack_o : wbs_ram_ack_o;
`endif
 
`ifdef RAM
`define MODULE wb_b3_ram_be
`VLBASE`MODULE
913,8 → 941,32
.wbs_ack_o(wbs_ack_o),
.wb_clk(mem_clk),
.wb_rst(mem_rst));
 
`else
`ifdef SHADOW_RAM
`define MODULE wb_b3_ram_be
`VLBASE`MODULE
`undef MODULE
# (
.adr_size(`RAM_ADR_SIZE),
.mem_size(`RAM_MEM_SIZE),
.memory_init(`RAM_MEM_INIT),
.memory_file(`RAM_MEM_INIT_FILE)
)
ram0 (
.wbs_dat_i(wbs_dat_i),
.wbs_adr_i(wbs_adr_i[`WB_RAM_ADR_SIZE-2-1:0]),
.wbs_cti_i(wbs_cti_i),
.wbs_bte_i(wbs_bte_i),
.wbs_sel_i(wbs_sel_i),
.wbs_we_i(wbs_we_i),
.wbs_stb_i(wbs_stb_i),
.wbs_cyc_i(wbs_cyc_i & ~select_sdram),
.wbs_dat_o(wbs_ram_dat_o),
.wbs_ack_o(wbs_ram_ack_o),
.wb_clk(mem_clk),
.wb_rst(mem_rst));
`endif
`endif
 
`ifdef SDR
`define MODULE sdr16
928,10 → 980,19
.bte_i(wbs_bte_i),
`endif
.we_i(wbs_we_i),
`ifdef SHADOW_RAM
.cyc_i(wbs_cyc_i & select_sdram),
`else
.cyc_i(wbs_cyc_i),
`endif
.stb_i(wbs_stb_i),
`ifdef SHADOW_RAM
.dat_o(wbs_sdram_dat_o),
.ack_o(wbs_sdram_ack_o),
`else
.dat_o(wbs_dat_o),
.ack_o(wbs_ack_o),
`endif
// SDR SDRAM
.ba(ba),
.a(a),
951,6 → 1012,48
`endif
 
`ifdef DDR3
`ifdef DDR3_BOARD_2AGX125N
ddr3_2agx125n_if ddr3_0 (
.wb_adr_i(wbs_adr_i),
.wb_stb_i(wbs_stb_i),
`ifdef SHADOW_RAM
.wb_cyc_i(wbs_cyc_i & select_sdram),
`else
.wb_cyc_i(wbs_cyc_i),
`endif
.wb_cti_i(wbs_cti_i),
.wb_bte_i(wbs_bte_i),
.wb_we_i (wbs_we_i),
.wb_sel_i(wbs_sel_i),
.wb_dat_i(wbs_dat_i),
`ifdef SHADOW_RAM
.wb_dat_o(wbs_sdram_dat_o),
.wb_ack_o(wbs_sdram_ack_o),
`else
.wb_dat_o(wbs_dat_o),
.wb_ack_o(wbs_ack_o),
`endif
 
.mem_addr(mem_addr),
.mem_ba(mem_ba),
.mem_cas_n(mem_cas_n),
.mem_cke(mem_cke),
.mem_clk(mem_clk),
.mem_clk_n(mem_clk_n),
.mem_cs_n(mem_cs_n),
.mem_dm(mem_dm),
.mem_dq(mem_dq),
.mem_dqs(mem_dqs),
.mem_dqsn(mem_dqsn),
.mem_odt(mem_odt),
.mem_ras_n(mem_ras_n),
.mem_reset_n(mem_reset_n),
.mem_we_n(mem_we_n),
.mem_ref_clk(mem_ref_clk), /* 100MHz */
 
.wb_clk(mem_clk),
.wb_rst(mem_rst));
`endif
`endif
 
endmodule
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
15,7 → 15,11
RTL_FILES = versatile_mem_ctrl_defines.v
RTL_FILES += sdr_sdram_ctrl.v
RTL_FILES += versatile_mem_ctrl_top.v
#RTL_FILES += ddr3_2agx125n_cache_dpram.v
#RTL_FILES += ddr3_2agx125n_if.v
#RTL_FILES += ddr3_2agx125n/ddr3_2agx125n_ip.v
OUT_FILE = vmemctrl.v
#ALTERA_INCLUDE = /opt/altera/11.0/ip/altera/alt_mem_if/alt_mem_if_controllers/alt_mem_if_nextgen_ddr_controller_110/rtl/alt_mem_ddrx_define
 
VCOUNT_FILES = VersatileCounter.class.php
VCOUNT_FILES += VersatileCounter.php
34,9 → 38,10
./VersatileCounter.php 11 1040
./VersatileCounter.php 12 2407
./VersatileCounter.php 11 1204
 
export:
svn export http://opencores.org/ocsvn/versatile_library/versatile_library/trunk/rtl/verilog/versatile_library.v
svn export http://opencores.org/ocsvn/versatile_library/versatile_library/trunk/backend/altera/lpm_ff.v
vppreproc --noline --noblank +define+ALTERA $(VLIB_DEFINES) versatile_library.v | sed -r -e 's/\/\/E2_([a-z]+)/`\1/' > $(VLIB_ALTERA)
vppreproc --noline --noblank +define+ACTEL $(VLIB_DEFINES) versatile_library.v | sed -r -e 's/\/\/E2_([a-z]+)/`\1/' > $(VLIB_ACTEL)
 
47,11 → 52,11
vppreproc --simple +define+VLBASE+$(VLIB_BASE) $(RTL_FILES) | cat copyright.v - > $(OUT_FILE)
 
test: versatile_mem_ctrl
iverilog -tnull lpm_ff.v $(VLIB_ALTERA) $(OUT_FILE)
iverilog -tnull $(VLIB_ACTEL) $(OUT_FILE)
iverilog -y$(ALTERA_INCLUDE) -tnull lpm_ff.v $(VLIB_ALTERA) $(OUT_FILE)
iverilog -y$(ALTERA_INCLUDE) -tnull $(VLIB_ACTEL) $(OUT_FILE)
 
# the single all rule
all: export versatile_mem_ctrl test
all: export versatile_mem_ctrl
 
clean:
rm -rf $(VLIB) $(OUT_FILE) $(VCOUNT_FILES)

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