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URL https://opencores.org/ocsvn/rise/rise/trunk

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    from Rev 112 to Rev 113
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Rev 112 → Rev 113

/trunk/vhdl/wb_stage.vhd
51,8 → 51,6
signal txd :std_logic;
signal rxd :std_logic;
component sc_uart is
generic (ADDR_BITS : integer;
CLK_FREQ : integer;
103,6 → 101,9
clear_out <= '0'; -- clear_out output is unused at the moment.
 
 
 
process (reset, mem_wb_register)
begin
if reset = '0' then
118,8 → 119,13
lr <= (others => 'X');
sr_enable <= '0';
sr <= (others => 'X');
else
rd <= '0';
wr <= '0';
wr_data <= (others => 'X');
rd_data <= (others => '0');
 
else
 
-- write back of register value. --
dreg_addr <= mem_wb_register.dreg_addr;
if mem_wb_register.aluop1(ALUOP1_WB_REG_BIT) = '1' then

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