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    from Rev 1132 to Rev 1133
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Rev 1132 → Rev 1133

/trunk/orp/orp_soc/rtl/verilog/xsv_fpga_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2002/08/12 05:35:12 lampret
// rty_i are unused - tied to zero.
//
// Revision 1.5 2002/03/29 20:58:51 lampret
// Changed hardcoded address for fake MC to use a define.
//
59,6 → 62,7
//
 
`include "xsv_fpga_defines.v"
`include "bench_defines.v"
 
module xsv_fpga_top (
 
509,7 → 513,11
//
// Global clock
//
`ifdef OR1200_CLMODE_1TO2
reg wb_clk;
`else
wire wb_clk;
`endif
 
//
// Reset debounce
527,6 → 535,19
wb_rst <= #1 rst_r;
 
//
// This is purely for testing 1/2 WB clock
// This should never be used when implementing in
// an FPGA.
//
`ifdef OR1200_CLMODE_1TO2
initial wb_clk = 0;
//always @(posedge clk)
// wb_clk = ~wb_clk;
always @(clk)
wb_clk = clk;
 
`else
//
// Some Xilinx P&R tools need this
//
`ifdef TARGET_VIRTEX
537,6 → 558,7
`else
assign wb_clk = clk;
`endif
`endif // OR1200_CLMODE_1TO2
 
//
// SRAM tri-state data
1305,4 → 1327,9
.t8_wb_err_i ( 1'b1 )
);
 
//initial begin
// $dumpvars(0);
// $dumpfile("dump.vcd");
//end
 
endmodule

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