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Rev 1133 → Rev 1134

/trunk/orp/orp_soc/bench/verilog/dbg_if_model.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/03/28 19:59:54 lampret
// Added bench directory
//
// Revision 1.2 2002/01/18 07:57:21 lampret
// Added test case for testing NPC read bug when doing single-step.
//
152,19 → 155,20
risc_data_o = 0;
opselect_o = 0;
risc_stall_a = 1'b0;
#100;
while (!bp_i) @(posedge risc_clk_i);
#30000;
$display("here we go ...", $time);
// while (!bp_i) @(posedge risc_clk_i);
stall;
wb_master.wr(32'h8000_0004, 32'h9c200000, 4'b1111); /* l.addi r1,r0,0x0 */
wb_master.wr(32'h8000_0008, 32'h18408008, 4'b1111); /* l.movhi r2,0x8008 */
wb_master.wr(32'h8000_000c, 32'h9c210001, 4'b1111); /* l.addi r1,r1,1 */
wb_master.wr(32'h8000_0010, 32'h9c210001, 4'b1111); /* l.addi r1,r1,1 */
wb_master.wr(32'h8000_0014, 32'hd4020800, 4'b1111); /* l.sw 0(r2),r1 */
wb_master.wr(32'h8000_0018, 32'h9c210001, 4'b1111); /* l.addi r1,r1,1 */
wb_master.wr(32'h8000_001c, 32'h84620000, 4'b1111); /* l.lwz r3,0(r2) */
wb_master.wr(32'h8000_0020, 32'h03fffffb, 4'b1111); /* l.j loop2 */
wb_master.wr(32'h8000_0024, 32'he0211800, 4'b1111); /* l.add r1,r1,r3 */
wb_master.wr(32'h8000_0028, 32'he0211800, 4'b1111); /* l.add r1,r1,r3 */
wb_master.wr(32'h0000_0004, 32'h9c200000, 4'b1111); /* l.addi r1,r0,0x0 */
wb_master.wr(32'h0000_0008, 32'h18400008, 4'b1111); /* l.movhi r2,0x0008 */
wb_master.wr(32'h0000_000c, 32'h9c210001, 4'b1111); /* l.addi r1,r1,1 */
wb_master.wr(32'h0000_0010, 32'h9c210001, 4'b1111); /* l.addi r1,r1,1 */
wb_master.wr(32'h0000_0014, 32'hd4020800, 4'b1111); /* l.sw 0(r2),r1 */
wb_master.wr(32'h0000_0018, 32'h9c210001, 4'b1111); /* l.addi r1,r1,1 */
wb_master.wr(32'h0000_001c, 32'h84620000, 4'b1111); /* l.lwz r3,0(r2) */
wb_master.wr(32'h0000_0020, 32'h03fffffb, 4'b1111); /* l.j loop2 */
wb_master.wr(32'h0000_0024, 32'he0211800, 4'b1111); /* l.add r1,r1,r3 */
wb_master.wr(32'h0000_0028, 32'he0211800, 4'b1111); /* l.add r1,r1,r3 */
 
// Enable exceptions in SR
wr_reg(17, 3);
173,7 → 177,7
wr_reg((6 << 11) + 20, 32'h2000);
 
// Set NPC
wr_npc(32'h8000_0004);
wr_npc(32'h0000_0004);
 
// Set step-bit (DMR1[ST])
wr_reg((6 << 11) + 16, 1 << 22);
192,7 → 196,7
rd_reg(32'h401, r1);
 
$display("Read npc = %h ppc = %h r1 = %h", npc, ppc, r1);
$display("Expected npc = %h ppc = %h r1 = %h\n", 32'h8000000c, 32'h80000024, 5);
$display("Expected npc = %h ppc = %h r1 = %h\n", 32'h0000000c, 32'h00000024, 5);
result = npc + ppc + r1;
 
 
200,8 → 204,8
wr_reg ((6 << 11) + 16, 0);
 
/* Set trap insn in delay slot */
wb_master.rd (32'h8000_0024, insn);
wb_master.wr (32'h8000_0024, 32'h21000001, 4'b1111);
wb_master.rd (32'h0000_0024, insn);
wb_master.wr (32'h0000_0024, 32'h21000001, 4'b1111);
 
/* Unstall */
unstall;
216,19 → 220,19
rd_reg(32'h401, r1);
 
/* Set back original insn */
wb_master.wr (32'h8000_0024, insn, 4'b1111);
wb_master.wr (32'h0000_0024, insn, 4'b1111);
 
$display("Read npc = %h ppc = %h r1 = %h", npc, ppc, r1);
$display("Expected npc = %h ppc = %h r1 = %h\n", 32'h8000000c, 32'h80000024, 8);
$display("Expected npc = %h ppc = %h r1 = %h\n", 32'h0000000c, 32'h00000024, 8);
result = npc + ppc + r1 + result;
 
 
/* Set trap insn in place of branch insn */
wb_master.rd (32'h8000_0020, insn);
wb_master.wr (32'h8000_0020, 32'h21000001, 4'b1111);
wb_master.rd (32'h0000_0020, insn);
wb_master.wr (32'h0000_0020, 32'h21000001, 4'b1111);
 
/* Set PC */
wr_npc(32'h8000_000c);
wr_npc(32'h0000_000c);
 
/* Unstall */
unstall;
243,18 → 247,18
rd_reg(32'h401, r1);
 
/* Set back original insn */
wb_master.wr (32'h8000_0020, insn, 4'b1111);
wb_master.wr (32'h0000_0020, insn, 4'b1111);
 
$display("Read npc = %h ppc = %h r1 = %h", npc, ppc, r1);
$display("Expected npc = %h ppc = %h r1 = %h\n", 32'h80000024, 32'h80000020, 11);
$display("Expected npc = %h ppc = %h r1 = %h\n", 32'h00000024, 32'h00000020, 11);
result = npc + ppc + r1 + result;
 
/* Set trap insn before branch insn */
wb_master.rd (32'h8000_001c, insn);
wb_master.wr (32'h8000_001c, 32'h21000001, 4'b1111);
wb_master.rd (32'h0000_001c, insn);
wb_master.wr (32'h0000_001c, 32'h21000001, 4'b1111);
 
/* Set PC */
wr_npc(32'h8000_0020);
wr_npc(32'h0000_0020);
 
/* Unstall */
unstall;
269,19 → 273,19
rd_reg(32'h401, r1);
 
/* Set back original insn */
wb_master.wr (32'h8000_001c, insn, 4'b1111);
wb_master.wr (32'h0000_001c, insn, 4'b1111);
 
$display("Read npc = %h ppc = %h r1 = %h", npc, ppc, r1);
$display("Expected npc = %h ppc = %h r1 = %h\n", 32'h80000020, 32'h8000001c, 24);
$display("Expected npc = %h ppc = %h r1 = %h\n", 32'h00000020, 32'h0000001c, 24);
result = npc + ppc + r1 + result;
 
 
/* Set trap insn behind lsu insn */
wb_master.rd (32'h8000_0018, insn);
wb_master.wr (32'h8000_0018, 32'h21000001, 4'b1111);
wb_master.rd (32'h0000_0018, insn);
wb_master.wr (32'h0000_0018, 32'h21000001, 4'b1111);
 
/* Set PC */
wr_npc(32'h8000_001c);
wr_npc(32'h0000_001c);
 
/* Unstall */
unstall;
296,18 → 300,18
rd_reg(32'h401, r1);
 
/* Set back original insn */
wb_master.wr (32'h8000_0018, insn, 4'b1111);
wb_master.wr (32'h0000_0018, insn, 4'b1111);
 
$display("Read npc = %h ppc = %h r1 = %h", npc, ppc, r1);
$display("Expected npc = %h ppc = %h r1 = %h\n", 32'h8000001c, 32'h80000018, 49);
$display("Expected npc = %h ppc = %h r1 = %h\n", 32'h0000001c, 32'h00000018, 49);
result = npc + ppc + r1 + result;
 
/* Set trap insn very near previous one */
wb_master.rd (32'h8000_001c, insn);
wb_master.wr (32'h8000_001c, 32'h21000001, 4'b1111);
wb_master.rd (32'h0000_001c, insn);
wb_master.wr (32'h0000_001c, 32'h21000001, 4'b1111);
 
/* Set PC */
wr_npc(32'h8000_0018);
wr_npc(32'h0000_0018);
 
/* Unstall */
unstall;
322,18 → 326,18
rd_reg(32'h401, r1);
 
/* Set back original insn */
wb_master.wr (32'h8000_001c, insn, 4'b1111);
wb_master.wr (32'h0000_001c, insn, 4'b1111);
 
$display("Read npc = %h ppc = %h r1 = %h", npc, ppc, r1);
$display("Expected npc = %h ppc = %h r1 = %h\n", 32'h80000020, 32'h8000001c, 50);
$display("Expected npc = %h ppc = %h r1 = %h\n", 32'h00000020, 32'h0000001c, 50);
result = npc + ppc + r1 + result;
 
/* Set trap insn to the start */
wb_master.rd (32'h8000_000c, insn);
wb_master.wr (32'h8000_000c, 32'h21000001, 4'b1111);
wb_master.rd (32'h0000_000c, insn);
wb_master.wr (32'h0000_000c, 32'h21000001, 4'b1111);
 
/* Set PC */
wr_npc(32'h8000_001c);
wr_npc(32'h0000_001c);
 
/* Unstall */
unstall;
348,10 → 352,10
rd_reg(32'h401, r1);
 
/* Set back original insn */
wb_master.wr (32'h8000_000c, insn, 4'b1111);
wb_master.wr (32'h0000_000c, insn, 4'b1111);
 
$display("Read npc = %h ppc = %h r1 = %h", npc, ppc, r1);
$display("Expected npc = %h ppc = %h r1 = %h\n", 32'h80000010, 32'h8000000c, 99);
$display("Expected npc = %h ppc = %h r1 = %h\n", 32'h00000010, 32'h0000000c, 99);
result = npc + ppc + r1 + result;
 
// Set step-bit (DMR1[ST])
371,11 → 375,11
rd_reg(32'h401, r1);
 
$display("Read npc = %h ppc = %h r1 = %h", npc, ppc, r1);
$display("Expected npc = %h ppc = %h r1 = %h\n", 32'h80000024, 32'h80000020, 101);
$display("Expected npc = %h ppc = %h r1 = %h\n", 32'h00000024, 32'h00000020, 101);
result = npc + ppc + r1 + result;
 
/* Set PC */
wr_npc(32'h8000_0020);
wr_npc(32'h0000_0020);
 
// Single-step
for (i = 0; i < 2; i = i + 1)
391,7 → 395,7
rd_reg(32'h401, r1);
 
$display("Read npc = %h ppc = %h r1 = %h", npc, ppc, r1);
$display("Expected npc = %h ppc = %h r1 = %h\n", 32'h8000000c, 32'h80000024, 201);
$display("Expected npc = %h ppc = %h r1 = %h\n", 32'h0000000c, 32'h00000024, 201);
result = npc + ppc + r1 + result;
 
$display("result = %h\n", result + 32'h5eaddaa9);

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