URL
https://opencores.org/ocsvn/or1k_old/or1k_old/trunk
Subversion Repositories or1k_old
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- This comparison shows the changes necessary to convert path
/
- from Rev 1137 to Rev 1138
- ↔ Reverse comparison
Rev 1137 → Rev 1138
/trunk/orp/orp_soc/README
35,8 → 35,66
Simulation |
++++++++++ |
|
N/A yet. |
Architectural and RTL level simulations can be performed. Running directory |
for all script should be sim/run. The following scripts are available: |
1) sim/bin/run_sw: for building and running architectural simulations. You will need |
OpenRISC GNU toolchain installed. To have correct toolchain installed, see |
which or1ksim is being used (for example or32-rtems-sim, or32-uclinux-sim). |
This script is also used for building software test cases for run_rtl_regression |
script. This script can also do 'make clean' through all software test cases. |
2) sim/bin/run_rtl_regression: for running RTL regressions using different |
software test cases available in sw/ directory. Test cases need first to be |
built using run_sw script. |
3) sim/bin/run_rtl_linter: for running linter tool over RTL files. |
|
Architectural simulations copy their logs into sim/log and all log files are prefixed |
with "s-". All RTL simulations copy their log files into sim/log and they are |
prefixed with "iN-" where N is a number representing regression iteration. Each |
iteration has different environment conditions, such as latency of memories used, |
OR1200 configured with different options etc. All waveforms from RTL simulations |
are stored in sim/out/wave directory. |
|
An example of running RTL regression: |
|
$ cd sim/run |
$ ../bin/run_rtl_regression |
Sun Aug 18 07:20:50 2002 0.178955 seconds |
Test 1: dhry-nocache-O2, 250 ms Test 2: dhry-icdc-O2, 100 ms |
Test 3: mmu-nocache, 100 ms Test 4: mmu-icdc, 400 ms |
Test 5: basic-icdc, 40 ms Test 6: basic-nocache, 40 ms |
Test 7: mul-nocache-O2, 40 ms Test 8: mul-icdc-O2, 40 ms |
Test 9: except-nocache, 60 ms Test 10: except-icdc, 40 ms |
Test 11: cbasic-nocache-O2, 40 ms Test 12: cbasic-icdc-O0, 40 ms |
|
Iteration 1: OR1200_REGISTERED_OUTPUTS+FLASH_GENERIC+FLASH_GENERIC_REGISTERED+SRAM_GENERIC_REGISTERED |
Iteration 2: OR1200_REGISTERED_OUTPUTS+FLASH_GENERIC+OR1200_CLMODE_1TO2 |
Iteration 3: OR1200_REGISTERED_OUTPUTS |
|
<<< |
<<< Iteration 1: OR1200_REGISTERED_OUTPUTS+FLASH_GENERIC+FLASH_GENERIC_REGISTERED+SRAM_GENERIC_REGISTERED |
<<< |
|
@@@ |
@@@ Compiling sources |
@@@ |
@@@ Passed |
|
@@@ |
@@@ Building design hierarchy (elaboration) |
@@@ |
@@@ Passed |
|
### |
### Running test 1: dhry-nocache-O2, 250 ms |
### |
### Passed (@time 9127052.00) |
|
### |
### Running test 2: dhry-icdc-O2, 100 ms |
### |
### Passed (@time 6402152.00) |
<cut> |
|
Synthesis |
+++++++++ |
|
74,6 → 132,9
-- |
Damjan Lampret, Mar/2002 |
$Log: not supported by cvs2svn $ |
Revision 1.3 2002/03/28 17:48:07 lampret |
Changing directory structure ... |
|
Revision 1.2 2002/03/21 22:14:46 lampret |
Explained 10MHz. Fixed directory name. |
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