URL
https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk
Subversion Repositories dbg_interface
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 114 to Rev 115
- ↔ Reverse comparison
Rev 114 → Rev 115
/trunk/bench/verilog/dbg_tb.v
43,6 → 43,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.31 2004/01/20 09:07:44 mohor |
// CRC generation iand verification in bench changed. |
// |
// Revision 1.30 2004/01/20 08:03:35 mohor |
// IDCODE test improved. |
// |
415,7 → 418,8
// Testing read and write to internal registers |
#10000; |
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set_instruction(`IDCODE); |
// set_instruction(`IDCODE); |
set_instruction(4'b1100); |
read_id_code(id); |
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$display("\tRead ID = 0x%0x", id); |
632,6 → 636,7
endtask |
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|
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// sets the instruction to the IR register and goes to the RunTestIdle state |
task set_instruction; |
input [3:0] instr; |
638,7 → 643,21
integer i; |
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begin |
$display("(%0t) Task set_instruction", $time); |
case (instr) |
`EXTEST : $display("(%0t) Task set_instruction (EXTEST)", $time); |
`SAMPLE_PRELOAD : $display("(%0t) Task set_instruction (SAMPLE_PRELOAD)", $time); |
`IDCODE : $display("(%0t) Task set_instruction (IDCODE)", $time); |
`DEBUG : $display("(%0t) Task set_instruction (DEBUG)", $time); |
`MBIST : $display("(%0t) Task set_instruction (MBIST)", $time); |
`BYPASS : $display("(%0t) Task set_instruction (BYPASS)", $time); |
default |
begin |
$display("(%0t) Task set_instruction (Unsupported instruction !!!)", $time); |
$display("\tERROR: Unsupported instruction !!!", $time); |
$stop; |
end |
endcase |
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tms_pad_i<=#1 1; |
gen_clk(2); |
tms_pad_i<=#1 0; |