OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /
    from Rev 114 to Rev 115
    Reverse comparison

Rev 114 → Rev 115

/trunk/insight/gdb/config/or1k/tm-or1k.h
37,9 → 37,12
unsigned int num_matchpoints;
/* Number of currently used matchpoints. */
unsigned int num_used_matchpoints;
/* Has watchpoint driven counters. */
int has_counters;
/* Number of registers. */
unsigned int num_gpr_regs;
unsigned int num_vf_regs;
unsigned int num_vfpr_regs;
/* Is there any vf support? */
int vf_present;
};
 
91,27 → 94,29
#define SPR_GROUP_SIZE (1 << SPR_GROUP_SIZE_BITS)
#define SPR_SYSTEM_GROUP (0)
#define SPR_DEBUG_GROUP (6)
#define SPR_GPR (1024)
#define SPR_VFPR ((MAX_CID + 1) * MAX_GPR_REGS + SPR_GPR)
#define OR1K_NUM_SPR_GROUPS (11)
#define SPR_GPR_START (1024)
#define SPR_VFPR_START ((MAX_CID + 1) * MAX_GPR_REGS + SPR_GPR_START)
#define OR1K_NUM_SPR_GROUPS (12)
 
/* Define register values. */
#define SPR_REG(group, index) (((group) << SPR_GROUP_SIZE_BITS) + (index))
 
#define VR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 1)
#define UPR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 2)
#define SR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 3)
#define VR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 0)
#define UPR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 1)
#define CPUCFGR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 2)
#define DCFGR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 7)
#define PC_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 16)
#define SR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 17)
#define CCR_SPRNUM(cid) SPR_REG(SPR_SYSTEM_GROUP, 4 + (cid))
#define DVR0_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 0)
#define DCR0_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 8)
#define DMR1_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 16)
#define DMR2_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 17)
#define DCWR0_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 18)
#define DCWR1_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 19)
#define DSR_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 20)
#define DRR_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 21)
#define DIR_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 22)
#define PC_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 2)
#define DVR0_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 32)
#define DCR0_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 40)
#define DMR1_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 48)
#define DMR2_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 49)
#define DCWR0_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 50)
#define DCWR1_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 51)
#define DSR_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 52)
#define DRR_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 53)
#define DIR_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 54)
#define ZERO_REGNUM (0)
#define SP_REGNUM (1)
#define FP_REGNUM (2)
/trunk/insight/gdb/remote-or1k.c
331,6 → 331,7
{
struct cleanup *old_cleanups = make_cleanup (or1k_set_undefined_cleanups, NULL);
int i;
unsigned int tmp;
 
/* What is this code doing here? I don't see any way it can happen, and
it might mean or1k_initializing didn't get cleared properly.
350,14 → 351,19
/* Determine implementation configuration. */
or1k_implementation.VR = or1k_read_spr_reg (VR_SPRNUM);
or1k_implementation.UPR = or1k_read_spr_reg (UPR_SPRNUM);
/* Determine number of gpr_regs. */
tmp = or1k_read_spr_reg (CPUCFGR_SPRNUM);
or1k_implementation.num_gpr_regs = ((tmp >> 4) & 1)?(16):(32);
/* Is any vector or floating point support present? */
or1k_implementation.vf_present = ((tmp >> 7) & 7) != 0;
or1k_implementation.num_vfpr_regs = (or1k_implementation.vf_present)?(32):(0);
 
/* Determine max number of supported matchpoints. */
or1k_implementation.num_matchpoints = 2;
/* Determine max number of supported matchpoints. */
tmp = or1k_read_spr_reg (DCFGR_SPRNUM);
or1k_implementation.num_matchpoints = tmp & 7;
or1k_implementation.num_used_matchpoints = 0;
or1k_implementation.num_gpr_regs = 32;
/*!!! FINISH */
or1k_implementation.has_counters = tmp & 4 == 1;
 
 
/* Is implementation supported? */
 
/* First we should have system and debug groups implemented. */
365,9 → 371,9
error ("System group should be available in the or1k implementation.");
if (or1k_implementation.VR & (1 << SPR_DEBUG_GROUP) == 0)
error ("Debug group should be available in the or1k implementation.");
if (or1k_implementation.has_counters)
warning ("Counters not supported.");
 
 
 
/* Delete break, watch, catch points. */
for(i = 0; i < NUM_MATCHPOINTS; i++)
or1k_write_spr_reg (DCR0_SPRNUM + i, 0);
/trunk/insight/gdb/or1k-tdep.c
40,17 → 40,25
 
/* Group reg name size. See or1k_reg_names. */
int or1k_group_name_sizes[OR1K_NUM_SPR_GROUPS] = {
64, 0, 0, 6, 6, 2, (24+32+32), 16, 1, 3, 2};
80, 0, 0, 6, 4, 2,
23, 16, 1, 3, 2, 8};
 
/* Generated reg names. See or1k_spr_reg_name. */
int or1k_group_name_start[OR1K_NUM_SPR_GROUPS] = {
0, 0, 0, 253, 254, 256,
32, 248, 16, 16, 255, 0};
 
/* Generated reg names (max valid alias index).
See or1k_spr_reg_name. */
int or1k_spr_valid_aliases[OR1K_NUM_SPR_GROUPS] = {
64, 515, 515, 6, 6, 2, (24+32+32), 16, 1, 3, 2};
2047+1, 2047+1, 2047+1, 258+1, 257+1, 257+1,
79+1, 263+1, 16+1, 18+1, 256+1, 7+1};
 
/* Register names. */
char *or1k_reg_names[] = {
/* group 0 - general*/
"UPR", "VR", "PC", "SR", "EPCR0", "SPR0_5", "SPR0_6", "SPR0_7",
"SPR0_8", "SPR0_9", "SPR0_10", "SPR0_11", "SPR0_12", "SPR0_13", "SPR0_14", "SPR0_15",
/* group 0 - general*/
"VR", "UPR", "CPUCFGR", "DMMUCFGR", "IMMUCFGR", "DCCFGR", "ICCFGR", "DCFGR",
"PCCFGR", "SPR0_9", "SPR0_10", "SPR0_11", "SPR0_12", "SPR0_13", "SPR0_14", "SPR0_15",
"PC", "SR", "SPR0_18", "SPR0_19", "SPR0_20", "SPR0_21", "SPR0_22", "SPR0_23",
"EPCR0", "EPCR1", "EPCR2", "EPCR3", "EPCR4", "EPCR5", "EPCR6", "EPCR7",
"EPCR8", "EPCR9", "EPCR10", "EPCR11", "EPCR12", "EPCR13", "EPCR14", "EPCR15",
"EEAR0","EEAR1", "EEAR2", "EEAR3", "EEAR4", "EEAR5", "EEAR6", "EEAR7",
61,20 → 69,20
/* group 1 - Data MMU - not listed, generated */
/* group 2 - Instruction MMU - not listed, generated */
/* group 3 - Data cache */
"DCCR", "DCBPR", "DCBFR", "DCBIR", "DCBWR", "DCBLR",
"DCCR", "DCBIR", "DCBPR", "DCBFR", "DCBWR", "DCBLR",
/* group 4 - Instruction cache */
"ICCR", "ICBPR", "ICBFR", "ICBIR", "ICBWR", "ICBLR",
"ICCR", "ICBLR", "ICBIR", "ICBPR",
/* group 5 - MAC */
"MACLO", "MACHI",
/* group 6 - debug */
"DVR0", "DVR1", "DVR2", "DVR3", "DVR4", "DVR5", "DVR6", "DVR7",
"DCR0", "DCR1", "DCR2", "DCR3", "DCR4", "DCR5", "DCR6", "DCR7",
"DMR1", "DMR2", "DCWR0","DCWR1", "DSR", "DRR", "PC", "SPR6_23",
"DMR1", "DMR2", "DCWR0","DCWR1","DSR", "DRR", "DIR",
 
/* group 7 - performance counters unit */
"PCCM0", "PCMR1", "PCMR2", "PCMR3", "PCMR4", "PCMR5", "PCMR6", "PCMR7",
"PCCR0", "PCCR1", "PCCR2", "PCCR3", "PCCR4", "PCCR5", "PCCR6", "PCCR7",
"PCCM0", "PCMR1", "PCMR2", "PCMR3", "PCMR4", "PCMR5", "PCMR6", "PCMR7",
/* group 8 - power management */
"PMR",
82,7 → 90,10
"PICMR", "PICPR",
/* group 10 - tick timer */
"TTCR", "TTIR"
"TTMR", "TTCR",
 
/* group 11 - configureation */
"CPUCFGR", "DMMUCFGR", "IMMUCFGR", "DCCFGR", "ICCFGR", "SPR11_5", "DCFGR", "PCCFGR"
};
 
static char *or1k_gdb_reg_names[] = {
139,10 → 150,10
or1k_regnum_to_sprnum (int regno)
{
if (regno < MAX_GPR_REGS)
return SPR_REG(SPR_SYSTEM_GROUP, regno + CURRENT_CID * MAX_GPR_REGS + SPR_GPR);
return SPR_REG(SPR_SYSTEM_GROUP, regno + CURRENT_CID * MAX_GPR_REGS + SPR_GPR_START);
if (regno < MAX_GPR_REGS + MAX_VF_REGS)
return SPR_REG(SPR_SYSTEM_GROUP, regno - MAX_GPR_REGS
+ CURRENT_CID * MAX_GPR_REGS + SPR_VFPR);
+ CURRENT_CID * MAX_GPR_REGS + SPR_VFPR_START);
if (regno == PS_REGNUM)
return SR_SPRNUM;
if (regno == PC_REGNUM)
165,6 → 176,15
{
/* Names covered in or1k_reg_names. */
case 0:
/* Generate upper names. */
if (index >= SPR_GPR_START)
{
if (index < SPR_VFPR_START)
sprintf (tmp_name, "GPR%i", index - SPR_GPR_START);
else
sprintf (tmp_name, "VFR%i", index - SPR_VFPR_START);
return (char *)&tmp_name;
}
case 3:
case 4:
case 5:
184,56 → 204,45
return (char *)&tmp_name;
}
else
return or1k_reg_names[group_start + index];
}
return or1k_reg_names[group_start + index - or1k_group_name_start[group]];
}
/* Build names for DMMU group. */
case 1:
if (index < 256) {
sprintf (tmp_name, "DTLBMR%i", index);
return (char *)&tmp_name;
}
index -= 256;
if (index < 256) {
sprintf (tmp_name, "DTLBTR%i", index);
return (char *)&tmp_name;
}
index -= 256;
case 2:
strcpy (tmp_name, (group == 1)?"D":"I");
switch (index)
{
case 0:
return "DMMUCR";
case 1:
return "DMMUPR";
case 2:
return "DTLBEIR";
case 16:
return strcat (tmp_name, "MMUCR");
case 17:
return strcat (tmp_name, "MMUPR");
case 18:
return strcat (tmp_name, "TLBEIR");
case 24:
return strcat (tmp_name, "ATBMR0");
case 25:
return strcat (tmp_name, "ATBMR1");
case 26:
return strcat (tmp_name, "ATBMR2");
case 27:
return strcat (tmp_name, "ATBMR3");
case 28:
return strcat (tmp_name, "ATBTR0");
case 29:
return strcat (tmp_name, "ATBTR0");
case 30:
return strcat (tmp_name, "ATBTR0");
case 31:
return strcat (tmp_name, "ATBTR0");
default:
sprintf (tmp_name, "SPR1_%i", index+512);
if (index >= 1024) {
index -= 1024;
sprintf (tmp_name, "%sTLBW%iMR%i", (group == 1)?"D":"I", index / 128, index % 128);
return (char *)&tmp_name;
}
sprintf (tmp_name, "SPR%i_%i", group, index);
return (char *)&tmp_name;
}
/* Build names for IMMU group. */
case 2:
if (index < 256) {
sprintf (tmp_name, "ITLBMR%i", index);
return (char *)&tmp_name;
}
index -= 256;
if (index < 256) {
sprintf (tmp_name, "ITLBTR%i", index);
return (char *)&tmp_name;
}
index -= 256;
switch (index)
{
case 0:
return "IMMUCR";
case 1:
return "IMMUPR";
case 2:
return "ITLBEIR";
default:
sprintf (tmp_name, "SPR1_%i", index+512);
return (char *)&tmp_name;
}
default:
sprintf (tmp_name, "SPR%i_%i", group, index);
return (char *)&tmp_name;
886,6 → 895,8
help_list (setor1kcmdlist, "set or1k ", all_commands, gdb_stdout);
}
 
/* Parses args for spr name and puts result into group and index. */
 
static char *
parse_spr_params (args, group, index)
char *args;
941,12 → 952,20
*index = (int) strtoul (args, &ptr_c, 0);
if (*ptr_c != 0)
*index = or1k_regno_from_name (*group, args);
else *index = -1;
 
if (*index < 0)
{
printf_filtered ("No register supplied. Valid registers are:\n");
for (i = 0; i < or1k_spr_valid_aliases[*group]; i++)
printf_unfiltered ("%s\t", or1k_spr_register_name (SPR_REG(*group, i)));
printf_unfiltered ("\n");
{
char reg_name[16];
char *gen_name = or1k_spr_register_name (SPR_REG(*group, i));
sprintf (reg_name, "SPR%i_%i", *group, i);
if (strcmp (reg_name, gen_name) != 0)
printf_filtered ("%s\t", gen_name);
}
printf_filtered ("\n");
return args + strlen(args) + 1;
}
}
955,10 → 974,11
/* No parameters - print groups */
{
int i;
printf_unfiltered ("No parameter supplied. Valid groups are:\n");
printf_filtered ("No parameter supplied. Valid groups are:\n");
for (i = 0; i < OR1K_NUM_SPR_GROUPS; i++)
printf_unfiltered ("%s\t", or1k_group_names[i]);
printf_unfiltered ("\nSingle register name or register name or number after the group can be also supplied.\n");
printf_filtered ("%s\t", or1k_group_names[i]);
printf_filtered ("\nSingle register name or register name or number after the group can be also supplied.\n");
return args;
}
return args + strlen(args) + 1;
}
985,9 → 1005,6
{
int group, index;
char *nargs = parse_spr_params (args, &group, &index);
/* Any arguments left? */
if (args + strlen(args) >= nargs)
error ("Invalid register value.");
if (index >= 0)
{
unsigned long prev;
994,6 → 1011,10
unsigned long value;
char *ptr_c;
 
/* Any arguments left? */
if (args + strlen(args) >= nargs)
error ("Invalid register value.");
 
prev = or1k_read_spr_reg (SPR_REG(group, index));
 
ptr_c = nargs;
/trunk/gdb-5.0/gdb/remote-or1k.c
331,6 → 331,7
{
struct cleanup *old_cleanups = make_cleanup (or1k_set_undefined_cleanups, NULL);
int i;
unsigned int tmp;
 
/* What is this code doing here? I don't see any way it can happen, and
it might mean or1k_initializing didn't get cleared properly.
350,14 → 351,19
/* Determine implementation configuration. */
or1k_implementation.VR = or1k_read_spr_reg (VR_SPRNUM);
or1k_implementation.UPR = or1k_read_spr_reg (UPR_SPRNUM);
/* Determine number of gpr_regs. */
tmp = or1k_read_spr_reg (CPUCFGR_SPRNUM);
or1k_implementation.num_gpr_regs = ((tmp >> 4) & 1)?(16):(32);
/* Is any vector or floating point support present? */
or1k_implementation.vf_present = ((tmp >> 7) & 7) != 0;
or1k_implementation.num_vfpr_regs = (or1k_implementation.vf_present)?(32):(0);
 
/* Determine max number of supported matchpoints. */
or1k_implementation.num_matchpoints = 2;
/* Determine max number of supported matchpoints. */
tmp = or1k_read_spr_reg (DCFGR_SPRNUM);
or1k_implementation.num_matchpoints = tmp & 7;
or1k_implementation.num_used_matchpoints = 0;
or1k_implementation.num_gpr_regs = 32;
/*!!! FINISH */
or1k_implementation.has_counters = tmp & 4 == 1;
 
 
/* Is implementation supported? */
 
/* First we should have system and debug groups implemented. */
365,9 → 371,9
error ("System group should be available in the or1k implementation.");
if (or1k_implementation.VR & (1 << SPR_DEBUG_GROUP) == 0)
error ("Debug group should be available in the or1k implementation.");
if (or1k_implementation.has_counters)
warning ("Counters not supported.");
 
 
 
/* Delete break, watch, catch points. */
for(i = 0; i < NUM_MATCHPOINTS; i++)
or1k_write_spr_reg (DCR0_SPRNUM + i, 0);
/trunk/gdb-5.0/gdb/or1k-tdep.c
40,17 → 40,25
 
/* Group reg name size. See or1k_reg_names. */
int or1k_group_name_sizes[OR1K_NUM_SPR_GROUPS] = {
64, 0, 0, 6, 6, 2, (24+32+32), 16, 1, 3, 2};
80, 0, 0, 6, 4, 2,
23, 16, 1, 3, 2, 8};
 
/* Generated reg names. See or1k_spr_reg_name. */
int or1k_group_name_start[OR1K_NUM_SPR_GROUPS] = {
0, 0, 0, 253, 254, 256,
32, 248, 16, 16, 255, 0};
 
/* Generated reg names (max valid alias index).
See or1k_spr_reg_name. */
int or1k_spr_valid_aliases[OR1K_NUM_SPR_GROUPS] = {
64, 515, 515, 6, 6, 2, (24+32+32), 16, 1, 3, 2};
2047+1, 2047+1, 2047+1, 258+1, 257+1, 257+1,
79+1, 263+1, 16+1, 18+1, 256+1, 7+1};
 
/* Register names. */
char *or1k_reg_names[] = {
/* group 0 - general*/
"UPR", "VR", "PC", "SR", "EPCR0", "SPR0_5", "SPR0_6", "SPR0_7",
"SPR0_8", "SPR0_9", "SPR0_10", "SPR0_11", "SPR0_12", "SPR0_13", "SPR0_14", "SPR0_15",
/* group 0 - general*/
"VR", "UPR", "CPUCFGR", "DMMUCFGR", "IMMUCFGR", "DCCFGR", "ICCFGR", "DCFGR",
"PCCFGR", "SPR0_9", "SPR0_10", "SPR0_11", "SPR0_12", "SPR0_13", "SPR0_14", "SPR0_15",
"PC", "SR", "SPR0_18", "SPR0_19", "SPR0_20", "SPR0_21", "SPR0_22", "SPR0_23",
"EPCR0", "EPCR1", "EPCR2", "EPCR3", "EPCR4", "EPCR5", "EPCR6", "EPCR7",
"EPCR8", "EPCR9", "EPCR10", "EPCR11", "EPCR12", "EPCR13", "EPCR14", "EPCR15",
"EEAR0","EEAR1", "EEAR2", "EEAR3", "EEAR4", "EEAR5", "EEAR6", "EEAR7",
61,20 → 69,20
/* group 1 - Data MMU - not listed, generated */
/* group 2 - Instruction MMU - not listed, generated */
/* group 3 - Data cache */
"DCCR", "DCBPR", "DCBFR", "DCBIR", "DCBWR", "DCBLR",
"DCCR", "DCBIR", "DCBPR", "DCBFR", "DCBWR", "DCBLR",
/* group 4 - Instruction cache */
"ICCR", "ICBPR", "ICBFR", "ICBIR", "ICBWR", "ICBLR",
"ICCR", "ICBLR", "ICBIR", "ICBPR",
/* group 5 - MAC */
"MACLO", "MACHI",
/* group 6 - debug */
"DVR0", "DVR1", "DVR2", "DVR3", "DVR4", "DVR5", "DVR6", "DVR7",
"DCR0", "DCR1", "DCR2", "DCR3", "DCR4", "DCR5", "DCR6", "DCR7",
"DMR1", "DMR2", "DCWR0","DCWR1", "DSR", "DRR", "PC", "SPR6_23",
"DMR1", "DMR2", "DCWR0","DCWR1","DSR", "DRR", "DIR",
 
/* group 7 - performance counters unit */
"PCCM0", "PCMR1", "PCMR2", "PCMR3", "PCMR4", "PCMR5", "PCMR6", "PCMR7",
"PCCR0", "PCCR1", "PCCR2", "PCCR3", "PCCR4", "PCCR5", "PCCR6", "PCCR7",
"PCCM0", "PCMR1", "PCMR2", "PCMR3", "PCMR4", "PCMR5", "PCMR6", "PCMR7",
/* group 8 - power management */
"PMR",
82,7 → 90,10
"PICMR", "PICPR",
/* group 10 - tick timer */
"TTCR", "TTIR"
"TTMR", "TTCR",
 
/* group 11 - configureation */
"CPUCFGR", "DMMUCFGR", "IMMUCFGR", "DCCFGR", "ICCFGR", "SPR11_5", "DCFGR", "PCCFGR"
};
 
static char *or1k_gdb_reg_names[] = {
139,10 → 150,10
or1k_regnum_to_sprnum (int regno)
{
if (regno < MAX_GPR_REGS)
return SPR_REG(SPR_SYSTEM_GROUP, regno + CURRENT_CID * MAX_GPR_REGS + SPR_GPR);
return SPR_REG(SPR_SYSTEM_GROUP, regno + CURRENT_CID * MAX_GPR_REGS + SPR_GPR_START);
if (regno < MAX_GPR_REGS + MAX_VF_REGS)
return SPR_REG(SPR_SYSTEM_GROUP, regno - MAX_GPR_REGS
+ CURRENT_CID * MAX_GPR_REGS + SPR_VFPR);
+ CURRENT_CID * MAX_GPR_REGS + SPR_VFPR_START);
if (regno == PS_REGNUM)
return SR_SPRNUM;
if (regno == PC_REGNUM)
165,6 → 176,15
{
/* Names covered in or1k_reg_names. */
case 0:
/* Generate upper names. */
if (index >= SPR_GPR_START)
{
if (index < SPR_VFPR_START)
sprintf (tmp_name, "GPR%i", index - SPR_GPR_START);
else
sprintf (tmp_name, "VFR%i", index - SPR_VFPR_START);
return (char *)&tmp_name;
}
case 3:
case 4:
case 5:
184,56 → 204,45
return (char *)&tmp_name;
}
else
return or1k_reg_names[group_start + index];
}
return or1k_reg_names[group_start + index - or1k_group_name_start[group]];
}
/* Build names for DMMU group. */
case 1:
if (index < 256) {
sprintf (tmp_name, "DTLBMR%i", index);
return (char *)&tmp_name;
}
index -= 256;
if (index < 256) {
sprintf (tmp_name, "DTLBTR%i", index);
return (char *)&tmp_name;
}
index -= 256;
case 2:
strcpy (tmp_name, (group == 1)?"D":"I");
switch (index)
{
case 0:
return "DMMUCR";
case 1:
return "DMMUPR";
case 2:
return "DTLBEIR";
case 16:
return strcat (tmp_name, "MMUCR");
case 17:
return strcat (tmp_name, "MMUPR");
case 18:
return strcat (tmp_name, "TLBEIR");
case 24:
return strcat (tmp_name, "ATBMR0");
case 25:
return strcat (tmp_name, "ATBMR1");
case 26:
return strcat (tmp_name, "ATBMR2");
case 27:
return strcat (tmp_name, "ATBMR3");
case 28:
return strcat (tmp_name, "ATBTR0");
case 29:
return strcat (tmp_name, "ATBTR0");
case 30:
return strcat (tmp_name, "ATBTR0");
case 31:
return strcat (tmp_name, "ATBTR0");
default:
sprintf (tmp_name, "SPR1_%i", index+512);
if (index >= 1024) {
index -= 1024;
sprintf (tmp_name, "%sTLBW%iMR%i", (group == 1)?"D":"I", index / 128, index % 128);
return (char *)&tmp_name;
}
sprintf (tmp_name, "SPR%i_%i", group, index);
return (char *)&tmp_name;
}
/* Build names for IMMU group. */
case 2:
if (index < 256) {
sprintf (tmp_name, "ITLBMR%i", index);
return (char *)&tmp_name;
}
index -= 256;
if (index < 256) {
sprintf (tmp_name, "ITLBTR%i", index);
return (char *)&tmp_name;
}
index -= 256;
switch (index)
{
case 0:
return "IMMUCR";
case 1:
return "IMMUPR";
case 2:
return "ITLBEIR";
default:
sprintf (tmp_name, "SPR1_%i", index+512);
return (char *)&tmp_name;
}
default:
sprintf (tmp_name, "SPR%i_%i", group, index);
return (char *)&tmp_name;
886,6 → 895,8
help_list (setor1kcmdlist, "set or1k ", all_commands, gdb_stdout);
}
 
/* Parses args for spr name and puts result into group and index. */
 
static char *
parse_spr_params (args, group, index)
char *args;
941,12 → 952,20
*index = (int) strtoul (args, &ptr_c, 0);
if (*ptr_c != 0)
*index = or1k_regno_from_name (*group, args);
else *index = -1;
 
if (*index < 0)
{
printf_filtered ("No register supplied. Valid registers are:\n");
for (i = 0; i < or1k_spr_valid_aliases[*group]; i++)
printf_unfiltered ("%s\t", or1k_spr_register_name (SPR_REG(*group, i)));
printf_unfiltered ("\n");
{
char reg_name[16];
char *gen_name = or1k_spr_register_name (SPR_REG(*group, i));
sprintf (reg_name, "SPR%i_%i", *group, i);
if (strcmp (reg_name, gen_name) != 0)
printf_filtered ("%s\t", gen_name);
}
printf_filtered ("\n");
return args + strlen(args) + 1;
}
}
955,10 → 974,11
/* No parameters - print groups */
{
int i;
printf_unfiltered ("No parameter supplied. Valid groups are:\n");
printf_filtered ("No parameter supplied. Valid groups are:\n");
for (i = 0; i < OR1K_NUM_SPR_GROUPS; i++)
printf_unfiltered ("%s\t", or1k_group_names[i]);
printf_unfiltered ("\nSingle register name or register name or number after the group can be also supplied.\n");
printf_filtered ("%s\t", or1k_group_names[i]);
printf_filtered ("\nSingle register name or register name or number after the group can be also supplied.\n");
return args;
}
return args + strlen(args) + 1;
}
985,9 → 1005,6
{
int group, index;
char *nargs = parse_spr_params (args, &group, &index);
/* Any arguments left? */
if (args + strlen(args) >= nargs)
error ("Invalid register value.");
if (index >= 0)
{
unsigned long prev;
994,6 → 1011,10
unsigned long value;
char *ptr_c;
 
/* Any arguments left? */
if (args + strlen(args) >= nargs)
error ("Invalid register value.");
 
prev = or1k_read_spr_reg (SPR_REG(group, index));
 
ptr_c = nargs;
/trunk/gdb-5.0/gdb/config/or1k/tm-or1k.h
37,9 → 37,12
unsigned int num_matchpoints;
/* Number of currently used matchpoints. */
unsigned int num_used_matchpoints;
/* Has watchpoint driven counters. */
int has_counters;
/* Number of registers. */
unsigned int num_gpr_regs;
unsigned int num_vf_regs;
unsigned int num_vfpr_regs;
/* Is there any vf support? */
int vf_present;
};
 
91,27 → 94,29
#define SPR_GROUP_SIZE (1 << SPR_GROUP_SIZE_BITS)
#define SPR_SYSTEM_GROUP (0)
#define SPR_DEBUG_GROUP (6)
#define SPR_GPR (1024)
#define SPR_VFPR ((MAX_CID + 1) * MAX_GPR_REGS + SPR_GPR)
#define OR1K_NUM_SPR_GROUPS (11)
#define SPR_GPR_START (1024)
#define SPR_VFPR_START ((MAX_CID + 1) * MAX_GPR_REGS + SPR_GPR_START)
#define OR1K_NUM_SPR_GROUPS (12)
 
/* Define register values. */
#define SPR_REG(group, index) (((group) << SPR_GROUP_SIZE_BITS) + (index))
 
#define VR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 1)
#define UPR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 2)
#define SR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 3)
#define VR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 0)
#define UPR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 1)
#define CPUCFGR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 2)
#define DCFGR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 7)
#define PC_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 16)
#define SR_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 17)
#define CCR_SPRNUM(cid) SPR_REG(SPR_SYSTEM_GROUP, 4 + (cid))
#define DVR0_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 0)
#define DCR0_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 8)
#define DMR1_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 16)
#define DMR2_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 17)
#define DCWR0_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 18)
#define DCWR1_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 19)
#define DSR_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 20)
#define DRR_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 21)
#define DIR_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 22)
#define PC_SPRNUM SPR_REG(SPR_SYSTEM_GROUP, 2)
#define DVR0_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 32)
#define DCR0_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 40)
#define DMR1_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 48)
#define DMR2_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 49)
#define DCWR0_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 50)
#define DCWR1_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 51)
#define DSR_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 52)
#define DRR_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 53)
#define DIR_SPRNUM SPR_REG(SPR_DEBUG_GROUP, 54)
#define ZERO_REGNUM (0)
#define SP_REGNUM (1)
#define FP_REGNUM (2)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.