URL
https://opencores.org/ocsvn/pci/pci/trunk
Subversion Repositories pci
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 114 to Rev 115
- ↔ Reverse comparison
Rev 114 → Rev 115
/trunk/rtl/verilog/pci_bridge32.v
43,6 → 43,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.11 2003/08/08 16:36:33 tadejm |
// Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. |
// |
// Revision 1.10 2003/08/03 18:05:06 mihad |
// Added limited WISHBONE B3 support for WISHBONE Slave Unit. |
// Doesn't support full speed bursts yet. |
127,7 → 130,8
wbm_cyc_o, |
wbm_stb_o, |
wbm_we_o, |
wbm_cab_o, |
wbm_cti_o, |
wbm_bte_o, |
wbm_ack_i, |
wbm_rty_i, |
wbm_err_i, |
243,7 → 247,8
output wbm_cyc_o ; |
output wbm_stb_o ; |
output wbm_we_o ; |
output wbm_cab_o ; |
output [2:0] wbm_cti_o ; |
output [1:0] wbm_bte_o ; |
input wbm_ack_i ; |
input wbm_rty_i ; |
input wbm_err_i ; |
390,8 → 395,9
wire pciu_cyc_out ; |
wire pciu_stb_out ; |
wire pciu_we_out ; |
wire [2:0] pciu_cti_out ; |
wire [1:0] pciu_bte_out ; |
wire [3:0] pciu_sel_out ; |
wire pciu_cab_out ; |
wire pciu_pciif_trdy_out ; |
wire pciu_pciif_stop_out ; |
wire pciu_pciif_devsel_out ; |
421,12 → 427,13
|
// assign pci target unit's outputs to top outputs where possible |
assign wbm_adr_o = pciu_adr_out ; |
assign wbm_dat_o = pciu_mdata_out ; |
assign wbm_dat_o = pciu_mdata_out ; |
assign wbm_cyc_o = pciu_cyc_out ; |
assign wbm_stb_o = pciu_stb_out ; |
assign wbm_we_o = pciu_we_out ; |
assign wbm_cti_o = pciu_cti_out ; |
assign wbm_bte_o = pciu_bte_out ; |
assign wbm_sel_o = pciu_sel_out ; |
assign wbm_cab_o = pciu_cab_out ; |
|
// CONFIGURATION SPACE OUTPUTS |
wire [31:0] conf_w_data_out ; |
1014,17 → 1021,18
.reset_in (reset), |
.wb_clock_in (wb_clk), |
.pci_clock_in (pci_clk), |
.ADR_O (pciu_adr_out), |
.MDATA_O (pciu_mdata_out), |
.MDATA_I (pciu_mdata_in), |
.CYC_O (pciu_cyc_out), |
.STB_O (pciu_stb_out), |
.WE_O (pciu_we_out), |
.SEL_O (pciu_sel_out), |
.ACK_I (pciu_ack_in), |
.RTY_I (pciu_rty_in), |
.ERR_I (pciu_err_in), |
.CAB_O (pciu_cab_out), |
.pciu_wbm_adr_o (pciu_adr_out), |
.pciu_wbm_dat_o (pciu_mdata_out), |
.pciu_wbm_dat_i (pciu_mdata_in), |
.pciu_wbm_cyc_o (pciu_cyc_out), |
.pciu_wbm_stb_o (pciu_stb_out), |
.pciu_wbm_we_o (pciu_we_out), |
.pciu_wbm_cti_o (pciu_cti_out), |
.pciu_wbm_bte_o (pciu_bte_out), |
.pciu_wbm_sel_o (pciu_sel_out), |
.pciu_wbm_ack_i (pciu_ack_in), |
.pciu_wbm_rty_i (pciu_rty_in), |
.pciu_wbm_err_i (pciu_err_in), |
.pciu_mem_enable_in (pciu_mem_enable_in), |
.pciu_io_enable_in (pciu_io_enable_in), |
.pciu_map_in (pciu_map_in), |
/trunk/rtl/verilog/top.v
42,6 → 42,10
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.10 2003/08/03 18:05:06 mihad |
// Added limited WISHBONE B3 support for WISHBONE Slave Unit. |
// Doesn't support full speed bursts yet. |
// |
// Revision 1.9 2003/01/27 16:49:31 mihad |
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. |
// |
127,7 → 131,8
CYC_O, |
STB_O, |
WE_O, |
CAB_O, |
CTI_O, |
BTE_O, |
ACK_I, |
RTY_I, |
ERR_I |
190,7 → 195,8
output CYC_O ; |
output STB_O ; |
output WE_O ; |
output CAB_O ; |
output [2:0] CTI_O ; |
output [1:0] BTE_O ; |
input ACK_I ; |
input RTY_I ; |
input ERR_I ; |
301,7 → 307,8
.wbm_cyc_o(CYC_O), |
.wbm_stb_o(STB_O), |
.wbm_we_o (WE_O), |
.wbm_cab_o(CAB_O), |
.wbm_cti_o(CTI_O), |
.wbm_bte_o(BTE_O), |
.wbm_ack_i(ACK_I), |
.wbm_rty_i(RTY_I), |
.wbm_err_i(ERR_I), |