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Rev 1140 → Rev 1141
/trunk/orp/orp_soc/rtl/verilog/xsv_fpga_top.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.7 2003/04/07 01:28:17 lampret |
// Adding OR1200_CLMODE_1TO2 test code. |
// |
// Revision 1.6 2002/08/12 05:35:12 lampret |
// rty_i are unused - tied to zero. |
// |
537,15 → 540,12
// |
// This is purely for testing 1/2 WB clock |
// This should never be used when implementing in |
// an FPGA. |
// an FPGA. It is used only for simulation regressions. |
// |
`ifdef OR1200_CLMODE_1TO2 |
initial wb_clk = 0; |
//always @(posedge clk) |
// wb_clk = ~wb_clk; |
always @(clk) |
wb_clk = clk; |
|
always @(posedge clk) |
wb_clk = ~wb_clk; |
`else |
// |
// Some Xilinx P&R tools need this |