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URL https://opencores.org/ocsvn/8051/8051/trunk

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Rev 115 → Rev 116

/trunk/rtl/verilog/oc8051_b_register.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7 2003/01/13 14:14:40 simont
// replace some modules
//
// Revision 1.6 2002/09/30 17:33:59 simont
// prepared header
//
56,29 → 59,16
`include "oc8051_defines.v"
 
 
module oc8051_b_register (clk, rst, bit_in, bit_out, data_in, wr, wr_bit,
wr_addr, rd_addr, data_out, wr_sfr);
//
// clk (in) clock
// rst (in) reset
// bit_in (in) bit input - used in case of writing bits to b register (bit adddressable memory space - alu carry) [oc8051_alu.desCy]
// data_in (in) data input - used to write to b register [oc8051_alu.des1]
// wr (in) write - actine high [oc8051_decoder.wr -r]
// wr_bit (in) write bit addresable - actine high [oc8051_decoder.bit_addr -r]
// wr_addr (in) write address [oc8051_ram_wr_sel.out]
// data_out (out) data output [oc8051_ram_sel.b_reg]
// wr_sfr
//
module oc8051_b_register (clk, rst, bit_in, data_in, wr, wr_bit,
wr_addr, data_out, wr_sfr);
 
 
input clk, rst, wr, wr_bit, bit_in;
input [2:0] rd_addr, wr_sfr;
input [2:0] wr_sfr;
input [7:0] wr_addr, data_in;
 
output bit_out;
output [7:0] data_out;
 
reg bit_out;
reg [7:0] data_out;
 
//
101,14 → 91,4
end
end
 
always @(posedge clk or posedge rst)
begin
if (rst) bit_out <= #1 1'b0;
else if ((rd_addr==wr_addr[2:0]) & wr & wr_bit) begin
bit_out <= #1 bit_in;
end else if ((wr_addr==`OC8051_SFR_B) & wr & !wr_bit) begin
bit_out <= #1 data_in[rd_addr];
end else bit_out <= #1 data_out[rd_addr];
end
 
endmodule
/trunk/rtl/verilog/oc8051_acc.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9 2003/01/13 14:14:40 simont
// replace some modules
//
// Revision 1.8 2002/11/05 17:23:54 simont
// add module oc8051_sfr, 256 bytes internal ram
//
59,32 → 62,21
`include "oc8051_defines.v"
 
 
module oc8051_acc (clk, rst, bit_in, data_in, data2_in, wr, wr_bit, wr_addr, rd_addr,
data_out, bit_out, p, wr_sfr);
// clk (in) clock
// rst (in) reset
// bit_in (in) bit input - used in case of writing bits to acc (bit adddressable memory space - alu carry) [oc8051_alu.desCy]
// data_in (in) data input - used to write to acc (from alu destiantion 1) [oc8051_alu.des1]
// data2_in (in) data 2 input - write to acc, from alu detination 2 - instuctions mul and div [oc8051_alu.des2]
// wr (in) write - actine high [oc8051_decoder.wr -r]
// wr_bit (in) write bit addresable - actine high [oc8051_decoder.bit_addr -r]
// wr_addr (in) write address (if is addres of acc and white high must be written to acc) [oc8051_ram_wr_sel.out]
// data_out (out) data output [oc8051_alu_src1_sel.acc oc8051_alu_src2_sel.acc oc8051_comp.acc oc8051_ram_sel.acc]
// p (out) parity [oc8051_psw.p]
// mx_ext (in) mx extension
// wr_sfr
//
module oc8051_acc (clk, rst,
bit_in, data_in, data2_in,
data_out,
wr, wr_bit, wr_addr,
p, wr_sfr);
 
 
input clk, rst, wr, wr_bit, bit_in;
input [2:0] rd_addr, wr_sfr;
input [2:0] wr_sfr;
input [7:0] wr_addr, data_in, data2_in;
 
output p, bit_out;
output p;
output [7:0] data_out;
 
reg [7:0] data_out;
reg bit_out;
 
//
//calculates parity
112,17 → 104,5
end
end
 
always @(posedge clk or posedge rst)
begin
if (rst) bit_out <= #1 1'b0;
else if ((rd_addr==wr_addr[2:0]) & wr & wr_bit) begin
bit_out <= #1 bit_in;
end else if (((wr_addr==`OC8051_SFR_ACC) & wr & !wr_bit) || (wr_sfr==`OC8051_WRS_ACC1)) begin
bit_out <= #1 data_in[rd_addr];
end else if ((wr_sfr==`OC8051_WRS_ACC2) || (wr_sfr==`OC8051_WRS_BA)) begin
bit_out <= #1 data2_in[rd_addr];
end else bit_out <= #1 data_out[rd_addr];
end
 
endmodule
 
/trunk/rtl/verilog/oc8051_tc2.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2003/04/04 10:34:13 simont
// change timers to meet timing specifications (add divider with 12)
//
// Revision 1.1 2003/01/13 14:13:12 simont
// initial import
//
58,18 → 61,19
 
 
 
module oc8051_tc2 (clk, rst,
wr_addr, rd_addr,
data_in, data_out, bit_out,
wr, wr_bit, bit_in,
module oc8051_tc2 (clk, rst,
wr_addr,
data_in, bit_in,
wr, wr_bit,
t2, t2ex,
rclk, tclk,
rclk, tclk,
brate2, tc2_int,
pres_ow);
pres_ow,
//registers
t2con, tl2, th2, rcap2l, rcap2h);
 
input [7:0] wr_addr,
data_in,
rd_addr;
data_in;
input clk,
rst,
wr,
78,14 → 82,16
t2ex,
bit_in,
pres_ow; //prescalre owerflov
output [7:0] data_out;
output tc2_int,
bit_out,
rclk,
tclk,
output [7:0] t2con,
tl2,
th2,
rcap2l,
rcap2h;
output tc2_int,
rclk,
tclk,
brate2;
 
reg [7:0] data_out;
 
reg brate2;
reg [7:0] t2con, tl2, th2, rcap2l, rcap2h;
108,8 → 114,6
assign ct2 = t2con[1];
assign cprl2 = t2con[0];
 
assign bit_out = t2con[rd_addr[2:0]];
 
always @(posedge clk or posedge rst)
begin
if (rst) begin
239,7 → 243,6
tc2_event <= #1 1'b0;
t2_r <= #1 1'b1;
end else if (!t2 & t2_r) begin
// end if (t2_r) begin
tc2_event <= #1 1'b1;
t2_r <= #1 1'b0;
end else begin
247,16 → 250,4
end
end
 
always @(rd_addr or t2con or tl2 or th2 or rcap2l or rcap2h)
begin
case (rd_addr)
`OC8051_SFR_RCAP2H: data_out = rcap2h;
`OC8051_SFR_RCAP2L: data_out = rcap2l;
`OC8051_SFR_TH2: data_out = th2;
`OC8051_SFR_TL2: data_out = tl2;
default: data_out = t2con;
endcase
 
end
 
endmodule
/trunk/rtl/verilog/oc8051_sfr.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2003/04/07 13:29:16 simont
// change uart to meet timing.
//
// Revision 1.5 2003/04/04 10:35:07 simont
// signal prsc_ow added.
//
159,11 → 162,27
 
reg wr_bit_r;
reg [2:0] ram_wr_sel_r;
wire acc_bit, b_bit, psw_bit, port_bit, uart_bit, int_bit, tc2_bit, pca_bit;
 
//sfr's
wire acc_bit, b_bit, psw_bit, port_bit, uart_bit, int_bit, tc2_bit;
 
wire p, int_uart, tf0, tf1, tr0, tr1;
wire dps, rclk, tclk, brate2, tc2_int;
wire [7:0] b_reg, psw, ports, uart, int_out, tc_out, tc2, sp_out;
wire rclk, tclk, brate2, tc2_int;
 
wire [7:0] b_reg, psw,
//ports
p0_data, p1_data, p2_data, p3_data,
//interrupt control
ie, tcon, ip,
// t/c 2
t2con, tl2, th2, rcap2l, rcap2h,
// t/c 0,1
tmod, tl0, th0, tl1, th1,
// serial interface
scon, pcon, sbuf,
// stack
sp_out;
 
wire pres_ow;
 
assign cy = psw[7];
176,14 → 195,14
// ACC
oc8051_acc oc8051_acc1(.clk(clk), .rst(rst), .bit_in(bit_in), .data_in(dat1),
.data2_in(dat2), .wr(we), .wr_bit(wr_bit_r), .wr_sfr(wr_sfr),
.wr_addr(adr1), .rd_addr(adr0[2:0]), .data_out(acc), .bit_out(acc_bit), .p(p));
.wr_addr(adr1), .data_out(acc), .p(p));
 
 
//
// b register
// B
oc8051_b_register oc8051_b_register (.clk(clk), .rst(rst), .bit_in(bit_in), .bit_out(b_bit),
.data_in(dat1), .wr(we), .wr_bit(wr_bit_r), .wr_addr(adr1), .rd_addr(adr0[2:0]),
oc8051_b_register oc8051_b_register (.clk(clk), .rst(rst), .bit_in(bit_in),
.data_in(dat1), .wr(we), .wr_bit(wr_bit_r), .wr_addr(adr1),
.data_out(b_reg), .wr_sfr(wr_sfr));
 
//
204,8 → 223,8
//
//program status word
// PSW
oc8051_psw oc8051_psw1 (.clk(clk), .rst(rst), .wr_addr(adr1), .rd_addr(adr0[2:0]), .data_in(dat1),
.wr(we), .wr_bit(wr_bit_r), .data_out(psw), .bit_out(psw_bit), .p(p), .cy_in(bit_in),
oc8051_psw oc8051_psw1 (.clk(clk), .rst(rst), .wr_addr(adr1), .data_in(dat1),
.wr(we), .wr_bit(wr_bit_r), .data_out(psw), .p(p), .cy_in(bit_in),
.ac_in(desAc), .ov_in(desOv), .set(psw_set), .bank_sel(bank_sel));
 
//
212,45 → 231,49
// ports
// P0, P1, P2, P3
oc8051_ports oc8051_ports1(.clk(clk), .rst(rst), .bit_in(bit_in), .data_in(dat1), .wr(we),
.wr_bit(wr_bit_r), .wr_addr(adr1), .rd_addr(adr0), .rmw(rmw),
.data_out(ports), .bit_out(port_bit), .p0_out(p0_out), .p1_out(p1_out),
.p2_out(p2_out), .p3_out(p3_out), .p0_in(p0_in), .p1_in(p1_in), .p2_in(p2_in),
.p3_in(p3_in));
.wr_bit(wr_bit_r), .wr_addr(adr1), .rmw(rmw),
.p0_out(p0_out), .p1_out(p1_out), .p2_out(p2_out), .p3_out(p3_out),
.p0_in(p0_in), .p1_in(p1_in), .p2_in(p2_in), .p3_in(p3_in),
.p0_data(p0_data), .p1_data(p1_data), .p2_data(p2_data), .p3_data(p3_data));
 
//
// serial interface
// SCON, SBUF
oc8051_uart oc8051_uatr1 (.clk(clk), .rst(rst), .bit_in(bit_in), .rd_addr(adr0),
oc8051_uart oc8051_uatr1 (.clk(clk), .rst(rst), .bit_in(bit_in),
.data_in(dat1), .wr(we), .wr_bit(wr_bit_r), .wr_addr(adr1),
.data_out(uart), .bit_out(uart_bit), .rxd(rxd), .txd(txd), .intr(uart_int),
.rclk(rclk), .tclk(tclk), .brate2(brate2),
.t1_ow(tf1), .pres_ow(pres_ow));
.rxd(rxd), .txd(txd), .intr(uart_int),
.rclk(rclk), .tclk(tclk), .brate2(brate2),
.t1_ow(tf1), .pres_ow(pres_ow),
.scon(scon), .pcon(pcon), .sbuf(sbuf));
 
//
// interrupt control
// IP, IE, TCON
oc8051_int oc8051_int1 (.clk(clk), .rst(rst), .wr_addr(adr1), .rd_addr(adr0), .bit_in(bit_in),
.ack(int_ack), .data_in(dat1), .data_out(int_out), .bit_out(int_bit),
oc8051_int oc8051_int1 (.clk(clk), .rst(rst), .wr_addr(adr1), .bit_in(bit_in),
.ack(int_ack), .data_in(dat1),
.wr(we), .wr_bit(wr_bit_r),
.tf0(tf0), .tf1(tf1), .t2_int(tc2_int), .tr0(tr0), .tr1(tr1),
.ie0(int0), .ie1(int1),
.uart_int(uart_int),
.reti(reti), .intr(intr), .int_vec(int_src));
.reti(reti), .intr(intr), .int_vec(int_src),
.ie(ie), .tcon(tcon), .ip(ip));
 
 
//
// timer/counter control
// TH0, TH1, TL0, TH1, TMOD
oc8051_tc oc8051_tc1(.clk(clk), .rst(rst), .wr_addr(adr1), .rd_addr(adr0),
oc8051_tc oc8051_tc1(.clk(clk), .rst(rst), .wr_addr(adr1),
.data_in(dat1), .wr(we), .wr_bit(wr_bit_r), .ie0(int0), .ie1(int1), .tr0(tr0),
.tr1(tr1), .t0(t0), .t1(t1), .data_out(tc_out), .tf0(tf0), .tf1(tf1), .pres_ow(pres_ow));
.tr1(tr1), .t0(t0), .t1(t1), .tf0(tf0), .tf1(tf1), .pres_ow(pres_ow),
.tmod(tmod), .tl0(tl0), .th0(th0), .tl1(tl1), .th1(th1));
 
//
// timer/counter 2
// TH2, TH2, RCAPL2L, RCAPL2H, T2CON
oc8051_tc2 oc8051_tc21(.clk(clk), .rst(rst), .wr_addr(adr1), .rd_addr(adr0_r), .data_in(dat1), .wr(we),
.wr_bit(wr_bit_r), .bit_in(bit_in), .t2(t2), .t2ex(t2ex), .data_out(tc2), .bit_out(tc2_bit),
.rclk(rclk), .tclk(tclk), .brate2(brate2), .tc2_int(tc2_int), .pres_ow(pres_ow));
// TH2, TL2, RCAPL2L, RCAPL2H, T2CON
oc8051_tc2 oc8051_tc21(.clk(clk), .rst(rst), .wr_addr(adr1), .data_in(dat1), .wr(we),
.wr_bit(wr_bit_r), .bit_in(bit_in), .t2(t2), .t2ex(t2ex),
.rclk(rclk), .tclk(tclk), .brate2(brate2), .tc2_int(tc2_int), .pres_ow(pres_ow),
.t2con(t2con), .tl2(tl2), .th2(th2), .rcap2l(rcap2l), .rcap2h(rcap2h));
 
 
 
267,37 → 290,48
 
//
//set output in case of address (byte)
always @(adr0_r or psw or acc or dptr_hi or ports or sp_out or b_reg or uart or
tc_out or tc2 or int_out or dptr_lo)
always @(adr0_r or psw or acc or dptr_hi or dptr_lo or b_reg or
//ports
p0_data or p1_data or p2_data or p3_data or
//interrupt control
ie or tcon or ip or
// t/c 2
t2con or tl2 or th2 or rcap2l or rcap2h or
// t/c 0,1
tmod or tl0 or th0 or tl1 or th1 or
// serial interface
scon or pcon or sbuf or
// stack
sp_out)
begin
case (adr0_r)
`OC8051_SFR_ACC: dat0 = acc;
`OC8051_SFR_PSW: dat0 = psw;
`OC8051_SFR_P0: dat0 = ports;
`OC8051_SFR_P1: dat0 = ports;
`OC8051_SFR_P2: dat0 = ports;
`OC8051_SFR_P3: dat0 = ports;
`OC8051_SFR_SP: dat0 = sp_out;
`OC8051_SFR_B: dat0 = b_reg;
`OC8051_SFR_DPTR_HI: dat0 = dptr_hi;
`OC8051_SFR_DPTR_LO: dat0 = dptr_lo;
`OC8051_SFR_SCON: dat0 = uart;
`OC8051_SFR_SBUF: dat0 = uart;
`OC8051_SFR_PCON: dat0 = uart;
`OC8051_SFR_TH0: dat0 = tc_out;
`OC8051_SFR_TH1: dat0 = tc_out;
`OC8051_SFR_TL0: dat0 = tc_out;
`OC8051_SFR_TL1: dat0 = tc_out;
`OC8051_SFR_TMOD: dat0 = tc_out;
`OC8051_SFR_IP: dat0 = int_out;
`OC8051_SFR_IE: dat0 = int_out;
`OC8051_SFR_TCON: dat0 = int_out;
`OC8051_SFR_RCAP2H: dat0 = tc2;
`OC8051_SFR_RCAP2L: dat0 = tc2;
`OC8051_SFR_TH2: dat0 = tc2;
`OC8051_SFR_TL2: dat0 = tc2;
`OC8051_SFR_T2CON: dat0 = tc2;
default: dat0 = 8'h00;
`OC8051_SFR_ACC: dat0 = acc;
`OC8051_SFR_PSW: dat0 = psw;
`OC8051_SFR_P0: dat0 = p0_data;
`OC8051_SFR_P1: dat0 = p1_data;
`OC8051_SFR_P2: dat0 = p2_data;
`OC8051_SFR_P3: dat0 = p3_data;
`OC8051_SFR_SP: dat0 = sp_out;
`OC8051_SFR_B: dat0 = b_reg;
`OC8051_SFR_DPTR_HI: dat0 = dptr_hi;
`OC8051_SFR_DPTR_LO: dat0 = dptr_lo;
`OC8051_SFR_SCON: dat0 = scon;
`OC8051_SFR_SBUF: dat0 = sbuf;
`OC8051_SFR_PCON: dat0 = pcon;
`OC8051_SFR_TH0: dat0 = th0;
`OC8051_SFR_TH1: dat0 = th1;
`OC8051_SFR_TL0: dat0 = tl0;
`OC8051_SFR_TL1: dat0 = tl1;
`OC8051_SFR_TMOD: dat0 = tmod;
`OC8051_SFR_IP: dat0 = ip;
`OC8051_SFR_IE: dat0 = ie;
`OC8051_SFR_TCON: dat0 = tcon;
`OC8051_SFR_RCAP2H: dat0 = rcap2h;
`OC8051_SFR_RCAP2L: dat0 = rcap2l;
`OC8051_SFR_TH2: dat0 = th2;
`OC8051_SFR_TL2: dat0 = tl2;
`OC8051_SFR_T2CON: dat0 = t2con;
default: dat0 = 8'h00;
endcase
end
 
304,22 → 338,30
 
//
//set output in case of address (bit)
always @(adr0_r or b_bit or acc_bit or psw_bit or int_bit or port_bit or uart_bit or tc2_bit)
always @(adr0_r or psw or acc or b_reg or
//ports
p0_data or p1_data or p2_data or p3_data or
//interrupt control
ie or tcon or ip or
// t/c 2
t2con or
// serial interface
scon)
begin
case (adr0_r[7:3])
`OC8051_SFR_B_ACC: bit_out = acc_bit;
`OC8051_SFR_B_PSW: bit_out = psw_bit;
`OC8051_SFR_B_P0: bit_out = port_bit;
`OC8051_SFR_B_P1: bit_out = port_bit;
`OC8051_SFR_B_P2: bit_out = port_bit;
`OC8051_SFR_B_P3: bit_out = port_bit;
`OC8051_SFR_B_B: bit_out = b_bit;
`OC8051_SFR_B_IP: bit_out = int_bit;
`OC8051_SFR_B_IE: bit_out = int_bit;
`OC8051_SFR_B_TCON: bit_out = int_bit;
`OC8051_SFR_B_SCON: bit_out = uart_bit;
`OC8051_SFR_B_T2CON: bit_out = tc2_bit;
default: bit_out = 1'b0;
`OC8051_SFR_B_ACC: bit_out = acc[adr0_r[2:0]];
`OC8051_SFR_B_PSW: bit_out = psw[adr0_r[2:0]];
`OC8051_SFR_B_P0: bit_out = p0_data[adr0_r[2:0]];
`OC8051_SFR_B_P1: bit_out = p1_data[adr0_r[2:0]];
`OC8051_SFR_B_P2: bit_out = p2_data[adr0_r[2:0]];
`OC8051_SFR_B_P3: bit_out = p3_data[adr0_r[2:0]];
`OC8051_SFR_B_B: bit_out = b_reg[adr0_r[2:0]];
`OC8051_SFR_B_IP: bit_out = ip[adr0_r[2:0]];
`OC8051_SFR_B_IE: bit_out = ie[adr0_r[2:0]];
`OC8051_SFR_B_TCON: bit_out = tcon[adr0_r[2:0]];
`OC8051_SFR_B_SCON: bit_out = scon[adr0_r[2:0]];
`OC8051_SFR_B_T2CON: bit_out = t2con[adr0_r[2:0]];
default: bit_out = 1'b0;
endcase
end
 
/trunk/rtl/verilog/oc8051_int.v
46,6 → 46,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7 2003/03/28 17:45:57 simont
// change module name.
//
// Revision 1.6 2003/01/13 14:14:41 simont
// replace some modules
//
63,7 → 66,10
 
 
 
module oc8051_int (clk, rst, wr_addr, rd_addr, data_in, bit_in, data_out, bit_out, wr, wr_bit,
module oc8051_int (clk, rst,
wr_addr,
data_in, bit_in,
wr, wr_bit,
//timer interrupts
tf0, tf1, t2_int,
tr0, tr1,
72,19 → 78,23
//uart interrupts
uart_int,
//to cpu
intr, reti, int_vec, ack);
intr, reti, int_vec, ack,
//registers
ie, tcon, ip);
 
input [7:0] wr_addr, data_in, rd_addr;
input [7:0] wr_addr, data_in;
input wr, tf0, tf1, t2_int, ie0, ie1, clk, rst, reti, wr_bit, bit_in, ack, uart_int;
 
output tr0, tr1, intr, bit_out;
output [7:0] int_vec, data_out;
output tr0, tr1, intr;
output [7:0] int_vec,
ie,
tcon,
ip;
 
reg [7:0] ip, ie, int_vec, data_out;
reg [7:0] ip, ie, int_vec;
 
reg [3:0] tcon_s;
reg tcon_tf1, tcon_tf0, tcon_ie1, tcon_ie0, bit_out;
wire [7:0] tcon;
reg tcon_tf1, tcon_tf0, tcon_ie1, tcon_ie0;
 
//
// isrc processing interrupt sources
246,7 → 256,6
always @(posedge clk or posedge rst)
begin
if (rst) begin
// tcon_ie1 <=#1 `OC8051_RST_TCON[3];
tcon_ie1 <=#1 1'b0;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
tcon_ie1 <= #1 data_in[3];
331,21 → 340,6
 
 
always @(posedge clk or posedge rst)
begin
if (rst) data_out <= #1 8'h0;
else if (wr & !wr_bit & (wr_addr==rd_addr) & (
(wr_addr==`OC8051_SFR_IP) | (wr_addr==`OC8051_SFR_IE) | (wr_addr==`OC8051_SFR_TCON))) begin
data_out <= #1 data_in;
end else begin
case (rd_addr)
`OC8051_SFR_IP: data_out <= #1 ip;
`OC8051_SFR_IE: data_out <= #1 ie0;
default: data_out <= #1 tcon;
endcase
end
end
 
always @(posedge clk or posedge rst)
if (rst) begin
tf0_buff <= #1 1'b0;
tf1_buff <= #1 1'b0;
358,21 → 352,4
ie1_buff <= #1 ie1;
end
 
always @(posedge clk or posedge rst)
begin
if (rst) bit_out <= #1 1'b0;
else if (wr & wr_bit & (wr_addr==rd_addr)) begin
bit_out <= #1 bit_in;
end else if ((rd_addr[7:3]==wr_addr[7:3]) & wr & !wr_bit) begin
bit_out <= #1 data_in[rd_addr[2:0]];
end else begin
case (rd_addr[7:3])
`OC8051_SFR_B_IP: bit_out <= #1 ip[rd_addr[2:0]];
`OC8051_SFR_B_IE: bit_out <= #1 ie[rd_addr[2:0]];
default: bit_out <= #1 tcon[rd_addr[2:0]];
endcase
end
end
 
 
endmodule
/trunk/rtl/verilog/oc8051_tc.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2003/04/04 10:34:13 simont
// change timers to meet timing specifications (add divider with 12)
//
// Revision 1.5 2003/01/13 14:14:41 simont
// replace some modules
//
61,18 → 64,19
 
 
module oc8051_tc (clk, rst,
wr_addr, rd_addr,
data_in, data_out,
data_in,
wr_addr,
wr, wr_bit,
ie0, ie1,
tr0, tr1,
ie0, ie1,
tr0, tr1,
t0, t1,
tf0, tf1,
pres_ow);
pres_ow,
//registers
tmod, tl0, th0, tl1, th1);
 
input [7:0] wr_addr,
data_in,
rd_addr;
data_in;
input clk,
rst,
wr,
83,13 → 87,17
tr1,
t0,
t1;
output [7:0] data_out;
output [7:0] tmod,
tl0,
th0,
tl1,
th1;
output tf0,
tf1,
pres_ow;
 
 
reg [7:0] tmod, tl0, th0, tl1, th1, data_out;
reg [7:0] tmod, tl0, th0, tl1, th1;
reg tf0, tf1_0, tf1_1, t0_buff, t1_buff;
 
reg pres_ow;
218,23 → 226,6
end
end
 
always @(posedge clk or posedge rst)
begin
if (rst) data_out <= #1 8'h0;
else if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_TH0) |
(wr_addr==`OC8051_SFR_TH1)|(wr_addr==`OC8051_SFR_TL0)|(wr_addr==`OC8051_SFR_TL1)|
(wr_addr==`OC8051_SFR_TMOD))) begin
data_out <= #1 data_in;
end else begin
case (rd_addr)
`OC8051_SFR_TH0: data_out <= #1 th0;
`OC8051_SFR_TH1: data_out <= #1 th1;
`OC8051_SFR_TL0: data_out <= #1 tl0;
`OC8051_SFR_TL1: data_out <= #1 tl1;
default: data_out <= #1 tmod;
endcase
end
end
 
always @(posedge clk or posedge rst)
begin
/trunk/rtl/verilog/oc8051_ports.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7 2003/01/13 14:14:41 simont
// replace some modules
//
// Revision 1.6 2002/09/30 17:33:59 simont
// prepared header
//
57,8 → 60,13
`include "oc8051_defines.v"
 
 
module oc8051_ports (clk, rst, bit_in, data_in, wr, wr_bit, wr_addr, rd_addr, rmw, data_out, bit_out, p0_out, p1_out, p2_out, p3_out,
p0_in, p1_in, p2_in, p3_in);
module oc8051_ports (clk, rst,
bit_in, data_in,
wr, wr_bit,
wr_addr, rmw,
p0_out, p1_out, p2_out, p3_out,
p0_in, p1_in, p2_in, p3_in,
p0_data, p1_data, p2_data, p3_data);
//
// clk (in) clock
// rst (in) reset
76,14 → 84,18
 
 
input clk, rst, wr, wr_bit, bit_in, rmw;
input [7:0] wr_addr, rd_addr, data_in, p0_in, p1_in, p2_in, p3_in;
input [7:0] wr_addr, data_in, p0_in, p1_in, p2_in, p3_in;
 
output bit_out;
output [7:0] data_out, p0_out, p1_out, p2_out, p3_out;
output [7:0] p0_out, p1_out, p2_out, p3_out;
output [7:0] p0_data, p1_data, p2_data, p3_data;
 
reg bit_out;
reg [7:0] data_out, p0_out, p1_out, p2_out, p3_out;
reg [7:0] p0_out, p1_out, p2_out, p3_out;
 
assign p0_data = rmw ? p0_out : p0_in;
assign p1_data = rmw ? p1_out : p1_in;
assign p2_data = rmw ? p2_out : p2_in;
assign p3_data = rmw ? p3_out : p3_in;
 
//
// case of writing to port
always @(posedge clk or posedge rst)
117,58 → 129,6
end
end
 
//always @(p0_out or p0_in or p1_out or p1_in or p2_out or p2_in or p3_out or p3_in or rmw)
always @(posedge clk or posedge rst)
begin
if (rst)
data_out <= #1 8'h0;
else if (rmw) begin
if ((rd_addr==wr_addr) & wr & !wr_bit)
data_out <= #1 data_in;
else begin
case (rd_addr[5:4])
2'b00: data_out <= #1 p0_out;
2'b01: data_out <= #1 p1_out;
2'b10: data_out <= #1 p2_out;
2'b11: data_out <= #1 p3_out;
endcase
end
end else
case (rd_addr[5:4])
2'b00: data_out <= #1 p0_in;
2'b01: data_out <= #1 p1_in;
2'b10: data_out <= #1 p2_in;
2'b11: data_out <= #1 p3_in;
endcase
end
 
//always @(rmw or rd_addr or p0_out or p1_out or p2_out or p3_out or p0_in or p1_in or p2_in or p3_in)
always @(posedge clk or posedge rst)
begin
if (rst)
bit_out <= #1 1'b0;
else if (rmw) begin
if ((wr_addr==rd_addr) & wr & wr_bit)
bit_out <= #1 bit_in;
else if ((wr_addr[7:3]==rd_addr[7:3]) & wr)
bit_out <= #1 data_in[rd_addr[2:0]];
else begin
case (rd_addr[7:3])
`OC8051_SFR_B_P0: bit_out <= #1 p0_out[rd_addr[2:0]];
`OC8051_SFR_B_P1: bit_out <= #1 p1_out[rd_addr[2:0]];
`OC8051_SFR_B_P2: bit_out <= #1 p2_out[rd_addr[2:0]];
default: bit_out <= #1 p3_out[rd_addr[2:0]];
endcase
end
end else begin
case (rd_addr[7:3])
`OC8051_SFR_B_P0: bit_out <= #1 p0_in[rd_addr[2:0]];
`OC8051_SFR_B_P1: bit_out <= #1 p1_in[rd_addr[2:0]];
`OC8051_SFR_B_P2: bit_out <= #1 p2_in[rd_addr[2:0]];
default: bit_out <= #1 p3_in[rd_addr[2:0]];
endcase
end
end
 
endmodule
 
/trunk/rtl/verilog/oc8051_psw.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9 2003/01/13 14:14:41 simont
// replace some modules
//
// Revision 1.8 2002/11/05 17:23:54 simont
// add module oc8051_sfr, 256 bytes internal ram
//
60,7 → 63,7
`include "oc8051_defines.v"
 
 
module oc8051_psw (clk, rst, wr_addr, rd_addr, data_in, wr, wr_bit, data_out, bit_out, p,
module oc8051_psw (clk, rst, wr_addr, data_in, wr, wr_bit, data_out, p,
cy_in, ac_in, ov_in, set, bank_sel);
//
// clk (in) clock
69,7 → 72,6
// data_in (in) data input [oc8051_alu.des1]
// wr (in) write [oc8051_decoder.wr -r]
// wr_bit (in) write bit addresable [oc8051_decoder.bit_addr -r]
// data_out (out) data output [oc8051_ram_sel.psw]
// p (in) parity [oc8051_acc.p]
// cy_in (in) input bit data [oc8051_alu.desCy]
// ac_in (in) auxiliary carry input [oc8051_alu.desAc]
80,14 → 82,11
 
input clk, rst, wr, p, cy_in, ac_in, ov_in, wr_bit;
input [1:0] set;
input [2:0] rd_addr;
input [7:0] wr_addr, data_in;
 
output bit_out;
output [1:0] bank_sel;
output [7:0] data_out;
 
reg bit_out;
reg [7:0] data;
wire wr_psw;
 
94,7 → 93,6
assign wr_psw = (wr & (wr_addr==`OC8051_SFR_PSW) && !wr_bit);
 
assign bank_sel = wr_psw ? data_in[4:3]:data[4:3];
//assign bank_sel = data[4:3];
assign data_out = data;
 
//
140,14 → 138,4
end
end
 
always @(posedge clk or posedge rst)
begin
if (rst) bit_out <= #1 1'b0;
else if ((rd_addr==wr_addr[2:0]) & wr & wr_bit) begin
bit_out <= #1 cy_in;
end else if ((wr_addr==`OC8051_SFR_PSW) & wr & !wr_bit) begin
bit_out <= #1 data_in[rd_addr];
end else bit_out <= #1 data_out[rd_addr];
end
 
endmodule
/trunk/rtl/verilog/oc8051_uart.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.11 2003/04/07 13:29:16 simont
// change uart to meet timing.
//
// Revision 1.10 2003/01/13 14:14:41 simont
// replace some modules
//
60,13 → 63,14
 
module oc8051_uart (rst, clk,
bit_in, data_in,
rd_addr, wr_addr,
bit_out, data_out,
wr_addr,
wr, wr_bit,
rxd, txd,
rxd, txd,
intr,
brate2, t1_ow, pres_ow,
rclk, tclk);
rclk, tclk,
//registers
scon, pcon, sbuf);
 
input rst,
clk,
79,29 → 83,19
pres_ow,
rclk,
tclk;
input [7:0] rd_addr,
data_in,
input [7:0] data_in,
wr_addr;
 
output txd,
intr,
bit_out;
output [7:0] data_out;
intr;
output [7:0] scon,
pcon,
sbuf;
 
reg /*txd, */bit_out;
reg [7:0] data_out;
 
reg t1_ow_buf;
//reg tr_start, trans, trans_buf, t1_ow_buf;
//reg [5:0] smod_cnt_r, smod_cnt_t;
//reg receive, receive_buf, rxd_buf, r_int;
//
reg [7:0] /*sbuf_rxd, sbuf_txd, */scon, pcon;
//reg [10:0] sbuf_rxd_tmp;
//
//tr_count trancive counter
//re_count receive counter
//reg [3:0] tr_count, re_count, re_count_buff;
reg [7:0] scon, pcon;
 
 
reg txd,
119,7 → 113,7
reg [11:0] sbuf_rxd_tmp;
reg [12:0] sbuf_txd;
 
 
assign sbuf = sbuf_rxd;
assign intr = scon[1] | scon [0];
 
//
261,127 → 255,6
end
end
 
/*
//
// transmit
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
txd <= #1 1'b1;
tr_count <= #1 4'd0;
trans <= #1 1'b0;
smod_cnt_t <= #1 6'h0;
//
// start transmiting
//
end else if (tr_start) begin
case (scon[7:6])
2'b00: begin // mode 0
txd <= #1 sbuf_txd[0];
tr_count <= #1 4'd1;
end
2'b10: begin
txd <= #1 1'b0;
tr_count <= #1 4'd0;
end
default: begin // mode 1 and mode 3
tr_count <= #1 4'b1111;
end
endcase
trans <= #1 1'b1;
smod_cnt_t <= #1 6'h0;
//
// transmiting/
//
end else if (trans)
begin
case (scon[7:6])
2'b00: begin //mode 0
if (smod_cnt_t == 6'd12) begin
if (tr_count==4'd8)
begin
trans <= #1 1'b0;
txd <= #1 1'b1;
end else begin
txd <= #1 sbuf_txd[tr_count];
tr_count <= #1 tr_count + 4'b1;
end
smod_cnt_t <= #1 6'h0;
end else smod_cnt_t <= #1 smod_cnt_t + 6'h01;
end
2'b01: begin // mode 1
if ((t1_ow) & !(t1_ow_buf))
begin
if (((pcon[7]) & (smod_cnt_t == 6'd15))| (!(pcon[7]) & (smod_cnt_t==6'd31)))
begin
case (tr_count)
4'd8: txd <= #1 1'b1; // stop bit
4'd9: trans <= #1 1'b0;
4'b1111: txd <= #1 1'b0; //start bit
default: txd <= #1 sbuf_txd[tr_count];
endcase
tr_count <= #1 tr_count + 4'b1;
smod_cnt_t <= #1 6'h0;
end else smod_cnt_t <= #1 smod_cnt_t + 6'h01;
end
end
2'b10: begin // mode 2
//
// if smod (pcon[7]) is 1 count to 4 else count to 6
//
if (((pcon[7]) & (smod_cnt_t==6'd31)) | (!(pcon[7]) & (smod_cnt_t==6'd63))) begin
case (tr_count)
4'd8: begin
txd <= #1 scon[3];
end
4'd9: begin
txd <= #1 1'b1; //stop bit
end
4'd10: begin
trans <= #1 1'b0;
end
default: begin
txd <= #1 sbuf_txd[tr_count];
end
endcase
tr_count <= #1 tr_count+1'b1;
smod_cnt_t <= #1 6'h00;
end else begin
smod_cnt_t <= #1 smod_cnt_t + 6'h01;
end
end
default: begin // mode 3
if ((t1_ow) & !(t1_ow_buf))
begin
if (((pcon[7]) & (smod_cnt_t == 6'd15))| (!(pcon[7]) & (smod_cnt_t==6'd31)))
begin
case (tr_count)
4'd8: begin
txd <= #1 scon[3];
end
4'd9: begin
txd <= #1 1'b1; //stop bit
end
4'd10: begin
trans <= #1 1'b0;
end
4'b1111: txd <= #1 1'b0; //start bit
default: begin
txd <= #1 sbuf_txd[tr_count];
end
endcase
tr_count <= #1 tr_count+1'b1;
smod_cnt_t <= #1 6'h00;
end else smod_cnt_t <= #1 smod_cnt_t + 6'h01;
end
end
endcase
end else
txd <= #1 1'b1;
end
*/
 
//
//serial port buffer (receive)
399,11 → 272,7
end else if (!rx_done) begin
receive <= #1 1'b0;
rx_done <= #1 1'b1;
// if (scon[7:6]==2'b00) begin
sbuf_rxd <= #1 sbuf_rxd_tmp[10:3];
// end else begin
// sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
// end
sbuf_rxd <= #1 sbuf_rxd_tmp[10:3];
end else if (receive & (scon[7:6]==2'b00) & pres_ow) begin //mode 0
{sbuf_rxd_tmp, rx_done} <= #1 {rxd, sbuf_rxd_tmp};
end else if (receive & (scon[7:6]!=2'b00) & shift_re) begin //mode 1, 2, 3
466,176 → 335,21
end
 
 
/*
always @(posedge clk or posedge rst)
begin
if (rst) begin
re_count <= #1 4'd0;
receive <= #1 1'b0;
sbuf_rxd <= #1 8'h00;
sbuf_rxd_tmp <= #1 11'd0;
smod_cnt_r <= #1 6'h00;
r_int <= #1 1'b0;
end else if (receive) begin
case (scon[7:6])
2'b00: begin // mode 0
if (smod_cnt_r==6'd12) begin
if (re_count==4'd8) begin
receive <= #1 1'b0;
r_int <= #1 1'b1;
sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
end else begin
sbuf_rxd_tmp[re_count + 4'd1] <= #1 rxd;
r_int <= #1 1'b0;
end
re_count <= #1 re_count + 4'd1;
smod_cnt_r <= #1 6'h00;
end else smod_cnt_r <= #1 smod_cnt_r + 6'h01;
end
2'b01: begin // mode 1
if ((t1_ow) & !(t1_ow_buf))
begin
if (((pcon[7]) & (smod_cnt_r == 6'd15))| (!(pcon[7]) & (smod_cnt_r==6'd31)))
begin
r_int <= #1 1'b0;
re_count <= #1 re_count + 4'd1;
smod_cnt_r <= #1 6'h00;
sbuf_rxd_tmp[re_count_buff] <= #1 rxd;
if ((re_count==4'd0) && (rxd))
receive <= #1 1'b0;
 
end else smod_cnt_r <= #1 smod_cnt_r + 6'h01;
end else begin
r_int <= #1 1'b1;
if (re_count == 4'd10)
begin
sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
receive <= #1 1'b0;
r_int <= #1 1'b1;
end else r_int <= #1 1'b0;
end
end
2'b10: begin // mode 2
if (((pcon[7]) & (smod_cnt_r==6'd31)) | (!(pcon[7]) & (smod_cnt_r==6'd63))) begin
r_int <= #1 1'b0;
re_count <= #1 re_count + 4'd1;
smod_cnt_r <= #1 6'h00;
sbuf_rxd_tmp[re_count_buff] <= #1 rxd;
re_count <= #1 re_count + 4'd1;
end else begin
smod_cnt_r <= #1 smod_cnt_r + 6'h1;
if (re_count==4'd11) begin
sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
r_int <= #1 sbuf_rxd_tmp[0] | !scon[5];
receive <= #1 1'b0;
end else
r_int <= #1 1'b0;
end
end
default: begin // mode 3
if ((t1_ow) & !(t1_ow_buf))
begin
if (((pcon[7]) & (smod_cnt_r == 6'd15))| (!(pcon[7]) & (smod_cnt_r==6'd31)))
begin
sbuf_rxd_tmp[re_count] <= #1 rxd;
r_int <= #1 1'b0;
re_count <= #1 re_count + 4'd1;
smod_cnt_r <= #1 6'h00;
end else smod_cnt_r <= #1 smod_cnt_r + 6'h01;
end else begin
if (re_count==4'd11) begin
sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
receive <= #1 1'b0;
r_int <= #1 sbuf_rxd_tmp[0] | !scon[5];
end else begin
r_int <= #1 1'b0;
end
end
end
endcase
end else begin
case (scon[7:6])
2'b00: begin
if ((scon[4]) && !(scon[0]) && !(r_int)) begin
receive <= #1 1'b1;
smod_cnt_r <= #1 6'h6;
end
end
2'b10: begin
if ((scon[4]) && !(rxd)) begin
receive <= #1 1'b1;
if (pcon[7])
smod_cnt_r <= #1 6'd15;
else smod_cnt_r <= #1 6'd31;
end
end
default: begin
if ((scon[4]) && (!rxd)) begin
if (pcon[7])
smod_cnt_r <= #1 6'd7;
else smod_cnt_r <= #1 6'd15;
receive <= #1 1'b1;
end
end
endcase
 
sbuf_rxd_tmp <= #1 11'd0;
re_count <= #1 4'd0;
r_int <= #1 1'b0;
end
end
*/
 
//
//
//
always @(posedge clk or posedge rst)
begin
if (rst) data_out <= #1 8'h0;
else if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_PCON) |
(wr_addr==`OC8051_SFR_SCON))) begin
data_out <= #1 data_in;
end else begin
case (rd_addr)
`OC8051_SFR_SBUF: data_out <= #1 sbuf_rxd;
`OC8051_SFR_PCON: data_out <= #1 pcon;
default: data_out <= #1 scon;
endcase
end
end
 
 
always @(posedge clk or posedge rst)
begin
if (rst) begin
// trans_buf <= #1 1'b0;
// receive_buf <= #1 1'b0;
t1_ow_buf <= #1 1'b0;
// rxd_buf <= #1 1'b0;
end else begin
// trans_buf <= #1 trans;
// receive_buf <= #1 receive;
t1_ow_buf <= #1 t1_ow;
// rxd_buf <= #1 rxd;
end
end
 
 
always @(posedge clk or posedge rst)
begin
if (rst) bit_out <= #1 1'b0;
else if (wr & wr_bit & (rd_addr==wr_addr) & (wr_addr[7:3]==`OC8051_SFR_B_SCON)) begin
bit_out <= #1 bit_in;
end else
bit_out <= #1 scon[rd_addr[2:0]];
end
 
/*
always @(posedge clk or posedge rst)
if (rst)
re_count_buff <= #1 4'h4;
else re_count_buff <= #1 re_count;
*/
 
endmodule
 

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