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Rev 115 → Rev 116

/trunk/rtl/verilog/pci_target_unit.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.12 2003/08/08 16:36:33 tadejm
// Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.
//
// Revision 1.11 2003/01/27 16:49:31 mihad
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
//
91,17 → 94,19
reset_in,
wb_clock_in,
pci_clock_in,
ADR_O,
MDATA_O,
MDATA_I,
CYC_O,
STB_O,
WE_O,
SEL_O,
ACK_I,
RTY_I,
ERR_I,
CAB_O,
 
pciu_wbm_adr_o,
pciu_wbm_dat_o,
pciu_wbm_dat_i,
pciu_wbm_cyc_o,
pciu_wbm_stb_o,
pciu_wbm_we_o,
pciu_wbm_cti_o,
pciu_wbm_bte_o,
pciu_wbm_sel_o,
pciu_wbm_ack_i,
pciu_wbm_rty_i,
pciu_wbm_err_i,
pciu_mem_enable_in,
pciu_io_enable_in,
pciu_map_in,
188,17 → 193,18
wb_clock_in,
pci_clock_in ;
 
output [31:0] ADR_O ;
output [31:0] MDATA_O ;
input [31:0] MDATA_I ;
output CYC_O ;
output STB_O ;
output WE_O ;
output [3:0] SEL_O ;
input ACK_I ;
input RTY_I ;
input ERR_I ;
output CAB_O ;
output [31:0] pciu_wbm_adr_o ;
output [31:0] pciu_wbm_dat_o ;
input [31:0] pciu_wbm_dat_i ;
output pciu_wbm_cyc_o ;
output pciu_wbm_stb_o ;
output pciu_wbm_we_o ;
output [2:0] pciu_wbm_cti_o ;
output [1:0] pciu_wbm_bte_o ;
output [3:0] pciu_wbm_sel_o ;
input pciu_wbm_ack_i ;
input pciu_wbm_rty_i ;
input pciu_wbm_err_i ;
 
input pciu_wbw_fifo_empty_in ;
input pciu_wbu_del_read_comp_pending_in ;
398,10 → 404,11
wire wbm_sm_cyc_out ;
wire wbm_sm_stb_out ;
wire wbm_sm_we_out ;
wire [2:0] wbm_sm_cti_out ;
wire [1:0] wbm_sm_bte_out ;
wire [3:0] wbm_sm_sel_out ;
wire [31:0] wbm_sm_adr_out ;
wire [31:0] wbm_sm_mdata_out ;
wire wbm_sm_cab_out ;
 
assign pciu_err_addr_out = wbm_sm_adr_out ;
assign pciu_err_bc_out = wbm_sm_pci_error_bc ;
411,13 → 418,14
assign pciu_err_source_out = wbm_sm_error_source_out ;
assign pciu_err_rty_exp_out = wbm_sm_write_rty_cnt_exp_out ;
 
assign ADR_O = wbm_sm_adr_out ;
assign MDATA_O = wbm_sm_mdata_out ;
assign CYC_O = wbm_sm_cyc_out ;
assign STB_O = wbm_sm_stb_out ;
assign WE_O = wbm_sm_we_out ;
assign SEL_O = wbm_sm_sel_out ;
assign CAB_O = wbm_sm_cab_out ;
assign pciu_wbm_adr_o = wbm_sm_adr_out ;
assign pciu_wbm_dat_o = wbm_sm_mdata_out ;
assign pciu_wbm_cyc_o = wbm_sm_cyc_out ;
assign pciu_wbm_stb_o = wbm_sm_stb_out ;
assign pciu_wbm_we_o = wbm_sm_we_out ;
assign pciu_wbm_cti_o = wbm_sm_cti_out ;
assign pciu_wbm_bte_o = wbm_sm_bte_out ;
assign pciu_wbm_sel_o = wbm_sm_sel_out ;
 
// pciw_pcir fifo outputs
 
471,10 → 479,10
wire wbm_sm_pciw_fifo_almost_empty_in = fifos_pciw_almost_empty_out ;
wire wbm_sm_pciw_fifo_empty_in = fifos_pciw_empty_out ;
wire wbm_sm_pciw_fifo_transaction_ready_in = fifos_pciw_transaction_ready_out ;
wire [31:0] wbm_sm_mdata_in = MDATA_I ;
wire wbm_sm_ack_in = ACK_I ;
wire wbm_sm_rty_in = RTY_I ;
wire wbm_sm_err_in = ERR_I ;
wire [31:0] wbm_sm_mdata_in = pciu_wbm_dat_i ;
wire wbm_sm_ack_in = pciu_wbm_ack_i ;
wire wbm_sm_rty_in = pciu_wbm_rty_i ;
wire wbm_sm_err_in = pciu_wbm_err_i ;
 
// WISHBONE master interface instantiation
pci_wb_master wishbone_master
506,17 → 514,18
.write_rty_cnt_exp_out (wbm_sm_write_rty_cnt_exp_out),
.error_source_out (wbm_sm_error_source_out),
.read_rty_cnt_exp_out (wbm_sm_read_rty_cnt_exp_out),
.CYC_O (wbm_sm_cyc_out),
.STB_O (wbm_sm_stb_out),
.WE_O (wbm_sm_we_out),
.SEL_O (wbm_sm_sel_out),
.ADR_O (wbm_sm_adr_out),
.MDATA_I (wbm_sm_mdata_in),
.MDATA_O (wbm_sm_mdata_out),
.ACK_I (wbm_sm_ack_in),
.RTY_I (wbm_sm_rty_in),
.ERR_I (wbm_sm_err_in),
.CAB_O (wbm_sm_cab_out)
.wb_cyc_o (wbm_sm_cyc_out),
.wb_stb_o (wbm_sm_stb_out),
.wb_we_o (wbm_sm_we_out),
.wb_cti_o (wbm_sm_cti_out),
.wb_bte_o (wbm_sm_bte_out),
.wb_sel_o (wbm_sm_sel_out),
.wb_adr_o (wbm_sm_adr_out),
.wb_dat_i (wbm_sm_mdata_in),
.wb_dat_o (wbm_sm_mdata_out),
.wb_ack_i (wbm_sm_ack_in),
.wb_rty_i (wbm_sm_rty_in),
.wb_err_i (wbm_sm_err_in)
);
 
// pciw_pcir_fifos inputs
/trunk/rtl/verilog/pci_target32_interface.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8 2003/08/08 16:36:33 tadejm
// Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.
//
// Revision 1.7 2003/01/27 16:49:31 mihad
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
//
773,7 → 776,7
 
// when disconnect is signalled, the next data written to fifo will be the last
// also when this happens, disconnect must stay asserted until last data is written to the fifo
reg next_write_to_pciw_fifo_is_last ;
reg keep_desconnect_wo_data_set ;
 
// selecting "fifo data" from medium registers or from PCIR_FIFO
wire [31:0] pcir_fifo_data = (sel_fifo_mreg_in && !pcir_fifo_empty_in) ? pcir_fifo_data_in : pcir_fifo_data_reg ;
787,7 → 790,7
assign disconect_wo_data_out = (
((/*pcir_fifo_ctrl[`LAST_CTRL_BIT] ||*/ pcir_fifo_empty_in || ~burst_ok_out/*addr_burst_ok*/ || io_memory_bus_command) &&
~bc0_in && ~frame_reg_in) ||
((pciw_fifo_full_in || pciw_fifo_almost_full_in || next_write_to_pciw_fifo_is_last || pciw_fifo_two_left_in ||
((pciw_fifo_full_in || pciw_fifo_almost_full_in || keep_desconnect_wo_data_set || pciw_fifo_two_left_in ||
(pciw_fifo_three_left_in && pciw_fifo_wenable) || ~addr_burst_ok || io_memory_bus_command) &&
bc0_in && ~frame_reg_in)
) ;
838,13 → 841,14
always@(posedge clk_in or posedge reset_in)
begin
if (reset_in)
next_write_to_pciw_fifo_is_last <= #1 1'b0 ;
else if (next_write_to_pciw_fifo_is_last && pciw_fifo_wenable)
next_write_to_pciw_fifo_is_last <= #1 1'b0 ;
keep_desconnect_wo_data_set <= #1 1'b0 ;
else if (keep_desconnect_wo_data_set && pciw_fifo_wenable)
keep_desconnect_wo_data_set <= #1 1'b0 ;
else if (pciw_fifo_wenable && disconect_wo_data_out)
next_write_to_pciw_fifo_is_last <= #1 1'b1 ;
keep_desconnect_wo_data_set <= #1 1'b1 ;
end
 
 
// signal assignments from fifo to PCI Target FSM
assign wbw_fifo_empty_out = wbw_fifo_empty_in ;
assign wbu_del_read_comp_pending_out = wbu_del_read_comp_pending_in ;
864,27 → 868,25
begin
if (reset_in)
begin
pciw_fifo_wenable_out = 1'b0;
pciw_fifo_control_out = 4'h0;
pciw_fifo_wenable_out <= #1 1'b0;
pciw_fifo_control_out <= #1 4'h0;
// data and address outputs assignments to PCIW_FIFO - correction of 2 LSBits
pciw_fifo_addr_data_out = 32'h0;
pciw_fifo_cbe_out = 4'h0;
pciw_fifo_addr_data_out <= #1 32'h0;
pciw_fifo_cbe_out <= #1 4'h0;
end
else
begin
pciw_fifo_wenable_out = load_to_pciw_fifo_in ;
pciw_fifo_control_out[`ADDR_CTRL_BIT] = ~rdy_in ;
pciw_fifo_control_out[`BURST_BIT] = rdy_in ? ~frame_reg_in : 1'b0 ;
pciw_fifo_wenable_out <= #1 load_to_pciw_fifo_in ;
pciw_fifo_control_out[`ADDR_CTRL_BIT] <= #1 ~rdy_in ;
pciw_fifo_control_out[`BURST_BIT] <= #1 rdy_in ? ~frame_reg_in : 1'b0 ;
// if '1' then next burst BE is not equat to current one => burst will be chopped into single transfers
pciw_fifo_control_out[`DATA_ERROR_CTRL_BIT] = rdy_in && (next_be_in != be_in) && ~bckp_trdy_in; // valid comp.
pciw_fifo_control_out[`LAST_CTRL_BIT] = rdy_in && (next_write_to_pciw_fifo_is_last ||
last_reg_in || pciw_fifo_almost_full_in ||
~addr_burst_ok || io_memory_bus_command);
pciw_fifo_control_out[`DATA_ERROR_CTRL_BIT] <= #1 rdy_in && (next_be_in != be_in) && ~bckp_trdy_in; // valid comp.
pciw_fifo_control_out[`LAST_CTRL_BIT] <= #1 rdy_in && (frame_reg_in || (bckp_trdy_in && ~bckp_stop_in));
// data and address outputs assignments to PCIW_FIFO - correction of 2 LSBits
pciw_fifo_addr_data_out = rdy_in ? data_in : {norm_address[31:2],
pciw_fifo_addr_data_out <= #1 rdy_in ? data_in : {norm_address[31:2],
norm_address[1] && io_memory_bus_command,
norm_address[0] && io_memory_bus_command} ;
pciw_fifo_cbe_out = rdy_in ? be_in : norm_bc ;
pciw_fifo_cbe_out <= #1 rdy_in ? be_in : norm_bc ;
end
end
 

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