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https://opencores.org/ocsvn/rise/rise/trunk
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- from Rev 115 to Rev 116
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Rev 115 → Rev 116
/trunk/vhdl/wb_stage.vhd
125,12 → 125,17
wr <= '0'; |
wr_data <= (others => 'X'); |
rd_data <= (others => '0'); |
sendtouart <='0' |
else |
if sendtouart = '1' then |
if mem_wb_register.dreg_addr = '0' then |
address <=x"8001"; |
rd <= '0'; |
wr <= '1'; |
wr_data <= mem_wb_register.reg; |
wr <= '1'; |
end if; |
else |
rd <= '0'; |
wr <= '0'; |
end if; |
|
-- write back of register value. -- |
dreg_addr <= mem_wb_register.dreg_addr; |
if mem_wb_register.aluop1(ALUOP1_WB_REG_BIT) = '1' then |