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Rev 1154 → Rev 1155

/trunk/or1200/rtl/verilog/or1200_defines.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.33 2003/04/07 20:56:07 lampret
// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description.
//
// Revision 1.32 2003/04/07 01:26:57 lampret
// RFRAM defines comments updated. Altera LPM option added.
//
708,7 → 711,46
//
// Exceptions
//
 
//
// Exception vectors per OR1K architecture:
// 0xP0000100 - reset
// 0xP0000200 - bus error
// ... etc
// where P represents exception prefix.
//
// Exception vectors can be customized as per
// the following formula:
// 0xPMMMMNVV - exception N
//
// P represents exception prefix
// MMMM represents middle part that is usually 16 bits
// wide and starts with all bits zero
// N represents exception N
// VV represents length of the individual vector space,
// usually it is 8 bits wide and starts with all bits zero
//
 
//
// MMMM and VV parts
//
// Sum of these two defines needs to be 24
// (assuming N and P width are each 4 bits)
//
`define OR1200_EXCEPT_MMMM 16'h0000
`define OR1200_EXCEPT_VV 8'h00
 
//
// N part width
//
`define OR1200_EXCEPT_WIDTH 4
 
//
// Definition of exception vectors
//
// To avoid implementation of a certain exception,
// simply comment out corresponding line
//
`define OR1200_EXCEPT_UNUSED `OR1200_EXCEPT_WIDTH'hf
`define OR1200_EXCEPT_TRAP `OR1200_EXCEPT_WIDTH'he
`define OR1200_EXCEPT_BREAK `OR1200_EXCEPT_WIDTH'hd
/trunk/or1200/rtl/verilog/or1200_except.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.14 2002/09/03 22:28:21 lampret
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
//
// Revision 1.13 2002/08/28 01:44:25 lampret
// Removed some commented RTL. Fixed SR/ESR flag bug.
//
414,14 → 417,19
extend_flush <= #1 1'b1;
esr <= #1 sr_we ? to_sr : sr;
casex (except_trig)
`ifdef OR1200_EXCEPT_TICK
13'b1_xxxx_xxxx_xxxx: begin
except_type <= #1 `OR1200_EXCEPT_TICK;
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
end
`endif
`ifdef OR1200_EXCEPT_INT
13'b0_1xxx_xxxx_xxxx: begin
except_type <= #1 `OR1200_EXCEPT_INT;
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
end
`endif
`ifdef OR1200_EXCEPT_ITLBMISS
13'b0_01xx_xxxx_xxxx: begin
except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
//
434,6 → 442,8
// eear <= #1 ex_dslot ? ex_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
// epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
end
`endif
`ifdef OR1200_EXCEPT_IPF
13'b0_001x_xxxx_xxxx: begin
except_type <= #1 `OR1200_EXCEPT_IPF;
//
442,48 → 452,66
eear <= #1 ex_dslot ? ex_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
end
`endif
`ifdef OR1200_EXCEPT_BUSERR
13'b0_0001_xxxx_xxxx: begin
except_type <= #1 `OR1200_EXCEPT_BUSERR;
eear <= #1 ex_dslot ? wb_pc : ex_pc;
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
end
`endif
`ifdef OR1200_EXCEPT_ILLEGAL
13'b0_0000_1xxx_xxxx: begin
except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
eear <= #1 ex_pc;
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
end
`endif
`ifdef OR1200_EXCEPT_ALIGN
13'b0_0000_01xx_xxxx: begin
except_type <= #1 `OR1200_EXCEPT_ALIGN;
eear <= #1 lsu_addr;
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
end
`endif
`ifdef OR1200_EXCEPT_DTLBMISS
13'b0_0000_001x_xxxx: begin
except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
eear <= #1 lsu_addr;
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
end
`endif
`ifdef OR1200_EXCEPT_DPF
13'b0_0000_0001_xxxx: begin
except_type <= #1 `OR1200_EXCEPT_DPF;
eear <= #1 lsu_addr;
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
end
`endif
`ifdef OR1200_EXCEPT_BUSERR
13'b0_0000_0000_1xxx: begin // Data Bus Error
except_type <= #1 `OR1200_EXCEPT_BUSERR;
eear <= #1 lsu_addr;
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
end
`endif
`ifdef OR1200_EXCEPT_RANGE
13'b0_0000_0000_01xx: begin
except_type <= #1 `OR1200_EXCEPT_RANGE;
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
end
13'b0_0000_0000_001x: begin
`endif
`ifdef OR1200_EXCEPT_TRAP 13'b0_0000_0000_001x: begin
except_type <= #1 `OR1200_EXCEPT_TRAP;
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
end
`endif
`ifdef OR1200_EXCEPT_SYSCALL
13'b0_0000_0000_0001: begin
except_type <= #1 `OR1200_EXCEPT_SYSCALL;
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
end
`endif
default:
except_type <= #1 `OR1200_EXCEPT_NONE;
endcase
504,6 → 532,7
if (icpu_ack_i | icpu_err_i | genpc_freeze)
state <= #1 `OR1200_EXCEPTFSM_FLU2;
`OR1200_EXCEPTFSM_FLU2:
`ifdef OR1200_EXCEPT_TRAP
if (except_type == `OR1200_EXCEPT_TRAP) begin
state <= #1 `OR1200_EXCEPTFSM_IDLE;
extend_flush <= #1 1'b0;
511,6 → 540,7
except_type <= #1 `OR1200_EXCEPT_NONE;
end
else
`endif
state <= #1 `OR1200_EXCEPTFSM_FLU3;
`OR1200_EXCEPTFSM_FLU3:
begin
/trunk/or1200/rtl/verilog/or1200_genpc.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2002/03/29 15:16:55 lampret
// Some of the warnings fixed.
//
// Revision 1.5 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
252,7 → 255,7
$display("Starting exception: %h.", except_type);
// synopsys translate_on
`endif
pc = { {4{except_prefix}}, 16'h0000, except_type, 8'h00};
pc = { {4{except_prefix}}, `OR1200_EXCEPT_MMMM, except_type, `OR1200_EXCEPT_VV};
taken = 1'b1;
end
default: begin
272,7 → 275,8
//
always @(posedge clk or posedge rst)
if (rst)
pcreg <= #1 30'd63;
// pcreg <= #1 30'd63;
pcreg <= #1 ({`OR1200_EXCEPT_RESET, `OR1200_EXCEPT_VV} - 1) >> 2;
else if (spr_pc_we)
pcreg <= #1 spr_dat_i[31:2];
else if (no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)

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