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https://opencores.org/ocsvn/or1k/or1k/trunk
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- This comparison shows the changes necessary to convert path
/
- from Rev 1160 to Rev 1161
- ↔ Reverse comparison
Rev 1160 → Rev 1161
/trunk/or1200/rtl/verilog/or1200_immu_top.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.11 2002/10/17 20:04:40 lampret |
// Added BIST scan. Special VS RAMs need to be used to implement BIST. |
// |
// Revision 1.10 2002/09/16 03:08:56 lampret |
// Disabled cache inhibit atttribute. |
// |
195,11 → 198,11
wire miss; |
wire page_cross; |
reg [31:0] icpu_adr_o; |
reg [31:`OR1200_IMMU_PS] icpu_vpn_r; |
`ifdef OR1200_NO_IMMU |
`else |
reg itlb_en_r; |
reg dis_spr_access; |
reg [31:`OR1200_IMMU_PS] icpu_vpn_r; |
`endif |
|
// |
228,6 → 231,23
Unsupported !!! |
`endif |
|
// |
// Page cross |
// |
// Asserted when CPU address crosses page boundary. Most of the time it is zero. |
// |
assign page_cross = icpu_adr_i[31:`OR1200_IMMU_PS] != icpu_vpn_r; |
|
// |
// Register icpu_adr_i's VPN for use when IMMU is not enabled but PPN is expected to come |
// one clock cycle after offset part. |
// |
always @(posedge clk or posedge rst) |
if (rst) |
icpu_vpn_r <= #1 {31-`OR1200_IMMU_PS{1'b0}}; |
else |
icpu_vpn_r <= #1 icpu_adr_i[31:`OR1200_IMMU_PS]; |
|
`ifdef OR1200_NO_IMMU |
|
// |
236,7 → 256,7
assign spr_dat_o = 32'h00000000; |
assign icimmu_adr_o = icpu_adr_i; |
assign icpu_tag_o = icimmu_tag_i; |
assign icimmu_cycstb_o = icpu_cycstb_i; |
assign icimmu_cycstb_o = icpu_cycstb_i & ~page_cross; |
assign icpu_rty_o = icimmu_rty_i; |
assign icpu_err_o = icimmu_err_i; |
assign icimmu_ci_o = `OR1200_IMMU_CI; |
326,24 → 346,8
// no cache inhibit. |
assign icimmu_ci_o = `OR1200_IMMU_CI; |
|
// |
// Page cross |
// |
// Asserted when CPU address crosses page boundary. Most of the time it is zero. |
// |
assign page_cross = icpu_adr_i[31:`OR1200_IMMU_PS] != icpu_vpn_r; |
|
// |
// Register icpu_adr_i's VPN for use when IMMU is not enabled but PPN is expected to come |
// one clock cycle after offset part. |
// |
always @(posedge clk or posedge rst) |
if (rst) |
icpu_vpn_r <= #1 {31-`OR1200_IMMU_PS{1'b0}}; |
else |
icpu_vpn_r <= #1 icpu_adr_i[31:`OR1200_IMMU_PS]; |
|
// |
// Physical address is either translated virtual address or |
// simply equal when IMMU is disabled |
// |
/trunk/or1200/rtl/verilog/or1200_ic_fsm.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.7 2002/03/29 15:16:55 lampret |
// Some of the warnings fixed. |
// |
// Revision 1.6 2002/03/28 19:10:40 lampret |
// Optimized cache controller FSM. |
// |
145,7 → 148,7
// |
// Generate of ICRAM write enables |
// |
assign icram_we = {4{load & biudata_valid & !cache_inhibit}}; |
assign icram_we = {4{biu_read & biudata_valid & !cache_inhibit}}; |
assign tag_we = biu_read & biudata_valid & !cache_inhibit; |
|
// |