URL
https://opencores.org/ocsvn/8051/8051/trunk
Subversion Repositories 8051
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 117 to Rev 118
- ↔ Reverse comparison
Rev 117 → Rev 118
/trunk/rtl/verilog/oc8051_defines.v
339,11 → 339,10
// |
//write sfr |
// |
`define OC8051_WRS_N 3'b000 //no |
`define OC8051_WRS_ACC1 3'b001 // acc destination 1 |
`define OC8051_WRS_ACC2 3'b010 // acc destination 2 |
`define OC8051_WRS_DPTR 3'b011 // data pointer |
`define OC8051_WRS_BA 3'b100 // a, b register |
`define OC8051_WRS_N 2'b00 //no |
`define OC8051_WRS_ACC1 2'b01 // acc destination 1 |
`define OC8051_WRS_ACC2 2'b10 // acc destination 2 |
`define OC8051_WRS_DPTR 2'b11 // data pointer |
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// |
370,6 → 369,7
`define OC8051_RWS_SP 3'b011 // stack pointer |
`define OC8051_RWS_D3 3'b101 // direct address (op3) |
`define OC8051_RWS_D1 3'b110 // direct address (op1) |
`define OC8051_RWS_B 3'b111 // b register |
`define OC8051_RWS_DC 3'b000 // |
|
// |
/trunk/rtl/verilog/oc8051_b_register.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.8 2003/04/07 14:58:02 simont |
// change sfr's interface. |
// |
// Revision 1.7 2003/01/13 14:14:40 simont |
// replace some modules |
// |
60,11 → 63,10
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|
module oc8051_b_register (clk, rst, bit_in, data_in, wr, wr_bit, |
wr_addr, data_out, wr_sfr); |
wr_addr, data_out); |
|
|
input clk, rst, wr, wr_bit, bit_in; |
input [2:0] wr_sfr; |
input [7:0] wr_addr, data_in; |
|
output [7:0] data_out; |
78,8 → 80,6
begin |
if (rst) |
data_out <= #1 `OC8051_RST_B; |
else if (wr_sfr==`OC8051_WRS_BA) |
data_out <= #1 data_in; |
else if (wr) begin |
if (!wr_bit) begin |
if (wr_addr==`OC8051_SFR_B) |
/trunk/rtl/verilog/oc8051_acc.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.11 2003/04/09 15:49:42 simont |
// Register oc8051_sfr dato output, add signal wait_data. |
// |
// Revision 1.10 2003/04/07 14:58:02 simont |
// change sfr's interface. |
// |
73,7 → 76,7
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|
input clk, rst, wr, wr_bit, bit_in; |
input [2:0] wr_sfr; |
input [1:0] wr_sfr; |
input [7:0] wr_addr, data_in, data2_in; |
|
output p; |
88,7 → 91,7
assign p = ^acc; |
|
assign wr_acc = (wr_sfr==`OC8051_WRS_ACC1) | (wr & !wr_bit & (wr_addr==`OC8051_SFR_ACC)); |
assign wr2_acc = (wr_sfr==`OC8051_WRS_ACC2) | (wr_sfr==`OC8051_WRS_BA); |
assign wr2_acc = (wr_sfr==`OC8051_WRS_ACC2); |
assign wr_bit_acc = (wr & wr_bit & (wr_addr[7:3]==`OC8051_SFR_B_ACC)); |
// |
//writing to acc |
/trunk/rtl/verilog/oc8051_memory_interface.v
44,7 → 44,10
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2003/01/13 14:13:12 simont |
// initial import |
// |
// |
|
// synopsys translate_off |
`include "oc8051_timescale.v" |
265,10 → 268,11
begin |
case (wr_sel) |
`OC8051_RWS_RN : wr_addr = {3'h0, rn_r}; |
`OC8051_RWS_I : wr_addr = ri_r; |
`OC8051_RWS_D : wr_addr = imm_r; |
`OC8051_RWS_I : wr_addr = ri_r; |
`OC8051_RWS_D : wr_addr = imm_r; |
`OC8051_RWS_SP : wr_addr = sp_w; |
`OC8051_RWS_D3 : wr_addr = imm2_r; |
`OC8051_RWS_B : wr_addr = `OC8051_SFR_B; |
default : wr_addr = 2'bxx; |
endcase |
end |
/trunk/rtl/verilog/oc8051_sfr.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.8 2003/04/09 15:49:42 simont |
// Register oc8051_sfr dato output, add signal wait_data. |
// |
// Revision 1.7 2003/04/07 14:58:02 simont |
// change sfr's interface. |
// |
155,8 → 158,8
|
input rst, clk, we, bit_in, desAc, desOv, rmw, rxd, t2, t2ex; |
input int_ack, int0, int1, reti, wr_bit, t0, t1; |
input [1:0] psw_set; |
input [2:0] ram_rd_sel, ram_wr_sel, wr_sfr; |
input [1:0] psw_set, wr_sfr; |
input [2:0] ram_rd_sel, ram_wr_sel; |
input [7:0] adr0, adr1, dat1, dat2, p0_in, p1_in, p2_in, p3_in; |
|
output bit_out, txd, intr, srcAc, cy, wait_data; |
212,7 → 215,7
// B |
oc8051_b_register oc8051_b_register (.clk(clk), .rst(rst), .bit_in(bit_in), |
.data_in(dat1), .wr(we), .wr_bit(wr_bit_r), .wr_addr(adr1), |
.data_out(b_reg), .wr_sfr(wr_sfr)); |
.data_out(b_reg)); |
|
// |
//stack pointer |
399,7 → 402,7
end else if ( |
(((wr_sfr==`OC8051_WRS_ACC1) & (adr0==`OC8051_SFR_ACC)) | //write to acc |
((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) | //write to dpl |
((wr_sfr==`OC8051_WRS_BA) & (adr0==`OC8051_SFR_B)) | //write to b |
// ((wr_sfr==`OC8051_WRS_BA) & (adr0==`OC8051_SFR_B)) | //write to b |
(adr1[7] & (adr1==adr0) & we & !wr_bit_r)) & !wait_data) begin //write and read same address |
// dat0 <= #1 dat1; |
wait_data <= #1 1'b1; |
406,8 → 409,9
|
end else if ( |
(((wr_sfr==`OC8051_WRS_ACC2) & (adr0==`OC8051_SFR_ACC)) | //write to acc |
((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_HI)) | //write to dph |
((wr_sfr==`OC8051_WRS_BA) & (adr0==`OC8051_SFR_ACC))) & !wait_data) begin //write to b |
((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_HI)) //write to dph |
// ((wr_sfr==`OC8051_WRS_BA) & (adr0==`OC8051_SFR_ACC)) |
) & !wait_data) begin //write to b |
// dat0 <= #1 dat2; |
wait_data <= #1 1'b1; |
|
457,8 → 461,9
bit_out <= #1 1'h0; |
else if ( |
((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) & we & !wr_bit_r) | |
((wr_sfr==`OC8051_WRS_ACC1) & (adr0[7:3]==`OC8051_SFR_B_ACC)) | //write to acc |
((wr_sfr==`OC8051_WRS_BA) & (adr0[7:3]==`OC8051_SFR_B_B))) //write to b |
((wr_sfr==`OC8051_WRS_ACC1) & (adr0[7:3]==`OC8051_SFR_B_ACC)) //write to acc |
// ((wr_sfr==`OC8051_WRS_BA) & (adr0[7:3]==`OC8051_SFR_B_B)) |
) //write to b |
|
bit_out <= #1 dat1[adr0[2:0]]; |
else if ((adr1==adr0) & we & wr_bit_r) |
/trunk/rtl/verilog/oc8051_top.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.21 2003/04/09 15:49:42 simont |
// Register oc8051_sfr dato output, add signal wait_data. |
// |
// Revision 1.20 2003/04/03 19:13:28 simont |
// Include instruction cache. |
// |
149,7 → 152,8
// ram_wr_sel ram write (internal) |
// src_sel1, src_sel2 from decoder to register |
wire src_sel3; |
wire [2:0] ram_rd_sel, ram_wr_sel, wr_sfr; |
wire [1:0] wr_sfr; |
wire [2:0] ram_rd_sel, ram_wr_sel; |
wire [2:0] src_sel2, src_sel1; |
|
// |
352,7 → 356,8
|
oc8051_sfr oc8051_sfr1(.rst(wb_rst_i), .clk(wb_clk_i), .adr0(rd_addr[7:0]), .adr1(wr_addr[7:0]), |
.dat0(sfr_out), .dat1(wr_dat), .dat2(des2), .we(wr_o && !wr_ind), .bit_in(desCy), |
.bit_out(sfr_bit), .wr_bit(bit_addr_o), .ram_rd_sel(ram_rd_sel), .ram_wr_sel(ram_wr_sel), .wr_sfr(wr_sfr), |
.bit_out(sfr_bit), .wr_bit(bit_addr_o), .ram_rd_sel(ram_rd_sel), .ram_wr_sel(ram_wr_sel), |
.wr_sfr(wr_sfr), |
// acc |
.acc(acc), |
// sp |
/trunk/rtl/verilog/oc8051_decoder.v
45,6 → 45,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.15 2003/04/09 15:49:42 simont |
// Register oc8051_sfr dato output, add signal wait_data. |
// |
// Revision 1.14 2003/01/13 14:14:40 simont |
// replace some modules |
// |
102,16 → 105,16
input [7:0] op_in; |
|
output wr_o, bit_addr, pc_wr, rmw, istb, src_sel3; |
output [1:0] psw_set, cy_sel, comp_sel; |
output [2:0] mem_act, src_sel1, src_sel2, ram_rd_sel_o, ram_wr_sel_o, pc_sel, wr_sfr_o, op1_c; |
output [1:0] psw_set, cy_sel, wr_sfr_o, comp_sel; |
output [2:0] mem_act, src_sel1, src_sel2, ram_rd_sel_o, ram_wr_sel_o, pc_sel, op1_c; |
output [3:0] alu_op_o; |
output rd; |
|
reg rmw; |
reg src_sel3, wr, bit_addr, pc_wr; |
reg [1:0] comp_sel, psw_set, cy_sel; |
reg [1:0] comp_sel, psw_set, cy_sel, wr_sfr; |
reg [3:0] alu_op; |
reg [2:0] src_sel2, mem_act, src_sel1, ram_wr_sel, ram_rd_sel, pc_sel, wr_sfr; |
reg [2:0] src_sel2, mem_act, src_sel1, ram_wr_sel, ram_rd_sel, pc_sel; |
|
// |
// state if 2'b00 then normal execution, sle instructin that need more than one clock |
1625,26 → 1628,26
wr_sfr <= #1 `OC8051_WRS_N; |
end |
`OC8051_DIV : begin |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
ram_wr_sel <= #1 `OC8051_RWS_B; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_RAM; |
alu_op <= #1 `OC8051_ALU_DIV; |
wr <= #1 1'b0; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_OV; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_BA; |
wr_sfr <= #1 `OC8051_WRS_ACC2; |
end |
`OC8051_MUL : begin |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
ram_wr_sel <= #1 `OC8051_RWS_B; |
src_sel1 <= #1 `OC8051_AS1_ACC; |
src_sel2 <= #1 `OC8051_AS2_RAM; |
alu_op <= #1 `OC8051_ALU_MUL; |
wr <= #1 1'b0; |
wr <= #1 1'b1; |
psw_set <= #1 `OC8051_PS_OV; |
cy_sel <= #1 `OC8051_CY_0; |
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_BA; |
wr_sfr <= #1 `OC8051_WRS_ACC2; |
end |
default begin |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
/trunk/rtl/verilog/oc8051_dptr.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2003/01/13 14:14:40 simont |
// replace some modules |
// |
// Revision 1.2 2002/09/30 17:33:59 simont |
// prepared header |
// |
72,7 → 75,7
|
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input clk, rst, wr, wr_bit; |
input [2:0] wr_sfr; |
input [1:0] wr_sfr; |
input [7:0] addr, data_in, data2_in; |
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output [7:0] data_hi, data_lo; |