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Rev 117 → Rev 118

/sdhc-sc-core/trunk/src/grpGlobal/pkgGlobal/src/Global-p.vhdl
1,10 → 1,12
-------------------------------------------------
-- file: Global-p.vhdl
-- author: Rainer Kastl
--
-- Global package contains constants and functions
-- Title: -
-- File: Global-p.vhdl
-- Author: Copyright 2010: Rainer Kastl
-- Standard: VHDL'93
--
-- Description: Global package contains constants and functions
-- for use everywhere.
-------------------------------------------------
--
 
library ieee;
use ieee.std_logic_1164.all;
21,6 → 23,12
 
function LogDualis(cNumber : natural) return natural;
 
 
-- Edge detector
constant cDetectRisingEdge : natural := 0;
constant cDetectFallingEdge : natural := 1;
constant cDetectAnyEdge : natural := 2;
 
end package Global;
 
package body Global is
/sdhc-sc-core/trunk/src/grpStrobesClocks/unitEdgeDetector/src/tbEdgeDetection-Bhv-ea.vhdl
0,0 → 1,134
-------------------------------------------------------------------------------
-- Title : Tests
-- Project : EdgeDetector
-------------------------------------------------------------------------------
-- File : tbEdgeDetection-Bhv-ea.vhd
-- Author : Rainer Kastl <hse05015@fh-hagenberg.at>
-- Company : FH-Hagenberg
-- Created : 2006-12-12
-- Last update: 2006-12-18
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Testing of EdgeDetector
-------------------------------------------------------------------------------
-- Copyright (c) 2006 FH-Hagenberg
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2006-12-12 1.0 Rainer Kastl <hse05015@fh-hagenberg.at> Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.Global.all;
 
entity tbEdgeDet is
 
end entity tbEdgeDet;
 
architecture Bhv of tbEdgeDet is
 
-- generics
constant cClkFrequency : natural := 25E6;
constant simulationTime : time := 1200 ns;
 
-- component ports
signal Clk : std_ulogic := cInactivated;
signal nResetAsync : std_ulogic := cnInactivated;
signal EdgeDetected, ClearEdgeDetected, iLine : std_ulogic;
signal EdgeDetected2, EdgeDetected3 : std_ulogic;
signal EdgeDetected4, EdgeDetected5 : std_ulogic;
signal EdgeDetected6 : std_ulogic;
 
begin -- architecture Bhv
 
-- component instantiation
DUT : entity work.EdgeDetector(Rtl)
port map (
iLine => iLine,
inResetAsync => nResetAsync,
iClk => Clk,
iClearEdgeDetected => ClearEdgeDetected,
oEdgeDetected => EdgeDetected);
 
DUT2 : entity work.EdgeDetector(Rtl)
generic map (
gEdgeDetection => cDetectFallingEdge)
port map (
iLine => iLine,
inResetAsync => nResetAsync,
iClk => Clk,
iClearEdgeDetected => ClearEdgeDetected,
oEdgeDetected => EdgeDetected2);
 
DUT3 : entity work.EdgeDetector(Rtl)
generic map (
gEdgeDetection => cDetectAnyEdge)
port map (
iLine => iLine,
inResetAsync => nResetAsync,
iClk => Clk,
iClearEdgeDetected => ClearEdgeDetected,
oEdgeDetected => EdgeDetected3);
DUT4 : entity work.EdgeDetector(Rtl)
generic map (gOutputRegistered => false)
port map (
iLine => iLine,
inResetAsync => nResetAsync,
iClk => Clk,
iClearEdgeDetected => ClearEdgeDetected,
oEdgeDetected => EdgeDetected4);
 
DUT5 : entity work.EdgeDetector(Rtl)
generic map (
gEdgeDetection => cDetectFallingEdge,
gOutputRegistered => false)
port map (
iLine => iLine,
inResetAsync => nResetAsync,
iClk => Clk,
iClearEdgeDetected => ClearEdgeDetected,
oEdgeDetected => EdgeDetected5);
 
DUT6 : entity work.EdgeDetector(Rtl)
generic map (
gEdgeDetection => cDetectAnyEdge,
gOutputRegistered => false)
port map (
iLine => iLine,
inResetAsync => nResetAsync,
iClk => Clk,
iClearEdgeDetected => ClearEdgeDetected,
oEdgeDetected => EdgeDetected6);
 
Clk <= not Clk after (1 sec / cClkFrequency) / 2;
 
nResetAsync <= cnInactivated after 0 ns,
cnActivated after 100 ns,
cnInactivated after 200 ns;
 
 
TestProcess : process is
begin
iLine <= '0' after 0 ns, '1' after 301 ns, '0' after 390 ns,
'1' after 550 ns, '0' after 600 ns, '1' after 690 ns,
'0' after 1000 ns;
ClearEdgeDetected <= '0' after 0 ns, '1' after 430 ns, '0' after 470 ns, '1'
after 590 ns, '0' after 630 ns, '1' after 810 ns,
'0' after 830 ns;
wait;
end process TestProcess;
 
-- Simulation is finished after predefined time.
SimulationFinished : process
begin
wait for simulationTime;
assert false
report "This is not a failure: Simulation finished !!!"
severity failure;
end process SimulationFinished;
end architecture Bhv;
 
sdhc-sc-core/trunk/src/grpStrobesClocks/unitEdgeDetector/src/tbEdgeDetection-Bhv-ea.vhdl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: sdhc-sc-core/trunk/src/grpStrobesClocks/unitEdgeDetector/src/EdgeDetector-Rtl-a.vhdl =================================================================== --- sdhc-sc-core/trunk/src/grpStrobesClocks/unitEdgeDetector/src/EdgeDetector-Rtl-a.vhdl (nonexistent) +++ sdhc-sc-core/trunk/src/grpStrobesClocks/unitEdgeDetector/src/EdgeDetector-Rtl-a.vhdl (revision 118) @@ -0,0 +1,69 @@ +------------------------------------------------------------------------------- +-- Title : - +-- Project : General IP +------------------------------------------------------------------------------- +-- $Id: EdgeDetector-Rtl-a.vhd,v 1.1 2004/05/09 19:32:20 fseebach Exp $ +------------------------------------------------------------------------------- +-- Author : Copyright 2004: Markus Pfaff, Friedrich Seebacher +-- Standard : Using VHDL'93 +-- Simulation : Model Technology Modelsim +-- Synthesis : Exemplar Leonardo +------------------------------------------------------------------------------- +-- Description: +-- Detects an edge on the input signal. The activation is configured by the +-- generic parameter gEdgeDetection. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.global.all; + + +architecture Rtl of EdgeDetector is + signal nQ, detection, Q : std_ulogic; +begin -- Rtl + + FF1 : process (iClk, inResetAsync) is + begin -- process FF1 + if inResetAsync = cnActivated then + nQ <= cnInactivated; + elsif iClk'event and iClk = cActivated then -- rising clock edge + nQ <= not iLine; + end if; + end process FF1; + + Gen : if gOutputRegistered = true generate -- only generate 2nd FF, if + -- condition is true + FF2 : process (iClk, iClearEdgeDetected, inResetAsync) is + begin -- process FF2 + if inResetAsync = cnActivated then + Q <= cInactivated; + elsif iClk'event and iClk = cActivated then -- rising clock edge + if iClearEdgeDetected = cActivated then + Q <= cInactivated; + elsif detection = cActivated then + Q <= cActivated; + end if; + end if; + end process FF2; + + oEdgeDetected <= Q; + end generate; + + Gen2 : if gOutputRegistered = false generate + -- else detection is Output + oEdgeDetected <= detection; + end generate; + + Detect : process (nQ, iLine) is + begin + case gEdgeDetection is + when cDetectRisingEdge => detection <= (iLine and nQ); + when cDetectFallingEdge => detection <= (iLine nor nQ); + when cDetectAnyEdge => detection <= (iLine and nQ) or (iLine nor nQ); + when others => null; + end case; + end process Detect; +end Rtl;
sdhc-sc-core/trunk/src/grpStrobesClocks/unitEdgeDetector/src/EdgeDetector-Rtl-a.vhdl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: sdhc-sc-core/trunk/src/grpStrobesClocks/unitEdgeDetector/src/EdgeDetector-e.vhdl =================================================================== --- sdhc-sc-core/trunk/src/grpStrobesClocks/unitEdgeDetector/src/EdgeDetector-e.vhdl (nonexistent) +++ sdhc-sc-core/trunk/src/grpStrobesClocks/unitEdgeDetector/src/EdgeDetector-e.vhdl (revision 118) @@ -0,0 +1,38 @@ +------------------------------------------------------------------------------- +-- Title : - +-- Project : General IP +------------------------------------------------------------------------------- +-- $Id: EdgeDetector-e.vhd,v 1.2 2004/05/09 23:35:16 fseebach Exp $ +------------------------------------------------------------------------------- +-- Author : Copyright 2004: Markus Pfaff, Friedrich Seebacher +-- Standard : Using VHDL'93 +-- Simulation : Model Technology Modelsim +-- Synthesis : Exemplar Leonardo +------------------------------------------------------------------------------- +-- Description: +-- Detects an edge on the input signal. The activation is configured by the +-- generic parameter gEdgeDetection. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.global.all; + +entity EdgeDetector is + + generic ( + -- which edge should be detected + gEdgeDetection : in natural := cDetectRisingEdge; + -- with or without second FF + gOutputRegistered : in boolean := true); + + port ( + iClk : in std_ulogic; -- system clock + inResetAsync : in std_ulogic; -- global asynchronous reset + iLine : in std_ulogic; -- input signal + iClearEdgeDetected : in std_ulogic; -- clear edge detected output + oEdgeDetected : out std_ulogic); -- edge detected output + +end EdgeDetector;
sdhc-sc-core/trunk/src/grpStrobesClocks/unitEdgeDetector/src/EdgeDetector-e.vhdl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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