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Rev 1170 → Rev 1171

/branches/branch_qmem/or1200/rtl/verilog/or1200_ic_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.6 2002/03/29 15:16:55 lampret
// Some of the warnings fixed.
//
103,9 → 106,9
 
// Internal i/f
ic_en,
icimmu_adr_i, icimmu_cycstb_i, icimmu_ci_i,
icpu_sel_i, icpu_tag_i,
icpu_dat_o, icpu_ack_o, icimmu_rty_o, icimmu_err_o, icimmu_tag_o,
icqmem_adr_i, icqmem_cycstb_i, icqmem_ci_i,
icqmem_sel_i, icqmem_tag_i,
icqmem_dat_o, icqmem_ack_o, icqmem_rty_o, icqmem_err_o, icqmem_tag_o,
 
`ifdef OR1200_BIST
// RAM BIST
146,16 → 149,16
// Internal I/F
//
input ic_en;
input [31:0] icimmu_adr_i;
input icimmu_cycstb_i;
input icimmu_ci_i;
input [3:0] icpu_sel_i;
input [3:0] icpu_tag_i;
output [dw-1:0] icpu_dat_o;
output icpu_ack_o;
output icimmu_rty_o;
output icimmu_err_o;
output [3:0] icimmu_tag_o;
input [31:0] icqmem_adr_i;
input icqmem_cycstb_i;
input icqmem_ci_i;
input [3:0] icqmem_sel_i;
input [3:0] icqmem_tag_i;
output [dw-1:0] icqmem_dat_o;
output icqmem_ack_o;
output icqmem_rty_o;
output icqmem_err_o;
output [3:0] icqmem_tag_o;
 
`ifdef OR1200_BIST
//
227,24 → 230,24
//
// Bypases of the IC when IC is disabled
//
assign icbiu_cyc_o = (ic_en) ? icfsm_biu_read : icimmu_cycstb_i;
assign icbiu_stb_o = (ic_en) ? icfsm_biu_read : icimmu_cycstb_i;
assign icbiu_cyc_o = (ic_en) ? icfsm_biu_read : icqmem_cycstb_i;
assign icbiu_stb_o = (ic_en) ? icfsm_biu_read : icqmem_cycstb_i;
assign icbiu_we_o = 1'b0;
assign icbiu_sel_o = (ic_en & icfsm_biu_read) ? 4'b1111 : icpu_sel_i;
assign icbiu_sel_o = (ic_en & icfsm_biu_read) ? 4'b1111 : icqmem_sel_i;
assign icbiu_cab_o = (ic_en) ? icfsm_burst : 1'b0;
assign icimmu_rty_o = ~icpu_ack_o & ~icimmu_err_o;
assign icimmu_tag_o = icimmu_err_o ? `OR1200_ITAG_BE : icpu_tag_i;
assign icqmem_rty_o = ~icqmem_ack_o & ~icqmem_err_o;
assign icqmem_tag_o = icqmem_err_o ? `OR1200_ITAG_BE : icqmem_tag_i;
 
//
// CPU normal and error termination
//
assign icpu_ack_o = ic_en ? (icfsm_first_hit_ack | icfsm_first_miss_ack) : icbiu_ack_i;
assign icimmu_err_o = ic_en ? icfsm_first_miss_err : icbiu_err_i;
assign icqmem_ack_o = ic_en ? (icfsm_first_hit_ack | icfsm_first_miss_ack) : icbiu_ack_i;
assign icqmem_err_o = ic_en ? icfsm_first_miss_err : icbiu_err_i;
 
//
// Select between claddr generated by IC FSM and addr[3:2] generated by LSU
//
assign ic_addr = (icfsm_biu_read) ? saved_addr : icimmu_adr_i;
assign ic_addr = (icfsm_biu_read) ? saved_addr : icqmem_adr_i;
 
//
// Select between input data generated by LSU or by BIU
254,7 → 257,7
//
// Select between data generated by ICRAM or passed by BIU
//
assign icpu_dat_o = icfsm_first_miss_ack | !ic_en ? icbiu_dat_i : from_icram;
assign icqmem_dat_o = icfsm_first_miss_ack | !ic_en ? icbiu_dat_i : from_icram;
 
//
// Tag comparison
273,12 → 276,12
.clk(clk),
.rst(rst),
.ic_en(ic_en),
.icimmu_cycstb_i(icimmu_cycstb_i),
.icimmu_ci_i(icimmu_ci_i),
.icqmem_cycstb_i(icqmem_cycstb_i),
.icqmem_ci_i(icqmem_ci_i),
.tagcomp_miss(tagcomp_miss),
.biudata_valid(icbiu_ack_i),
.biudata_error(icbiu_err_i),
.start_addr(icimmu_adr_i),
.start_addr(icqmem_adr_i),
.saved_addr(saved_addr),
.icram_we(icram_we),
.biu_read(icfsm_biu_read),
/branches/branch_qmem/or1200/rtl/verilog/or1200_defines.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.35 2003/04/24 00:16:07 lampret
// No functional changes. Added defines to disable implementation of multiplier/MAC
//
// Revision 1.34 2003/04/20 22:23:57 lampret
// No functional change. Only added customization for exception vectors.
//
1272,6 → 1275,52
`define OR1200_SB_ENTRIES 4 // 4 or 8
 
 
/////////////////////////////////////////////////
//
// Quick Embedded Memory (QMEM)
//
 
//
// Quick Embedded Memory
//
// Instantiation of dedicated insn/data memory (RAM or ROM).
// Insn fetch has effective throughput 1insn / clock cycle.
// Data load takes two clock cycles / access, data store
// takes 1 clock cycle / access (if there is no insn fetch)).
// Memory instantiation is shared between insn and data,
// meaning if insn fetch are performed, data load/store
// performance will be lower.
//
// Main reason for QMEM is to put some time critical functions
// into this memory and to have predictable and fast access
// to these functions. (soft fpu, context switch, exception
// handlers, stack, etc)
//
// It makes design a bit bigger and slower. QMEM sits behind
// IMMU/DMMU so all addresses are physical (so the MMUs can be
// used with QMEM and QMEM is seen by the CPU just like any other
// memory in the system). IC/DC are sitting behind QMEM so the
// whole design timing might be worse with QMEM implemented.
//
//`define OR1200_QMEM_IMPLEMENTED
 
//
// Base address and mask of QMEM
//
// Base address defines first address of QMEM. Mask defines
// QMEM range in address space. Actual size of QMEM is however
// determined with instantiated RAM/ROM. However bigger
// mask will reserve more address space for QMEM, but also
// make design faster, while more tight mask will take
// less address space but also make design slower. If
// instantiated RAM/ROM is smaller than space reserved with
// the mask, instatiated RAM/ROM will also be shadowed
// at higher addresses in reserved space.
//
`define OR1200_QMEM_ADDR 32'h0080_0000
`define OR1200_QMEM_MASK 32'hfff0_0000 // Max QMEM size 1MB
 
 
/////////////////////////////////////////////////////
//
// VR, UPR and Configuration Registers
/branches/branch_qmem/or1200/rtl/verilog/or1200_freeze.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2002/07/31 02:04:35 lampret
// MAC now follows software convention (signed multiply instead of unsigned).
//
// Revision 1.5 2002/07/14 22:17:17 lampret
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
//
183,7 → 186,7
if (rst)
multicycle_cnt <= #1 3'b0;
else if (multicycle_cnt)
multicycle_cnt <= #1 multicycle_cnt - 'd1;
multicycle_cnt <= #1 multicycle_cnt - 1'd1;
else if (multicycle & !ex_freeze)
multicycle_cnt <= #1 multicycle;
 
/branches/branch_qmem/or1200/rtl/verilog/or1200_spram_1024x32.v
63,6 → 63,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
385,7 → 388,7
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
lpm_ram_dq_component.lpm_hint = "USE_EAB=OFF";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
 
`else
/branches/branch_qmem/or1200/rtl/verilog/or1200_immu_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.12 2003/06/06 02:54:47 lampret
// When OR1200_NO_IMMU and OR1200_NO_IC are not both defined or undefined at the same time, results in a IC bug. Fixed.
//
// Revision 1.11 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
122,8 → 125,8
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
`endif
 
// IC i/f
icimmu_rty_i, icimmu_err_i, icimmu_tag_i, icimmu_adr_o, icimmu_cycstb_o, icimmu_ci_o
// QMEM i/f
qmemimmu_rty_i, qmemimmu_err_i, qmemimmu_tag_i, qmemimmu_adr_o, qmemimmu_cycstb_o, qmemimmu_ci_o
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
175,12 → 178,12
//
// IC I/F
//
input icimmu_rty_i;
input icimmu_err_i;
input [3:0] icimmu_tag_i;
output [aw-1:0] icimmu_adr_o;
output icimmu_cycstb_o;
output icimmu_ci_o;
input qmemimmu_rty_i;
input qmemimmu_err_i;
input [3:0] qmemimmu_tag_i;
output [aw-1:0] qmemimmu_adr_o;
output qmemimmu_cycstb_o;
output qmemimmu_ci_o;
 
//
// Internal wires and regs
254,12 → 257,12
// Put all outputs in inactive state
//
assign spr_dat_o = 32'h00000000;
assign icimmu_adr_o = icpu_adr_i;
assign icpu_tag_o = icimmu_tag_i;
assign icimmu_cycstb_o = icpu_cycstb_i & ~page_cross;
assign icpu_rty_o = icimmu_rty_i;
assign icpu_err_o = icimmu_err_i;
assign icimmu_ci_o = `OR1200_IMMU_CI;
assign qmemimmu_adr_o = icpu_adr_i;
assign icpu_tag_o = qmemimmu_tag_i;
assign qmemimmu_cycstb_o = icpu_cycstb_i & ~page_cross;
assign icpu_rty_o = qmemimmu_rty_i;
assign icpu_err_o = qmemimmu_err_i;
assign qmemimmu_ci_o = `OR1200_IMMU_CI;
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
`endif
301,18 → 304,18
// OR1200_DTAG_TE - TLB miss Exception
// OR1200_DTAG_PE - Page fault Exception
//
assign icpu_tag_o = miss ? `OR1200_DTAG_TE : fault ? `OR1200_DTAG_PE : icimmu_tag_i;
assign icpu_tag_o = miss ? `OR1200_DTAG_TE : fault ? `OR1200_DTAG_PE : qmemimmu_tag_i;
 
//
// icpu_rty_o
//
// assign icpu_rty_o = !icpu_err_o & icimmu_rty_i;
assign icpu_rty_o = icimmu_rty_i | itlb_spr_access & immu_en;
// assign icpu_rty_o = !icpu_err_o & qmemimmu_rty_i;
assign icpu_rty_o = qmemimmu_rty_i | itlb_spr_access & immu_en;
 
//
// icpu_err_o
//
assign icpu_err_o = miss | fault | icimmu_err_i;
assign icpu_err_o = miss | fault | qmemimmu_err_i;
 
//
// Assert itlb_en_r after one clock cycle and when there is no
333,8 → 336,8
// Cut transfer if something goes wrong with translation. If IC is disabled,
// use delayed signals.
//
// assign icimmu_cycstb_o = (!ic_en & immu_en) ? ~(miss | fault) & icpu_cycstb_i & ~page_cross : (miss | fault) ? 1'b0 : icpu_cycstb_i & ~page_cross; // DL
assign icimmu_cycstb_o = immu_en ? ~(miss | fault) & icpu_cycstb_i & ~page_cross & itlb_done : icpu_cycstb_i & ~page_cross;
// assign qmemimmu_cycstb_o = (!ic_en & immu_en) ? ~(miss | fault) & icpu_cycstb_i & ~page_cross : (miss | fault) ? 1'b0 : icpu_cycstb_i & ~page_cross; // DL
assign qmemimmu_cycstb_o = immu_en ? ~(miss | fault) & icpu_cycstb_i & ~page_cross & itlb_done : icpu_cycstb_i & ~page_cross;
 
//
// Cache Inhibit
341,10 → 344,10
//
// Cache inhibit is not really needed for instruction memory subsystem.
// If we would do it, we would do it like this.
// assign icimmu_ci_o = immu_en ? itlb_done & itlb_ci : `OR1200_IMMU_CI;
// assign qmemimmu_ci_o = immu_en ? itlb_done & itlb_ci : `OR1200_IMMU_CI;
// However this causes a async combinational loop so we stick to
// no cache inhibit.
assign icimmu_ci_o = `OR1200_IMMU_CI;
assign qmemimmu_ci_o = `OR1200_IMMU_CI;
 
 
//
351,7 → 354,7
// Physical address is either translated virtual address or
// simply equal when IMMU is disabled
//
assign icimmu_adr_o = itlb_done ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:0]} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:0]}; // DL: immu_en
assign qmemimmu_adr_o = itlb_done ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:0]} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:0]}; // DL: immu_en
 
//
// Output to SPRS unit
/branches/branch_qmem/or1200/rtl/verilog/or1200_dc_fsm.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7 2002/03/29 15:16:55 lampret
// Some of the warnings fixed.
//
// Revision 1.6 2002/03/28 19:10:40 lampret
// Optimized cache controller FSM.
//
106,7 → 109,7
clk, rst,
 
// Internal i/f to top level DC
dc_en, dcdmmu_cycstb_i, dcdmmu_ci_i, dcpu_we_i, dcpu_sel_i,
dc_en, dcqmem_cycstb_i, dcqmem_ci_i, dcqmem_we_i, dcqmem_sel_i,
tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
dcram_we, biu_read, biu_write, first_hit_ack, first_miss_ack, first_miss_err,
burst, tag_we, dc_addr
118,10 → 121,10
input clk;
input rst;
input dc_en;
input dcdmmu_cycstb_i;
input dcdmmu_ci_i;
input dcpu_we_i;
input [3:0] dcpu_sel_i;
input dcqmem_cycstb_i;
input dcqmem_ci_i;
input dcqmem_we_i;
input [3:0] dcqmem_sel_i;
input tagcomp_miss;
input biudata_valid;
input biudata_error;
152,7 → 155,7
//
// Generate of DCRAM write enables
//
assign dcram_we = {4{load & biudata_valid & !cache_inhibit}} | {4{first_store_hit_ack}} & dcpu_sel_i;
assign dcram_we = {4{load & biudata_valid & !cache_inhibit}} | {4{first_store_hit_ack}} & dcqmem_sel_i;
assign tag_we = biu_read & biudata_valid & !cache_inhibit;
 
//
170,8 → 173,8
// Assert for cache miss first word stored/loaded OK
// Assert for cache miss first word stored/loaded with an error
//
assign first_hit_ack = (state == `OR1200_DCFSM_CLOAD) & !tagcomp_miss & !cache_inhibit & !dcdmmu_ci_i | first_store_hit_ack;
assign first_store_hit_ack = (state == `OR1200_DCFSM_CSTORE) & !tagcomp_miss & biudata_valid & !cache_inhibit & !dcdmmu_ci_i;
assign first_hit_ack = (state == `OR1200_DCFSM_CLOAD) & !tagcomp_miss & !cache_inhibit & !dcqmem_ci_i | first_store_hit_ack;
assign first_store_hit_ack = (state == `OR1200_DCFSM_CSTORE) & !tagcomp_miss & biudata_valid & !cache_inhibit & !dcqmem_ci_i;
assign first_miss_ack = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_valid;
assign first_miss_err = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_error;
 
201,7 → 204,7
else
case (state) // synopsys parallel_case
`OR1200_DCFSM_IDLE :
if (dc_en & dcdmmu_cycstb_i & dcpu_we_i) begin // store
if (dc_en & dcqmem_cycstb_i & dcqmem_we_i) begin // store
state <= #1 `OR1200_DCFSM_CSTORE;
saved_addr_r <= #1 start_addr;
hitmiss_eval <= #1 1'b1;
209,7 → 212,7
load <= #1 1'b0;
cache_inhibit <= #1 1'b0;
end
else if (dc_en & dcdmmu_cycstb_i) begin // load
else if (dc_en & dcqmem_cycstb_i) begin // load
state <= #1 `OR1200_DCFSM_CLOAD;
saved_addr_r <= #1 start_addr;
hitmiss_eval <= #1 1'b1;
224,13 → 227,13
cache_inhibit <= #1 1'b0;
end
`OR1200_DCFSM_CLOAD: begin // load
if (dcdmmu_cycstb_i & dcdmmu_ci_i)
if (dcqmem_cycstb_i & dcqmem_ci_i)
cache_inhibit <= #1 1'b1;
if (hitmiss_eval)
saved_addr_r[31:13] <= #1 start_addr[31:13];
if ((hitmiss_eval & !dcdmmu_cycstb_i) || // load aborted (usually caused by DMMU)
if ((hitmiss_eval & !dcqmem_cycstb_i) || // load aborted (usually caused by DMMU)
(biudata_error) || // load terminated with an error
((cache_inhibit | dcdmmu_ci_i) & biudata_valid)) begin // load from cache-inhibited area
((cache_inhibit | dcqmem_ci_i) & biudata_valid)) begin // load from cache-inhibited area
state <= #1 `OR1200_DCFSM_IDLE;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
238,12 → 241,12
end
else if (tagcomp_miss & biudata_valid) begin // load missed, finish current external load and refill
state <= #1 `OR1200_DCFSM_LREFILL3;
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
hitmiss_eval <= #1 1'b0;
cnt <= #1 `OR1200_DCLS-2;
cache_inhibit <= #1 1'b0;
end
else if (!tagcomp_miss & !dcdmmu_ci_i) begin // load hit, finish immediately
else if (!tagcomp_miss & !dcqmem_ci_i) begin // load hit, finish immediately
state <= #1 `OR1200_DCFSM_IDLE;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
254,8 → 257,8
end
`OR1200_DCFSM_LREFILL3 : begin
if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
cnt <= #1 cnt - 'd1;
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;
cnt <= #1 cnt - 1'd1;
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
end
else if (biudata_valid) begin // last load of line refill
state <= #1 `OR1200_DCFSM_IDLE;
263,13 → 266,13
end
end
`OR1200_DCFSM_CSTORE: begin // store
if (dcdmmu_cycstb_i & dcdmmu_ci_i)
if (dcqmem_cycstb_i & dcqmem_ci_i)
cache_inhibit <= #1 1'b1;
if (hitmiss_eval)
saved_addr_r[31:13] <= #1 start_addr[31:13];
if ((hitmiss_eval & !dcdmmu_cycstb_i) || // store aborted (usually caused by DMMU)
if ((hitmiss_eval & !dcqmem_cycstb_i) || // store aborted (usually caused by DMMU)
(biudata_error) || // store terminated with an error
((cache_inhibit | dcdmmu_ci_i) & biudata_valid)) begin // store to cache-inhibited area
((cache_inhibit | dcqmem_ci_i) & biudata_valid)) begin // store to cache-inhibited area
state <= #1 `OR1200_DCFSM_IDLE;
hitmiss_eval <= #1 1'b0;
store <= #1 1'b0;
297,8 → 300,8
`ifdef OR1200_DC_STORE_REFILL
`OR1200_DCFSM_SREFILL4 : begin
if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
cnt <= #1 cnt - 'd1;
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;
cnt <= #1 cnt - 1'd1;
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
end
else if (biudata_valid) begin // last load of line refill
state <= #1 `OR1200_DCFSM_IDLE;
/branches/branch_qmem/or1200/rtl/verilog/or1200_dpram_32x32.v
62,6 → 62,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.6 2002/03/28 19:25:42 lampret
// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.
//
402,7 → 405,7
 
`else
 
`ifdef OR1200_ALTERA_LPM
`ifdef OR1200_ALTERA_LPM_XXX
 
//
// Instantiation of FPGA memory:
/branches/branch_qmem/or1200/rtl/verilog/or1200_dc_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.5 2002/08/18 19:54:47 lampret
// Added store buffer.
//
100,9 → 103,9
 
// Internal i/f
dc_en,
dcdmmu_adr_i, dcdmmu_cycstb_i, dcdmmu_ci_i,
dcpu_we_i, dcpu_sel_i, dcpu_tag_i, dcpu_dat_i,
dcpu_dat_o, dcpu_ack_o, dcpu_rty_o, dcdmmu_err_o, dcdmmu_tag_o,
dcqmem_adr_i, dcqmem_cycstb_i, dcqmem_ci_i,
dcqmem_we_i, dcqmem_sel_i, dcqmem_tag_i, dcqmem_dat_i,
dcqmem_dat_o, dcqmem_ack_o, dcqmem_rty_o, dcqmem_err_o, dcqmem_tag_o,
 
`ifdef OR1200_BIST
// RAM BIST
143,18 → 146,18
// Internal I/F
//
input dc_en;
input [31:0] dcdmmu_adr_i;
input dcdmmu_cycstb_i;
input dcdmmu_ci_i;
input dcpu_we_i;
input [3:0] dcpu_sel_i;
input [3:0] dcpu_tag_i;
input [dw-1:0] dcpu_dat_i;
output [dw-1:0] dcpu_dat_o;
output dcpu_ack_o;
output dcpu_rty_o;
output dcdmmu_err_o;
output [3:0] dcdmmu_tag_o;
input [31:0] dcqmem_adr_i;
input dcqmem_cycstb_i;
input dcqmem_ci_i;
input dcqmem_we_i;
input [3:0] dcqmem_sel_i;
input [3:0] dcqmem_tag_i;
input [dw-1:0] dcqmem_dat_i;
output [dw-1:0] dcqmem_dat_o;
output dcqmem_ack_o;
output dcqmem_rty_o;
output dcqmem_err_o;
output [3:0] dcqmem_tag_o;
 
`ifdef OR1200_BIST
//
222,39 → 225,39
// Data to BIU is from DCRAM when DC is enabled or from LSU when
// DC is disabled
//
assign dcsb_dat_o = dcpu_dat_i;
assign dcsb_dat_o = dcqmem_dat_i;
 
//
// Bypases of the DC when DC is disabled
//
assign dcsb_cyc_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcdmmu_cycstb_i;
assign dcsb_stb_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcdmmu_cycstb_i;
assign dcsb_we_o = (dc_en) ? dcfsm_biu_write : dcpu_we_i;
assign dcsb_sel_o = (dc_en & dcfsm_biu_read & !dcfsm_biu_write & !dcdmmu_ci_i) ? 4'b1111 : dcpu_sel_i;
assign dcsb_cyc_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcqmem_cycstb_i;
assign dcsb_stb_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcqmem_cycstb_i;
assign dcsb_we_o = (dc_en) ? dcfsm_biu_write : dcqmem_we_i;
assign dcsb_sel_o = (dc_en & dcfsm_biu_read & !dcfsm_biu_write & !dcqmem_ci_i) ? 4'b1111 : dcqmem_sel_i;
assign dcsb_cab_o = (dc_en) ? dcfsm_burst : 1'b0;
assign dcpu_rty_o = ~dcpu_ack_o;
assign dcdmmu_tag_o = dcdmmu_err_o ? `OR1200_DTAG_BE : dcpu_tag_i;
assign dcqmem_rty_o = ~dcqmem_ack_o;
assign dcqmem_tag_o = dcqmem_err_o ? `OR1200_DTAG_BE : dcqmem_tag_i;
 
//
// DC/LSU normal and error termination
//
assign dcpu_ack_o = dc_en ? dcfsm_first_hit_ack | dcfsm_first_miss_ack : dcsb_ack_i;
assign dcdmmu_err_o = dc_en ? dcfsm_first_miss_err : dcsb_err_i;
assign dcqmem_ack_o = dc_en ? dcfsm_first_hit_ack | dcfsm_first_miss_ack : dcsb_ack_i;
assign dcqmem_err_o = dc_en ? dcfsm_first_miss_err : dcsb_err_i;
 
//
// Select between claddr generated by DC FSM and addr[3:2] generated by LSU
//
//assign dc_addr = (dcfsm_biu_read | dcfsm_biu_write) ? saved_addr : dcdmmu_adr_i;
//assign dc_addr = (dcfsm_biu_read | dcfsm_biu_write) ? saved_addr : dcqmem_adr_i;
 
//
// Select between input data generated by LSU or by BIU
//
assign to_dcram = (dcfsm_biu_read) ? dcsb_dat_i : dcpu_dat_i;
assign to_dcram = (dcfsm_biu_read) ? dcsb_dat_i : dcqmem_dat_i;
 
//
// Select between data generated by DCRAM or passed by BIU
//
assign dcpu_dat_o = dcfsm_first_miss_ack | !dc_en ? dcsb_dat_i : from_dcram;
assign dcqmem_dat_o = dcfsm_first_miss_ack | !dc_en ? dcsb_dat_i : from_dcram;
 
//
// Tag comparison
273,14 → 276,14
.clk(clk),
.rst(rst),
.dc_en(dc_en),
.dcdmmu_cycstb_i(dcdmmu_cycstb_i),
.dcdmmu_ci_i(dcdmmu_ci_i),
.dcpu_we_i(dcpu_we_i),
.dcpu_sel_i(dcpu_sel_i),
.dcqmem_cycstb_i(dcqmem_cycstb_i),
.dcqmem_ci_i(dcqmem_ci_i),
.dcqmem_we_i(dcqmem_we_i),
.dcqmem_sel_i(dcqmem_sel_i),
.tagcomp_miss(tagcomp_miss),
.biudata_valid(dcsb_ack_i),
.biudata_error(dcsb_err_i),
.start_addr(dcdmmu_adr_i),
.start_addr(dcqmem_adr_i),
.saved_addr(saved_addr),
.dcram_we(dcram_we),
.biu_read(dcfsm_biu_read),
/branches/branch_qmem/or1200/rtl/verilog/or1200_spram_256x21.v
63,6 → 63,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
314,7 → 317,7
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
lpm_ram_dq_component.lpm_hint = "USE_EAB=OFF";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
 
`else
/branches/branch_qmem/or1200/rtl/verilog/or1200_dmmu_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.6 2002/03/29 15:16:55 lampret
// Some of the warnings fixed.
//
108,7 → 111,7
`endif
 
// DC i/f
dcdmmu_err_i, dcdmmu_tag_i, dcdmmu_adr_o, dcdmmu_cycstb_o, dcdmmu_ci_o
qmemdmmu_err_i, qmemdmmu_tag_i, qmemdmmu_adr_o, qmemdmmu_cycstb_o, qmemdmmu_ci_o
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
159,11 → 162,11
//
// DC I/F
//
input dcdmmu_err_i;
input [3:0] dcdmmu_tag_i;
output [aw-1:0] dcdmmu_adr_o;
output dcdmmu_cycstb_o;
output dcdmmu_ci_o;
input qmemdmmu_err_i;
input [3:0] qmemdmmu_tag_i;
output [aw-1:0] qmemdmmu_adr_o;
output qmemdmmu_cycstb_o;
output qmemdmmu_ci_o;
 
//
// Internal wires and regs
205,11 → 208,11
// Put all outputs in inactive state
//
assign spr_dat_o = 32'h00000000;
assign dcdmmu_adr_o = dcpu_adr_i;
assign dcpu_tag_o = dcdmmu_tag_i;
assign dcdmmu_cycstb_o = dcpu_cycstb_i;
assign dcpu_err_o = dcdmmu_err_i;
assign dcdmmu_ci_o = `OR1200_DMMU_CI;
assign qmemdmmu_adr_o = dcpu_adr_i;
assign dcpu_tag_o = qmemdmmu_tag_i;
assign qmemdmmu_cycstb_o = dcpu_cycstb_i;
assign dcpu_err_o = qmemdmmu_err_i;
assign qmemdmmu_ci_o = `OR1200_DMMU_CI;
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
`endif
233,12 → 236,12
// OR1200_DTAG_TE - TLB miss Exception
// OR1200_DTAG_PE - Page fault Exception
//
assign dcpu_tag_o = miss ? `OR1200_DTAG_TE : fault ? `OR1200_DTAG_PE : dcdmmu_tag_i;
assign dcpu_tag_o = miss ? `OR1200_DTAG_TE : fault ? `OR1200_DTAG_PE : qmemdmmu_tag_i;
 
//
// dcpu_err_o
//
assign dcpu_err_o = miss | fault | dcdmmu_err_i;
assign dcpu_err_o = miss | fault | qmemdmmu_err_i;
 
//
// Assert dtlb_done one clock cycle after new address and dtlb_en must be active.
254,13 → 257,13
//
// Cut transfer if something goes wrong with translation. Also delayed signals because of translation delay.
//
assign dcdmmu_cycstb_o = (!dc_en & dmmu_en) ? ~(miss | fault) & dtlb_done & dcpu_cycstb_i : ~(miss | fault) & dcpu_cycstb_i;
//assign dcdmmu_cycstb_o = (dmmu_en) ? ~(miss | fault) & dcpu_cycstb_i : (miss | fault) ? 1'b0 : dcpu_cycstb_i;
assign qmemdmmu_cycstb_o = (!dc_en & dmmu_en) ? ~(miss | fault) & dtlb_done & dcpu_cycstb_i : ~(miss | fault) & dcpu_cycstb_i;
//assign qmemdmmu_cycstb_o = (dmmu_en) ? ~(miss | fault) & dcpu_cycstb_i : (miss | fault) ? 1'b0 : dcpu_cycstb_i;
 
//
// Cache Inhibit
//
assign dcdmmu_ci_o = dmmu_en ? dtlb_done & dtlb_ci : `OR1200_DMMU_CI;
assign qmemdmmu_ci_o = dmmu_en ? dtlb_done & dtlb_ci : `OR1200_DMMU_CI;
 
//
// Register dcpu_adr_i's VPN for use when DMMU is not enabled but PPN is expected to come
276,8 → 279,8
// Physical address is either translated virtual address or
// simply equal when DMMU is disabled
//
// assign dcdmmu_adr_o = dmmu_en ? {dtlb_ppn, dcpu_adr_i[`OR1200_DMMU_PS-1:0]} : {dcpu_vpn_r, dcpu_adr_i[`OR1200_DMMU_PS-1:0]};
assign dcdmmu_adr_o = dmmu_en ? {dtlb_ppn, dcpu_adr_i[`OR1200_DMMU_PS-1:0]} : dcpu_adr_i;
// assign qmemdmmu_adr_o = dmmu_en ? {dtlb_ppn, dcpu_adr_i[`OR1200_DMMU_PS-1:0]} : {dcpu_vpn_r, dcpu_adr_i[`OR1200_DMMU_PS-1:0]};
assign qmemdmmu_adr_o = dmmu_en ? {dtlb_ppn, dcpu_adr_i[`OR1200_DMMU_PS-1:0]} : dcpu_adr_i;
 
//
// Output to SPRS unit
/branches/branch_qmem/or1200/rtl/verilog/or1200_tpram_32x32.v
62,6 → 62,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
255,7 → 258,7
 
`else
 
`ifdef OR1200_ALTERA_LPM
`ifdef OR1200_ALTERA_LPM_XXX
 
//
// Instantiation of FPGA memory:
/branches/branch_qmem/or1200/rtl/verilog/or1200_genpc.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7 2003/04/20 22:23:57 lampret
// No functional change. Only added customization for exception vectors.
//
// Revision 1.6 2002/03/29 15:16:55 lampret
// Some of the warnings fixed.
//
172,7 → 175,7
or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i or except_prefix) begin
casex ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case
{2'b00, `OR1200_BRANCHOP_NOP}: begin
pc = {pcreg + 'd1, 2'b0};
pc = {pcreg + 1'd1, 2'b0};
taken = 1'b0;
end
{2'b00, `OR1200_BRANCHOP_J}: begin
218,12 → 221,12
$display("%t: BRANCHOP_BF: not taken", $time);
// synopsys translate_on
`endif
pc = {pcreg + 'd1, 2'b0};
pc = {pcreg + 1'd1, 2'b0};
taken = 1'b0;
end
{2'b00, `OR1200_BRANCHOP_BNF}:
if (flag) begin
pc = {pcreg + 'd1, 2'b0};
pc = {pcreg + 1'd1, 2'b0};
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("%t: BRANCHOP_BNF: not taken", $time);
/branches/branch_qmem/or1200/rtl/verilog/or1200_ic_fsm.v
6,7 → 6,7
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Data cache state machine ////
//// Insn cache state machine ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8 2003/06/06 02:54:47 lampret
// When OR1200_NO_IMMU and OR1200_NO_IC are not both defined or undefined at the same time, results in a IC bug. Fixed.
//
// Revision 1.7 2002/03/29 15:16:55 lampret
// Some of the warnings fixed.
//
108,7 → 111,7
clk, rst,
 
// Internal i/f to top level IC
ic_en, icimmu_cycstb_i, icimmu_ci_i,
ic_en, icqmem_cycstb_i, icqmem_ci_i,
tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
icram_we, biu_read, first_hit_ack, first_miss_ack, first_miss_err,
burst, tag_we
120,8 → 123,8
input clk;
input rst;
input ic_en;
input icimmu_cycstb_i;
input icimmu_ci_i;
input icqmem_cycstb_i;
input icqmem_ci_i;
input tagcomp_miss;
input biudata_valid;
input biudata_error;
164,7 → 167,7
// Assert for cache miss first word stored/loaded OK
// Assert for cache miss first word stored/loaded with an error
//
assign first_hit_ack = (state == `OR1200_ICFSM_CFETCH) & hitmiss_eval & !tagcomp_miss & !cache_inhibit & !icimmu_ci_i;
assign first_hit_ack = (state == `OR1200_ICFSM_CFETCH) & hitmiss_eval & !tagcomp_miss & !cache_inhibit & !icqmem_ci_i;
assign first_miss_ack = (state == `OR1200_ICFSM_CFETCH) & biudata_valid;
assign first_miss_err = (state == `OR1200_ICFSM_CFETCH) & biudata_error;
 
189,7 → 192,7
else
case (state) // synopsys parallel_case
`OR1200_ICFSM_IDLE :
if (ic_en & icimmu_cycstb_i) begin // fetch
if (ic_en & icqmem_cycstb_i) begin // fetch
state <= #1 `OR1200_ICFSM_CFETCH;
saved_addr_r <= #1 start_addr;
hitmiss_eval <= #1 1'b1;
202,12 → 205,12
cache_inhibit <= #1 1'b0;
end
`OR1200_ICFSM_CFETCH: begin // fetch
if (icimmu_cycstb_i & icimmu_ci_i)
if (icqmem_cycstb_i & icqmem_ci_i)
cache_inhibit <= #1 1'b1;
if (hitmiss_eval)
saved_addr_r[31:13] <= #1 start_addr[31:13];
if ((!ic_en) ||
(hitmiss_eval & !icimmu_cycstb_i) || // fetch aborted (usually caused by IMMU)
(hitmiss_eval & !icqmem_cycstb_i) || // fetch aborted (usually caused by IMMU)
(biudata_error) || // fetch terminated with an error
(cache_inhibit & biudata_valid)) begin // fetch from cache-inhibited page
state <= #1 `OR1200_ICFSM_IDLE;
217,16 → 220,16
end
else if (tagcomp_miss & biudata_valid) begin // fetch missed, finish current external fetch and refill
state <= #1 `OR1200_ICFSM_LREFILL3;
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
hitmiss_eval <= #1 1'b0;
cnt <= #1 `OR1200_ICLS-2;
cache_inhibit <= #1 1'b0;
end
else if (!tagcomp_miss & !icimmu_ci_i) begin // fetch hit, finish immediately
else if (!tagcomp_miss & !icqmem_ci_i) begin // fetch hit, finish immediately
saved_addr_r <= #1 start_addr;
cache_inhibit <= #1 1'b0;
end
else if (!icimmu_cycstb_i) begin // fetch aborted (usually caused by exception)
else if (!icqmem_cycstb_i) begin // fetch aborted (usually caused by exception)
state <= #1 `OR1200_ICFSM_IDLE;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
237,8 → 240,8
end
`OR1200_ICFSM_LREFILL3 : begin
if (biudata_valid && (|cnt)) begin // refill ack, more fetchs to come
cnt <= #1 cnt - 'd1;
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;
cnt <= #1 cnt - 1'd1;
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
end
else if (biudata_valid) begin // last fetch of line refill
state <= #1 `OR1200_ICFSM_IDLE;
/branches/branch_qmem/or1200/rtl/verilog/or1200_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.10 2002/12/08 08:57:56 lampret
// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
//
// Revision 1.9 2002/10/17 20:04:41 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
311,13 → 314,13
wire [31:0] spr_dat_dmmu;
 
//
// DMMU and DC
// DMMU and QMEM
//
wire dcdmmu_err_dc;
wire [3:0] dcdmmu_tag_dc;
wire [aw-1:0] dcdmmu_adr_dmmu;
wire dcdmmu_cycstb_dmmu;
wire dcdmmu_ci_dmmu;
wire qmemdmmu_err_qmem;
wire [3:0] qmemdmmu_tag_qmem;
wire [aw-1:0] qmemdmmu_adr_dmmu;
wire qmemdmmu_cycstb_dmmu;
wire qmemdmmu_ci_dmmu;
 
//
// CPU and data memory subsystem
328,9 → 331,9
wire [3:0] dcpu_sel_cpu;
wire [3:0] dcpu_tag_cpu;
wire [31:0] dcpu_dat_cpu;
wire [31:0] dcpu_dat_dc;
wire dcpu_ack_dc;
wire dcpu_rty_dc;
wire [31:0] dcpu_dat_qmem;
wire dcpu_ack_qmem;
wire dcpu_rty_qmem;
wire dcpu_err_dmmu;
wire [3:0] dcpu_tag_dmmu;
 
348,23 → 351,50
wire icpu_cycstb_cpu;
wire [3:0] icpu_sel_cpu;
wire [3:0] icpu_tag_cpu;
wire [31:0] icpu_dat_ic;
wire icpu_ack_ic;
wire [31:0] icpu_dat_qmem;
wire icpu_ack_qmem;
wire [31:0] icpu_adr_immu;
wire icpu_err_immu;
wire [3:0] icpu_tag_immu;
 
//
// IMMU and IC
// IMMU and QMEM
//
wire [aw-1:0] icimmu_adr_immu;
wire icimmu_rty_ic;
wire icimmu_err_ic;
wire [3:0] icimmu_tag_ic;
wire icimmu_cycstb_immu;
wire icimmu_ci_immu;
wire [aw-1:0] qmemimmu_adr_immu;
wire qmemimmu_rty_qmem;
wire qmemimmu_err_qmem;
wire [3:0] qmemimmu_tag_qmem;
wire qmemimmu_cycstb_immu;
wire qmemimmu_ci_immu;
 
//
// QMEM and IC
//
wire [aw-1:0] icqmem_adr_qmem;
wire icqmem_rty_ic;
wire icqmem_err_ic;
wire [3:0] icqmem_tag_ic;
wire icqmem_cycstb_qmem;
wire icqmem_ci_qmem;
wire [31:0] icqmem_dat_ic;
wire icqmem_ack_ic;
 
//
// QMEM and DC
//
wire [aw-1:0] dcqmem_adr_qmem;
wire dcqmem_rty_dc;
wire dcqmem_err_dc;
wire [3:0] dcqmem_tag_dc;
wire dcqmem_cycstb_qmem;
wire dcqmem_ci_qmem;
wire [31:0] dcqmem_dat_dc;
wire [31:0] dcqmem_dat_qmem;
wire dcqmem_we_qmem;
wire [3:0] dcqmem_sel_qmem;
wire dcqmem_ack_dc;
 
//
// Connection between CPU and PIC
//
wire [dw-1:0] spr_dat_pic;
411,7 → 441,8
wire scanb_dc_so;
wire scanb_immu_si = scanb_si;
wire scanb_ic_si = scanb_immu_so;
wire scanb_dmmu_si = scanb_ic_so;
wire scanb_qmem_si = scanb_ic_so;
wire scanb_dmmu_si = scanb_qmem_so;
wire scanb_dc_si = scanb_dmmu_so;
assign scanb_so = scanb_dc_so;
`endif
520,7 → 551,7
.scanb_clk(scanb_clk),
`endif
 
// CPU i/f
// CPU and IMMU
.ic_en(ic_en),
.immu_en(immu_en),
.supv(supv),
538,13 → 569,13
.spr_dat_i(spr_dat_cpu),
.spr_dat_o(spr_dat_immu),
 
// IC i/f
.icimmu_rty_i(icimmu_rty_ic),
.icimmu_err_i(icimmu_err_ic),
.icimmu_tag_i(icimmu_tag_ic),
.icimmu_adr_o(icimmu_adr_immu),
.icimmu_cycstb_o(icimmu_cycstb_immu),
.icimmu_ci_o(icimmu_ci_immu)
// QMEM and IMMU
.qmemimmu_rty_i(qmemimmu_rty_qmem),
.qmemimmu_err_i(qmemimmu_err_qmem),
.qmemimmu_tag_i(qmemimmu_tag_qmem),
.qmemimmu_adr_o(qmemimmu_adr_immu),
.qmemimmu_cycstb_o(qmemimmu_cycstb_immu),
.qmemimmu_ci_o(qmemimmu_ci_immu)
);
 
//
563,18 → 594,18
.scanb_clk(scanb_clk),
`endif
 
// IC and CPU/IMMU
// IC and QMEM
.ic_en(ic_en),
.icimmu_adr_i(icimmu_adr_immu),
.icimmu_cycstb_i(icimmu_cycstb_immu),
.icimmu_ci_i(icimmu_ci_immu),
.icpu_sel_i(icpu_sel_cpu),
.icpu_tag_i(icpu_tag_cpu),
.icpu_dat_o(icpu_dat_ic),
.icpu_ack_o(icpu_ack_ic),
.icimmu_rty_o(icimmu_rty_ic),
.icimmu_err_o(icimmu_err_ic),
.icimmu_tag_o(icimmu_tag_ic),
.icqmem_adr_i(icqmem_adr_qmem),
.icqmem_cycstb_i(icqmem_cycstb_qmem),
.icqmem_ci_i(icqmem_ci_qmem),
.icqmem_sel_i(icqmem_sel_qmem),
.icqmem_tag_i(icqmem_tag_qmem),
.icqmem_dat_o(icqmem_dat_ic),
.icqmem_ack_o(icqmem_ack_ic),
.icqmem_rty_o(icqmem_rty_ic),
.icqmem_err_o(icqmem_err_ic),
.icqmem_tag_o(icqmem_tag_ic),
 
// SPR access
.spr_cs(spr_cs[`OR1200_SPR_GROUP_IC]),
601,14 → 632,14
.clk(clk_i),
.rst(rst_i),
 
// Connection IC and IFETCHER inside CPU
// Connection QMEM and IFETCHER inside CPU
.ic_en(ic_en),
.icpu_adr_o(icpu_adr_cpu),
.icpu_cycstb_o(icpu_cycstb_cpu),
.icpu_sel_o(icpu_sel_cpu),
.icpu_tag_o(icpu_tag_cpu),
.icpu_dat_i(icpu_dat_ic),
.icpu_ack_i(icpu_ack_ic),
.icpu_dat_i(icpu_dat_qmem),
.icpu_ack_i(icpu_ack_qmem),
.icpu_rty_i(icpu_rty_immu),
.icpu_adr_i(icpu_adr_immu),
.icpu_err_i(icpu_err_immu),
632,7 → 663,7
// Connection IMMU and CPU internally
.immu_en(immu_en),
 
// Connection DC and CPU
// Connection QMEM and CPU
.dc_en(dc_en),
.dcpu_adr_o(dcpu_adr_cpu),
.dcpu_cycstb_o(dcpu_cycstb_cpu),
640,9 → 671,9
.dcpu_sel_o(dcpu_sel_cpu),
.dcpu_tag_o(dcpu_tag_cpu),
.dcpu_dat_o(dcpu_dat_cpu),
.dcpu_dat_i(dcpu_dat_dc),
.dcpu_ack_i(dcpu_ack_dc),
.dcpu_rty_i(dcpu_rty_dc),
.dcpu_dat_i(dcpu_dat_qmem),
.dcpu_ack_i(dcpu_ack_qmem),
.dcpu_rty_i(dcpu_rty_qmem),
.dcpu_err_i(dcpu_err_dmmu),
.dcpu_tag_i(dcpu_tag_dmmu),
 
702,12 → 733,12
.spr_dat_i(spr_dat_cpu),
.spr_dat_o(spr_dat_dmmu),
 
// DC i/f
.dcdmmu_err_i(dcdmmu_err_dc),
.dcdmmu_tag_i(dcdmmu_tag_dc),
.dcdmmu_adr_o(dcdmmu_adr_dmmu),
.dcdmmu_cycstb_o(dcdmmu_cycstb_dmmu),
.dcdmmu_ci_o(dcdmmu_ci_dmmu)
// QMEM and DMMU
.qmemdmmu_err_i(qmemdmmu_err_qmem),
.qmemdmmu_tag_i(qmemdmmu_tag_qmem),
.qmemdmmu_adr_o(qmemdmmu_adr_dmmu),
.qmemdmmu_cycstb_o(qmemdmmu_cycstb_dmmu),
.qmemdmmu_ci_o(qmemdmmu_ci_dmmu)
);
 
//
726,20 → 757,20
.scanb_clk(scanb_clk),
`endif
 
// DC and CPU/DMMU
// DC and QMEM
.dc_en(dc_en),
.dcdmmu_adr_i(dcdmmu_adr_dmmu),
.dcdmmu_cycstb_i(dcdmmu_cycstb_dmmu),
.dcdmmu_ci_i(dcdmmu_ci_dmmu),
.dcpu_we_i(dcpu_we_cpu),
.dcpu_sel_i(dcpu_sel_cpu),
.dcpu_tag_i(dcpu_tag_cpu),
.dcpu_dat_i(dcpu_dat_cpu),
.dcpu_dat_o(dcpu_dat_dc),
.dcpu_ack_o(dcpu_ack_dc),
.dcpu_rty_o(dcpu_rty_dc),
.dcdmmu_err_o(dcdmmu_err_dc),
.dcdmmu_tag_o(dcdmmu_tag_dc),
.dcqmem_adr_i(dcqmem_adr_qmem),
.dcqmem_cycstb_i(dcqmem_cycstb_qmem),
.dcqmem_ci_i(dcqmem_ci_qmem),
.dcqmem_we_i(dcqmem_we_qmem),
.dcqmem_sel_i(dcqmem_sel_qmem),
.dcqmem_tag_i(dcqmem_tag_qmem),
.dcqmem_dat_i(dcqmem_dat_qmem),
.dcqmem_dat_o(dcqmem_dat_dc),
.dcqmem_ack_o(dcqmem_ack_dc),
.dcqmem_rty_o(dcqmem_rty_dc),
.dcqmem_err_o(dcqmem_err_dc),
.dcqmem_tag_o(dcqmem_tag_dc),
 
// SPR access
.spr_cs(spr_cs[`OR1200_SPR_GROUP_DC]),
760,6 → 791,75
);
 
//
// Instantiation of embedded memory - qmem
//
or1200_qmem_top or1200_qmem_top(
.clk(clk_i),
.rst(rst_i),
 
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_qmem_si),
.scanb_so(scanb_qmem_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
`endif
 
// QMEM and CPU/IMMU
.qmemimmu_adr_i(qmemimmu_adr_immu),
.qmemimmu_cycstb_i(qmemimmu_cycstb_immu),
.qmemimmu_ci_i(qmemimmu_ci_immu),
.qmemicpu_sel_i(icpu_sel_cpu),
.qmemicpu_tag_i(icpu_tag_cpu),
.qmemicpu_dat_o(icpu_dat_qmem),
.qmemicpu_ack_o(icpu_ack_qmem),
.qmemimmu_rty_o(qmemimmu_rty_qmem),
.qmemimmu_err_o(qmemimmu_err_qmem),
.qmemimmu_tag_o(qmemimmu_tag_qmem),
 
// QMEM and IC
.icqmem_adr_o(icqmem_adr_qmem),
.icqmem_cycstb_o(icqmem_cycstb_qmem),
.icqmem_ci_o(icqmem_ci_qmem),
.icqmem_sel_o(icqmem_sel_qmem),
.icqmem_tag_o(icqmem_tag_qmem),
.icqmem_dat_i(icqmem_dat_ic),
.icqmem_ack_i(icqmem_ack_ic),
.icqmem_rty_i(icqmem_rty_ic),
.icqmem_err_i(icqmem_err_ic),
.icqmem_tag_i(icqmem_tag_ic),
 
// QMEM and CPU/DMMU
.qmemdmmu_adr_i(qmemdmmu_adr_dmmu),
.qmemdmmu_cycstb_i(qmemdmmu_cycstb_dmmu),
.qmemdmmu_ci_i(qmemdmmu_ci_dmmu),
.qmemdcpu_we_i(dcpu_we_cpu),
.qmemdcpu_sel_i(dcpu_sel_cpu),
.qmemdcpu_tag_i(dcpu_tag_cpu),
.qmemdcpu_dat_i(dcpu_dat_cpu),
.qmemdcpu_dat_o(dcpu_dat_qmem),
.qmemdcpu_ack_o(dcpu_ack_qmem),
.qmemdcpu_rty_o(dcpu_rty_qmem),
.qmemdmmu_err_o(qmemdmmu_err_qmem),
.qmemdmmu_tag_o(qmemdmmu_tag_qmem),
 
// QMEM and DC
.dcqmem_adr_o(dcqmem_adr_qmem),
.dcqmem_cycstb_o(dcqmem_cycstb_qmem),
.dcqmem_ci_o(dcqmem_ci_qmem),
.dcqmem_we_o(dcqmem_we_qmem),
.dcqmem_sel_o(dcqmem_sel_qmem),
.dcqmem_tag_o(dcqmem_tag_qmem),
.dcqmem_dat_o(dcqmem_dat_qmem),
.dcqmem_dat_i(dcqmem_dat_dc),
.dcqmem_ack_i(dcqmem_ack_dc),
.dcqmem_rty_i(dcqmem_rty_dc),
.dcqmem_err_i(dcqmem_err_dc),
.dcqmem_tag_i(dcqmem_tag_dc)
);
 
//
// Instantiation of Store Buffer
//
or1200_sb or1200_sb(
/branches/branch_qmem/or1200/rtl/verilog/or1200_wb_biu.v
49,6 → 49,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2003/04/07 20:57:46 lampret
// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Fixed order of ifdefs.
//
// Revision 1.5 2002/12/08 08:57:56 lampret
// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
//
250,7 → 253,7
if (rst)
valid_div <= #1 2'b0;
else
valid_div <= #1 valid_div + 'd1;
valid_div <= #1 valid_div + 1'd1;
 
//
// biu_ack_o is one RISC clock cycle long long_ack_o.

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