URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 1178 to Rev 1179
- ↔ Reverse comparison
Rev 1178 → Rev 1179
/trunk/or1200/rtl/verilog/or1200_spram_1024x8.v
63,6 → 63,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2003/04/07 01:19:07 lampret |
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive. |
// |
// Revision 1.2 2002/10/17 20:04:40 lampret |
// Added BIST scan. Special VS RAMs need to be used to implement BIST. |
// |
136,12 → 139,9
// Internal wires and registers |
// |
|
`ifdef OR1200_VIRTUALSILICON_SSP |
`else |
`ifdef OR1200_BIST |
assign scanb_so = scanb_si; |
`endif |
`endif |
|
`ifdef OR1200_ARTISAN_SSP |
|
153,15 → 153,27
`ifdef UNUSED |
art_hssp_1024x8 #(dw, 1<<aw, aw) artisan_ssp( |
`else |
`ifdef OR1200_BIST |
art_hssp_1024x8_bist artisan_ssp( |
`else |
art_hssp_1024x8 artisan_ssp( |
`endif |
.clk(clk), |
.cen(~ce), |
.wen(~we), |
.a(addr), |
.d(di), |
.oen(~oe), |
.q(do) |
`endif |
`ifdef OR1200_BIST |
// RAM BIST |
.scanb_rst(scanb_rst), |
.scanb_si(scanb_si), |
.scanb_so(scanb_so), |
.scanb_en(scanb_en), |
.scanb_clk(scanb_clk), |
`endif |
.CLK(clk), |
.CEN(~ce), |
.WEN(~we), |
.A(addr), |
.D(di), |
.OEN(~oe), |
.Q(do) |
); |
|
`else |
/trunk/or1200/rtl/verilog/or1200_spram_1024x32.v
63,6 → 63,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2003/04/07 01:19:07 lampret |
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive. |
// |
// Revision 1.2 2002/10/17 20:04:40 lampret |
// Added BIST scan. Special VS RAMs need to be used to implement BIST. |
// |
136,12 → 139,9
// Internal wires and registers |
// |
|
`ifdef OR1200_VIRTUALSILICON_SSP |
`else |
`ifdef OR1200_BIST |
assign scanb_so = scanb_si; |
`endif |
`endif |
|
`ifdef OR1200_ARTISAN_SSP |
|
151,17 → 151,29
// Artisan Synchronous Single-Port RAM (ra1sh) |
// |
`ifdef UNUSED |
art_hdsp_1024x32 #(dw, 1<<aw, aw) artisan_ssp( |
art_hssp_1024x32 #(dw, 1<<aw, aw) artisan_ssp( |
`else |
art_hdsp_1024x32 artisan_ssp( |
`ifdef OR1200_BIST |
art_hssp_1024x32_bist artisan_ssp( |
`else |
art_hssp_1024x32 artisan_ssp( |
`endif |
.clk(clk), |
.cen(~ce), |
.wen(~we), |
.a(addr), |
.d(di), |
.oen(~oe), |
.q(do) |
`endif |
`ifdef OR1200_BIST |
// RAM BIST |
.scanb_rst(scanb_rst), |
.scanb_si(scanb_si), |
.scanb_so(scanb_so), |
.scanb_en(scanb_en), |
.scanb_clk(scanb_clk), |
`endif |
.CLK(clk), |
.CEN(~ce), |
.WEN(~we), |
.A(addr), |
.D(di), |
.OEN(~oe), |
.Q(do) |
); |
|
`else |
/trunk/or1200/rtl/verilog/or1200_spram_64x22.v
63,6 → 63,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2003/04/07 01:19:07 lampret |
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive. |
// |
// Revision 1.2 2002/10/17 20:04:41 lampret |
// Added BIST scan. Special VS RAMs need to be used to implement BIST. |
// |
137,12 → 140,9
// |
wire [9:0] unconnected; |
|
`ifdef OR1200_VIRTUALSILICON_SSP |
`else |
`ifdef OR1200_BIST |
assign scanb_so = scanb_si; |
`endif |
`endif |
|
`ifdef OR1200_ARTISAN_SSP |
|
154,15 → 154,27
`ifdef UNUSED |
art_hssp_64x22 #(dw, 1<<aw, aw) artisan_ssp( |
`else |
`ifdef OR1200_BIST |
art_hssp_64x22_bist artisan_ssp( |
`else |
art_hssp_64x22 artisan_ssp( |
`endif |
.clk(clk), |
.cen(~ce), |
.wen(~we), |
.a(addr), |
.d(di), |
.oen(~oe), |
.q(do) |
`endif |
`ifdef OR1200_BIST |
// RAM BIST |
.scanb_rst(scanb_rst), |
.scanb_si(scanb_si), |
.scanb_so(scanb_so), |
.scanb_en(scanb_en), |
.scanb_clk(scanb_clk), |
`endif |
.CLK(clk), |
.CEN(~ce), |
.WEN(~we), |
.A(addr), |
.D(di), |
.OEN(~oe), |
.Q(do) |
); |
|
`else |
/trunk/or1200/rtl/verilog/or1200_spram_64x24.v
63,6 → 63,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2003/04/07 01:19:07 lampret |
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive. |
// |
// Revision 1.2 2002/10/17 20:04:41 lampret |
// Added BIST scan. Special VS RAMs need to be used to implement BIST. |
// |
140,12 → 143,9
// |
wire [7:0] unconnected; |
|
`ifdef OR1200_VIRTUALSILICON_SSP |
`else |
`ifdef OR1200_BIST |
assign scanb_so = scanb_si; |
`endif |
`endif |
|
`ifdef OR1200_ARTISAN_SSP |
|
157,15 → 157,27
`ifdef UNUSED |
art_hssp_64x24 #(dw, 1<<aw, aw) artisan_ssp( |
`else |
`ifdef OR1200_BIST |
art_hssp_64x24_bist artisan_ssp( |
`else |
art_hssp_64x24 artisan_ssp( |
`endif |
.clk(clk), |
.cen(~ce), |
.wen(~we), |
.a(addr), |
.d(di), |
.oen(~oe), |
.q(do) |
`endif |
`ifdef OR1200_BIST |
// RAM BIST |
.scanb_rst(scanb_rst), |
.scanb_si(scanb_si), |
.scanb_so(scanb_so), |
.scanb_en(scanb_en), |
.scanb_clk(scanb_clk), |
`endif |
.CLK(clk), |
.CEN(~ce), |
.WEN(~we), |
.A(addr), |
.D(di), |
.OEN(~oe), |
.Q(do) |
); |
|
`else |
/trunk/or1200/rtl/verilog/or1200_spram_2048x32.v
63,6 → 63,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.4 2003/04/07 01:19:07 lampret |
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive. |
// |
// Revision 1.3 2002/10/28 15:03:50 mohor |
// Signal scanb_sen renamed to scanb_en. |
// |
139,12 → 142,9
// Internal wires and registers |
// |
|
`ifdef OR1200_VIRTUALSILICON_SSP |
`else |
`ifdef OR1200_BIST |
assign scanb_so = scanb_si; |
`endif |
`endif |
|
`ifdef OR1200_ARTISAN_SSP |
|
156,15 → 156,27
`ifdef UNUSED |
art_hdsp_2048x32 #(dw, 1<<aw, aw) artisan_ssp( |
`else |
art_hdsp_2048x32 artisan_ssp( |
`ifdef OR1200_BIST |
art_hssp_2048x32_bist artisan_ssp( |
`else |
art_hssp_2048x32 artisan_ssp( |
`endif |
.clk(clk), |
.cen(~ce), |
.wen(~we), |
.a(addr), |
.d(di), |
.oen(~oe), |
.q(do) |
`endif |
`ifdef OR1200_BIST |
// RAM BIST |
.scanb_rst(scanb_rst), |
.scanb_si(scanb_si), |
.scanb_so(scanb_so), |
.scanb_en(scanb_en), |
.scanb_clk(scanb_clk), |
`endif |
.CLK(clk), |
.CEN(~ce), |
.WEN(~we), |
.A(addr), |
.D(di), |
.OEN(~oe), |
.Q(do) |
); |
|
`else |
/trunk/or1200/rtl/verilog/or1200_spram_256x21.v
63,6 → 63,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2003/04/07 01:19:07 lampret |
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive. |
// |
// Revision 1.2 2002/10/17 20:04:40 lampret |
// Added BIST scan. Special VS RAMs need to be used to implement BIST. |
// |
143,12 → 146,9
// |
wire [10:0] unconnected; |
|
`ifdef OR1200_VIRTUALSILICON_SSP |
`else |
`ifdef OR1200_BIST |
assign scanb_so = scanb_si; |
`endif |
`endif |
|
`ifdef OR1200_ARTISAN_SSP |
|
160,15 → 160,27
`ifdef UNUSED |
art_hssp_256x21 #(dw, 1<<aw, aw) artisan_ssp( |
`else |
`ifdef OR1200_BIST |
art_hssp_256x21_bist artisan_ssp( |
`else |
art_hssp_256x21 artisan_ssp( |
`endif |
.clk(clk), |
.cen(~ce), |
.wen(~we), |
.a(addr), |
.d(di), |
.oen(~oe), |
.q(do) |
`endif |
`ifdef OR1200_BIST |
// RAM BIST |
.scanb_rst(scanb_rst), |
.scanb_si(scanb_si), |
.scanb_so(scanb_so), |
.scanb_en(scanb_en), |
.scanb_clk(scanb_clk), |
`endif |
.CLK(clk), |
.CEN(~ce), |
.WEN(~we), |
.A(addr), |
.D(di), |
.OEN(~oe), |
.Q(do) |
); |
|
`else |
/trunk/or1200/rtl/verilog/or1200_spram_2048x8.v
63,6 → 63,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2003/04/07 01:19:07 lampret |
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive. |
// |
// Revision 1.2 2002/10/17 20:04:40 lampret |
// Added BIST scan. Special VS RAMs need to be used to implement BIST. |
// |
136,12 → 139,9
// Internal wires and registers |
// |
|
`ifdef OR1200_VIRTUALSILICON_SSP |
`else |
`ifdef OR1200_BIST |
assign scanb_so = scanb_si; |
`endif |
`endif |
|
`ifdef OR1200_ARTISAN_SSP |
|
153,15 → 153,27
`ifdef UNUSED |
art_hssp_2048x8 #(dw, 1<<aw, aw) artisan_ssp( |
`else |
`ifdef OR1200_BIST |
art_hssp_2048x8_bist artisan_ssp( |
`else |
art_hssp_2048x8 artisan_ssp( |
`endif |
.clk(clk), |
.cen(~ce), |
.wen(~we), |
.a(addr), |
.d(di), |
.oen(~oe), |
.q(do) |
`endif |
`ifdef OR1200_BIST |
// RAM BIST |
.scanb_rst(scanb_rst), |
.scanb_si(scanb_si), |
.scanb_so(scanb_so), |
.scanb_en(scanb_en), |
.scanb_clk(scanb_clk), |
`endif |
.CLK(clk), |
.CEN(~ce), |
.WEN(~we), |
.A(addr), |
.D(di), |
.OEN(~oe), |
.Q(do) |
); |
|
`else |
/trunk/or1200/rtl/verilog/or1200_spram_64x14.v
63,6 → 63,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2003/04/07 01:19:07 lampret |
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive. |
// |
// Revision 1.2 2002/10/17 20:04:41 lampret |
// Added BIST scan. Special VS RAMs need to be used to implement BIST. |
// |
137,12 → 140,9
// |
wire [1:0] unconnected; |
|
`ifdef OR1200_VIRTUALSILICON_SSP |
`else |
`ifdef OR1200_BIST |
assign scanb_so = scanb_si; |
`endif |
`endif |
|
`ifdef OR1200_ARTISAN_SSP |
|
154,15 → 154,27
`ifdef UNUSED |
art_hssp_64x14 #(dw, 1<<aw, aw) artisan_ssp( |
`else |
`ifdef OR1200_BIST |
art_hssp_64x14_bist artisan_ssp( |
`else |
art_hssp_64x14 artisan_ssp( |
`endif |
.clk(clk), |
.cen(~ce), |
.wen(~we), |
.a(addr), |
.d(di), |
.oen(~oe), |
.q(do) |
`endif |
`ifdef OR1200_BIST |
// RAM BIST |
.scanb_rst(scanb_rst), |
.scanb_si(scanb_si), |
.scanb_so(scanb_so), |
.scanb_en(scanb_en), |
.scanb_clk(scanb_clk), |
`endif |
.CLK(clk), |
.CEN(~ce), |
.WEN(~we), |
.A(addr), |
.D(di), |
.OEN(~oe), |
.Q(do) |
); |
|
`else |
/trunk/or1200/rtl/verilog/or1200_spram_512x20.v
63,6 → 63,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2003/04/07 01:19:07 lampret |
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive. |
// |
// Revision 1.2 2002/10/17 20:04:40 lampret |
// Added BIST scan. Special VS RAMs need to be used to implement BIST. |
// |
143,12 → 146,9
// |
wire [3:0] unconnected; |
|
`ifdef OR1200_VIRTUALSILICON_SSP |
`else |
`ifdef OR1200_BIST |
assign scanb_so = scanb_si; |
`endif |
`endif |
|
`ifdef OR1200_ARTISAN_SSP |
|
160,15 → 160,27
`ifdef UNUSED |
art_hssp_512x20 #(dw, 1<<aw, aw) artisan_ssp( |
`else |
`ifdef OR1200_BIST |
art_hssp_512x20_bist artisan_ssp( |
`else |
art_hssp_512x20 artisan_ssp( |
`endif |
.clk(clk), |
.cen(~ce), |
.wen(~we), |
.a(addr), |
.d(di), |
.oen(~oe), |
.q(do) |
`endif |
`ifdef OR1200_BIST |
// RAM BIST |
.scanb_rst(scanb_rst), |
.scanb_si(scanb_si), |
.scanb_so(scanb_so), |
.scanb_en(scanb_en), |
.scanb_clk(scanb_clk), |
`endif |
.CLK(clk), |
.CEN(~ce), |
.WEN(~we), |
.A(addr), |
.D(di), |
.OEN(~oe), |
.Q(do) |
); |
|
`else |