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URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

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Rev 118 → Rev 119

/sdhc-sc-core/trunk/src/grpSd/pkgSdWb/src/SdWb-p.vhdl
15,7 → 15,7
 
-- data and address types
subtype aData is std_ulogic_vector(31 downto 0);
subtype aAddr is std_ulogic_vector(31 downto 0);
subtype aSdBlockAddr is std_ulogic_vector(31 downto 0);
 
subtype aWbAddr is std_ulogic_vector(6 downto 4);
 
27,6 → 27,7
 
 
-- addresses for register banks in SdWbSlave
 
constant cOperationAddr : aWbAddr := "000";
constant cStartAddrAddr : aWbAddr := "001";
constant cEndAddrAddr : aWbAddr := "010";
33,37 → 34,57
constant cReadDataAddr : aWbAddr := "011";
constant cWriteDataAddr : aWbAddr := "100";
 
-- configuration of the next operation
type aOperationBlock is record
 
StartAddr : aSdBlockAddr; -- start block address for SD card the next operation
EndAddr : aSdBlockAddr; -- last block address
Operation : aOperation; -- operation to execute (Read, write, etc.)
 
end record aOperationBlock;
 
constant cDefaultOperationBlock : aOperationBlock := (
StartAddr => (others => '0'),
EndAddr => (others => '0'),
Operation => (others => '0'));
 
 
-- ports
type aSdWbSlaveToSdController is record
StartAddr : aAddr;
EndAddr : aAddr;
Operation : aOperation;
Valid : std_ulogic;
WriteData : aData;
 
AckOperationToggle : std_ulogic; -- every edge signals that the OperationBlock is valid
OperationBlock : aOperationBlock;
WriteData : aData; -- data to write to the card (32 bit blocks)
 
end record aSdWbSlaveToSdController;
 
type aSdControllerToSdWbSlave is record
Done : std_ulogic;
ReadData : aData;
 
ReqOperationEdge : std_ulogic; -- Request a new OperationBlock
Done : std_ulogic;
ReadData : aData;
 
end record aSdControllerToSdWbSlave;
 
type aSdWbSlaveDataOutput is record
 
Dat : aData;
 
end record aSdWbSlaveDataOutput;
 
type aSdWbSlaveDataInput is record
 
Sel : std_ulogic_vector(0 downto 0);
Adr : aWbAddr;
Dat : aData;
 
end record aSdWbSlaveDataInput;
 
-- default port values
constant cDefaultSdWbSlaveToSdController : aSdWbSlaveToSdController := (
StartAddr => (others => '0'),
EndAddr => (others => '0'),
Operation => (others => '0'),
Valid => '0',
WriteData => (others => '0'));
OperationBlock => cDefaultOperationBlock,
WriteData => (others => '0'),
AckOperationToggle => '0');
 
end package SdWb;
 
/sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/Files.tcl
0,0 → 1,5
set pkgs {Global Global
Wishbone Wishbone
Sd SdWb}
 
set units {Sd SdWbSlave {Rtl}}
/sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/src/SdWbSlave-Rtl-ea.vhdl File deleted
/sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/src/SdWbSlave-Rtl-a.vhdl
0,0 → 1,187
--
-- Title: SdWbSlave
-- File: SdWbSlave-Rtl-ea.vhdl
-- Author: Copyright 2010: Rainer Kastl
-- Standard: VHDL'93
--
-- Description: Wishbone interface for the SD-Core
--
 
architecture Rtl of SdWbSlave is
 
type aWbState is (idle, ClassicRead, ClassicWrite);
type aSdIntState is (idle, newOperation);
 
type aRegs is record
 
WbState : aWbState; -- state of the wb interface
SdIntState : aSdIntState; -- state of the sd controller interface
OperationBlock : aOperationBlock; -- Operation for the SdController
ReqOperation : std_ulogic; -- Register for catching edges on the SdController ReqOperationEdge line
-- Register outputs
oWbDat : aSdWbSlaveDataOutput;
oWbCtrl : aWbSlaveCtrlOutput;
oController : aSdWbSlaveToSdController;
 
end record aRegs;
 
constant cDefaultRegs : aRegs := (
WbState => idle,
SdIntState => idle,
OperationBlock => cDefaultOperationBlock,
ReqOperation => cInactivated,
oWbDat => (Dat => (others => '0')),
oWbCtrl => cDefaultWbSlaveCtrlOutput,
oController => cDefaultSdWbSlaveToSdController);
 
signal R, NxR : aRegs;
 
begin
WbStateReg : process (iClk, iRstSync)
begin
if (iClk'event and iClk = cActivated) then
if (iRstSync = cActivated) then -- sync. reset
R <= cDefaultRegs;
else
R <= NxR;
end if;
end if;
end process WbStateReg ;
 
WbStateAndOutputs : process (iWbCtrl, iWbDat, iController, R)
begin
-- Default Assignments
 
NxR <= R;
NxR.oWbDat.Dat <= (others => 'X');
NxR.oWbCtrl <= cDefaultWbSlaveCtrlOutput;
 
-- Determine next state
case R.WbState is
when idle =>
if iWbCtrl.Cyc = cActivated and iWbCtrl.Stb = cActivated then
case iWbCtrl.Cti is
when cCtiClassicCycle =>
-- switch to ClassicRead or ClassicWrite
case iWbCtrl.We is
when cInactivated =>
NxR.WbState <= ClassicRead;
when cActivated =>
NxR.WbState <= ClassicWrite;
when others =>
report "iWbCtrl.We is invalid" severity warning;
end case;
when others => null;
end case;
end if;
 
when ClassicRead =>
assert (iWbCtrl.Cyc = cActivated) report
"Cyc deactivated mid cyclus" severity warning;
 
NxR.oWbCtrl.Ack <= cActivated;
 
if (iWbDat.Sel = "1") then
case iWbDat.Adr is
when cOperationAddr =>
NxR.oWbDat.Dat <= R.OperationBlock.Operation;
 
when cStartAddrAddr =>
NxR.oWbDat.Dat <= R.OperationBlock.StartAddr;
 
when cEndAddrAddr =>
NxR.oWbDat.Dat <= R.OperationBlock.EndAddr;
 
when cReadDataAddr =>
-- read data from fifo
 
when others =>
report "Read to an invalid address" severity warning;
NxR.oWbCtrl.Err <= cActivated;
NxR.oWbCtrl.Ack <= cInactivated;
end case;
end if;
NxR.WbState <= idle;
 
when ClassicWrite =>
assert (iWbCtrl.Cyc = cActivated) report
"Cyc deactivated mid cyclus" severity warning;
 
-- default state transition and output
 
NxR.oWbCtrl.Ack <= cActivated;
NxR.WbState <= idle;
 
if (iWbDat.Sel = "1") then
case iWbDat.Adr is
when cOperationAddr =>
if (R.SdIntState = idle) then
-- save operation and notify the SdController
 
NxR.OperationBlock.Operation <= iWbDat.Dat;
NxR.SdIntState <= newOperation;
 
else
-- insert waitstates until we can notify the SdController again
 
NxR.oWbCtrl.Ack <= cInactivated;
 
end if;
 
when cStartAddrAddr =>
 
NxR.OperationBlock.StartAddr <= iWbDat.Dat;
 
when cEndAddrAddr =>
 
NxR.OperationBlock.EndAddr <= iWbDat.Dat;
 
when cWriteDataAddr =>
-- put into fifo
 
when others =>
report "Read to an invalid address" severity warning;
end case;
end if;
 
when others => null;
end case;
 
-- send operations to SdController
case R.SdIntState is
when idle =>
-- save edges on the ReqOperationEdge line which would be missed otherwise
 
if (iController.ReqOperationEdge = cActivated) then
 
R.ReqOperation <= cActivated;
end if;
 
when newOperation =>
-- send a new operation, when the controller requested it
if (R.ReqOperation = cActivated or iController.ReqOperationEdge = cActivated) then
 
NxR.oController.OperationBlock <= R.OperationBlock;
NxR.oController.AckOperationToggle <= not R.oController.AckOperationToggle;
 
-- go to idle state, the next request will come only after the SdController received this block
NxR.ReqOperation <= cInactivated;
NxR.SdIntState <= idle;
 
end if;
when others =>
report "Invalid state" severity error;
end case;
 
end process WbStateAndOutputs;
end architecture Rtl;
 
/sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/src/SdWbSlave-e.vhdl
0,0 → 1,33
--
-- Title: SdWbSlave
-- File: SdWbSlave-Rtl-ea.vhdl
-- Author: Copyright 2010: Rainer Kastl
-- Standard: VHDL'93
--
-- Description: Wishbone interface for the SD-Core
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use work.Global.all;
use work.wishbone.all;
use work.SdWb.all;
 
entity SdWbSlave is
port (
iClk : in std_ulogic; -- Clock, rising clock edge
iRstSync : in std_ulogic; -- Reset, active high, synchronous
 
-- wishbone
iWbCtrl : in aWbSlaveCtrlInput; -- All control signals for a wishbone slave
oWbCtrl : out aWbSlaveCtrlOutput; -- All output signals for a wishbone slave
iWbDat : in aSdWbSlaveDataInput;
oWbDat : out aSdWbSlaveDataOutput;
-- To sd controller
iController : in aSdControllerToSdWbSlave;
oController : out aSdWbSlaveToSdController
);
end entity;
 
/sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/sim/SdWbSlave-unattended.tcl
0,0 → 1,3
set script SdWbSlave.tcl
 
do "../../../sim/unattended.tcl"
/sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/sim/SdWbSlave.tcl
0,0 → 1,2
source ../Files.tcl
source ../../../sim/sim.tcl
/sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/sim/Makefile
0,0 → 1,7
include ../../../../Makefile.rules
 
all: SdWbSlave-unattended.sim
 
clean:
rm -rf vsim.wlf work
 

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