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URL https://opencores.org/ocsvn/8051/8051/trunk

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Rev 119 → Rev 120

/trunk/bench/verilog/oc8051_tb.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.10 2003/04/03 19:20:55 simont
// Remove instruction cache and wb_interface
//
// Revision 1.9 2003/04/02 15:08:59 simont
// rename signals
//
109,14 → 112,45
.wbi_adr_o(iadr_o), .wbi_stb_o(istb_o), .wbi_ack_i(iack_i),
.wbi_cyc_o(icyc_o), .wbi_dat_i(idat_i), .wbi_err_i(wbi_err_i),
 
.p0_i(p0_in), .p1_i(p1_in), .p2_i(p2_in), .p3_i(p3_in),
.p0_o(p0_out), .p1_o(p1_out), .p2_o(p2_out), .p3_o(p3_out),
`ifdef OC8051_PORTS
 
.ea_in(ea[0]),
`ifdef OC8051_PORT0
.p0_i(p0_in),
.p0_o(p0_out),
`endif
 
`ifdef OC8051_PORT1
.p1_i(p1_in),
.p1_o(p1_out),
`endif
 
`ifdef OC8051_PORT2
.p2_i(p2_in),
.p2_o(p2_out),
`endif
 
`ifdef OC8051_PORT3
.p3_i(p3_in),
.p3_o(p3_out),
`endif
`endif
 
 
`ifdef OC8051_UART
.rxd_i(rxd), .txd_o(txd),
.t0_i(t0), .t1_i(t1), .t2_i(t2), .t2ex_i(t2ex));
`endif
 
`ifdef OC8051_TC01
.t0_i(t0), .t1_i(t1),
`endif
 
`ifdef OC8051_TC2
.t2_i(t2), .t2ex_i(t2ex),
`endif
 
.ea_in(ea[0]));
 
 
//
// external data ram
//
/trunk/rtl/verilog/oc8051_defines.v
46,6 → 46,20
//
 
//
// oc8051 pherypherals
//
`define OC8051_UART
`define OC8051_TC01
`define OC8051_TC2
`define OC8051_PORTS //ports global enable
`define OC8051_PORT0
`define OC8051_PORT1
`define OC8051_PORT2
`define OC8051_PORT3
 
 
 
//
// oc8051 memory
//
//`define OC8051_CACHE
/trunk/rtl/verilog/oc8051_sp.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2003/01/13 14:14:41 simont
// replace some modules
//
// Revision 1.4 2002/11/05 17:23:54 simont
// add module oc8051_sfr, 256 bytes internal ram
//
60,13 → 63,12
 
 
 
module oc8051_sp (clk, rst, ram_rd_sel, ram_wr_sel, wr_addr, wr, wr_bit, data_in, data_out, sp_out, sp_w);
module oc8051_sp (clk, rst, ram_rd_sel, ram_wr_sel, wr_addr, wr, wr_bit, data_in, sp_out, sp_w);
 
 
input clk, rst, wr, wr_bit;
input [2:0] ram_rd_sel, ram_wr_sel;
input [7:0] data_in, wr_addr;
output [7:0] data_out;
output [7:0] sp_out, sp_w;
 
reg [7:0] sp_out, sp_w;
81,7 → 83,6
 
assign sp_t= write ? data_in : sp;
 
assign data_out = sp;
 
always @(posedge clk or posedge rst)
begin
/trunk/rtl/verilog/oc8051_sfr.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9 2003/04/09 16:24:03 simont
// change wr_sft to 2 bit wire.
//
// Revision 1.8 2003/04/09 15:49:42 simont
// Register oc8051_sfr dato output, add signal wait_data.
//
77,126 → 80,205
`include "oc8051_defines.v"
 
 
module oc8051_sfr (rst, clk,
module oc8051_sfr (rst, clk,
adr0, adr1, dat0,
dat1, dat2,
we, bit_in, wr_bit,
dat1, dat2, bit_in,
we, wr_bit,
bit_out,
wr_sfr, acc, ram_wr_sel, ram_rd_sel, sp, sp_w, bank_sel, desAc, desOv, psw_set, srcAc, cy, rmw,
p0_out, p1_out, p2_out, p3_out, p0_in, p1_in, p2_in, p3_in, rxd, txd, int_ack, intr, int0,
int1, reti, int_src, t0, t1, dptr_hi, dptr_lo, t2, t2ex,
wait_data);
//
// rst (in) reset - pin
// clk (in) clock - pin
// adr0, adr1 (in) address input
// dat0 (out) data output
// dat1 (in) data input
// dat2
// we (in) write enable
// bit_in
// bit_out
// wr_bit
// ram_rd_sel
// ram_wr_sel
// wr_sfr
//////////
//
// acc:
// acc
//////////
//
// sp:
// sp
//////////
//
// psw:
// bank_sel
// desAc
// desOv
// psw_set
// srcAc
// cy
//////////
//
// ports:
// rmw
// px_out
// px_in
//////////
//
// serial interface:
// rxd
// txd
//////////
//
// interrupt interface:
// int_ack
// intr
// int0, int1
// reti
// int_src
//////////
//
// timers/counters:
// t0
// t1
// t2
// t2ex
//
//////////
//
// dptr:
// dptr_hi
// dptr_lo
//
//////////
//
wr_sfr, acc,
ram_wr_sel, ram_rd_sel,
sp, sp_w,
bank_sel,
desAc, desOv,
srcAc, cy,
psw_set, rmw,
 
`ifdef OC8051_PORTS
 
`ifdef OC8051_PORT0
p0_out,
p0_in,
`endif
 
`ifdef OC8051_PORT1
p1_out,
p1_in,
`endif
 
input rst, clk, we, bit_in, desAc, desOv, rmw, rxd, t2, t2ex;
input int_ack, int0, int1, reti, wr_bit, t0, t1;
input [1:0] psw_set, wr_sfr;
input [2:0] ram_rd_sel, ram_wr_sel;
input [7:0] adr0, adr1, dat1, dat2, p0_in, p1_in, p2_in, p3_in;
`ifdef OC8051_PORT2
p2_out,
p2_in,
`endif
 
output bit_out, txd, intr, srcAc, cy, wait_data;
`ifdef OC8051_PORT3
p3_out,
p3_in,
`endif
 
`endif
 
 
`ifdef OC8051_UART
rxd, txd,
`endif
 
int_ack, intr,
int0, int1,
int_src,
reti,
 
`ifdef OC8051_TC01
t0, t1,
`endif
 
`ifdef OC8051_TC2
t2, t2ex,
`endif
 
dptr_hi, dptr_lo,
wait_data);
 
 
input rst, // reset - pin
clk, // clock - pin
we, // write enable
bit_in,
desAc,
desOv,
rmw;
input int_ack,
int0,
int1,
reti,
wr_bit;
input [1:0] psw_set,
wr_sfr;
input [2:0] ram_rd_sel,
ram_wr_sel;
input [7:0] adr0, //address 0 input
adr1, //address 1 input
dat1, //data 1 input (des1)
dat2; //data 2 input (des2)
 
output bit_out,
intr,
srcAc,
cy,
wait_data;
output [1:0] bank_sel;
output [7:0] dat0, p0_out, p1_out, p2_out, p3_out, int_src, dptr_hi, dptr_lo, acc;
output [7:0] sp, sp_w;
output [7:0] dat0, //data output
int_src,
dptr_hi,
dptr_lo,
acc;
output [7:0] sp,
sp_w;
 
// ports
`ifdef OC8051_PORTS
 
reg bit_out, wait_data;
reg [7:0] dat0, adr0_r;
`ifdef OC8051_PORT0
input [7:0] p0_in;
output [7:0] p0_out;
wire [7:0] p0_data;
`endif
 
reg wr_bit_r;
reg [2:0] ram_wr_sel_r;
`ifdef OC8051_PORT1
input [7:0] p1_in;
output [7:0] p1_out;
wire [7:0] p1_data;
`endif
 
//sfr's
wire acc_bit, b_bit, psw_bit, port_bit, uart_bit, int_bit, tc2_bit;
`ifdef OC8051_PORT2
input [7:0] p2_in;
output [7:0] p2_out;
wire [7:0] p2_data;
`endif
 
wire p, int_uart, tf0, tf1, tr0, tr1;
wire rclk, tclk, brate2, tc2_int;
`ifdef OC8051_PORT3
input [7:0] p3_in;
output [7:0] p3_out;
wire [7:0] p3_data;
`endif
 
wire [7:0] b_reg, psw,
//ports
p0_data, p1_data, p2_data, p3_data,
//interrupt control
ie, tcon, ip,
// t/c 2
t2con, tl2, th2, rcap2l, rcap2h,
// t/c 0,1
tmod, tl0, th0, tl1, th1,
`endif
 
 
// serial interface
scon, pcon, sbuf,
// stack
sp_out;
`ifdef OC8051_UART
input rxd;
output txd;
`endif
 
wire pres_ow;
// timer/counter 0,1
`ifdef OC8051_TC01
input t0, t1;
`endif
 
// timer/counter 2
`ifdef OC8051_TC2
input t2, t2ex;
`endif
 
reg bit_out,
wait_data;
reg [7:0] dat0,
adr0_r;
 
reg wr_bit_r;
reg [2:0] ram_wr_sel_r;
 
 
wire p,
uart_int,
tf0,
tf1,
tr0,
tr1,
rclk,
tclk,
brate2,
tc2_int;
 
 
wire [7:0] b_reg,
psw,
 
`ifdef OC8051_TC2
// t/c 2
t2con,
tl2,
th2,
rcap2l,
rcap2h,
`endif
 
`ifdef OC8051_TC01
// t/c 0,1
tmod,
tl0,
th0,
tl1,
th1,
`endif
 
// serial interface
`ifdef OC8051_UART
scon,
pcon,
sbuf,
`endif
 
//interrupt control
ie,
tcon,
ip;
 
 
reg pres_ow;
reg [3:0] prescaler;
 
 
assign cy = psw[7];
assign srcAc = psw [6];
 
205,87 → 287,230
//
// accumulator
// ACC
oc8051_acc oc8051_acc1(.clk(clk), .rst(rst), .bit_in(bit_in), .data_in(dat1),
.data2_in(dat2), .wr(we), .wr_bit(wr_bit_r), .wr_sfr(wr_sfr),
.wr_addr(adr1), .data_out(acc), .p(p));
oc8051_acc oc8051_acc1(.clk(clk),
.rst(rst),
.bit_in(bit_in),
.data_in(dat1),
.data2_in(dat2),
.wr(we),
.wr_bit(wr_bit_r),
.wr_sfr(wr_sfr),
.wr_addr(adr1),
.data_out(acc),
.p(p));
 
 
//
// b register
// B
oc8051_b_register oc8051_b_register (.clk(clk), .rst(rst), .bit_in(bit_in),
.data_in(dat1), .wr(we), .wr_bit(wr_bit_r), .wr_addr(adr1),
.data_out(b_reg));
oc8051_b_register oc8051_b_register (.clk(clk),
.rst(rst),
.bit_in(bit_in),
.data_in(dat1),
.wr(we),
.wr_bit(wr_bit_r),
.wr_addr(adr1),
.data_out(b_reg));
 
//
//stack pointer
// SP
oc8051_sp oc8051_sp1(.clk(clk), .rst(rst), .ram_rd_sel(ram_rd_sel), .ram_wr_sel(ram_wr_sel),
.wr_addr(adr1), .wr(we), .wr_bit(wr_bit_r), .data_in(dat1),
.data_out(sp_out), .sp_out(sp), .sp_w(sp_w));
oc8051_sp oc8051_sp1(.clk(clk),
.rst(rst),
.ram_rd_sel(ram_rd_sel),
.ram_wr_sel(ram_wr_sel),
.wr_addr(adr1),
.wr(we),
.wr_bit(wr_bit_r),
.data_in(dat1),
.sp_out(sp),
.sp_w(sp_w));
 
//
//data pointer
// DPTR, DPH, DPL
oc8051_dptr oc8051_dptr1(.clk(clk), .rst(rst), .addr(adr1), .data_in(dat1),
.data2_in(dat2), .wr(we), .wr_bit(wr_bit_r),
.data_hi(dptr_hi), .data_lo(dptr_lo), .wr_sfr(wr_sfr));
oc8051_dptr oc8051_dptr1(.clk(clk),
.rst(rst),
.addr(adr1),
.data_in(dat1),
.data2_in(dat2),
.wr(we),
.wr_bit(wr_bit_r),
.data_hi(dptr_hi),
.data_lo(dptr_lo),
.wr_sfr(wr_sfr));
 
 
//
//program status word
// PSW
oc8051_psw oc8051_psw1 (.clk(clk), .rst(rst), .wr_addr(adr1), .data_in(dat1),
.wr(we), .wr_bit(wr_bit_r), .data_out(psw), .p(p), .cy_in(bit_in),
.ac_in(desAc), .ov_in(desOv), .set(psw_set), .bank_sel(bank_sel));
oc8051_psw oc8051_psw1 (.clk(clk),
.rst(rst),
.wr_addr(adr1),
.data_in(dat1),
.wr(we),
.wr_bit(wr_bit_r),
.data_out(psw),
.p(p),
.cy_in(bit_in),
.ac_in(desAc),
.ov_in(desOv),
.set(psw_set),
.bank_sel(bank_sel));
 
//
// ports
// P0, P1, P2, P3
oc8051_ports oc8051_ports1(.clk(clk), .rst(rst), .bit_in(bit_in), .data_in(dat1), .wr(we),
.wr_bit(wr_bit_r), .wr_addr(adr1), .rmw(rmw),
.p0_out(p0_out), .p1_out(p1_out), .p2_out(p2_out), .p3_out(p3_out),
.p0_in(p0_in), .p1_in(p1_in), .p2_in(p2_in), .p3_in(p3_in),
.p0_data(p0_data), .p1_data(p1_data), .p2_data(p2_data), .p3_data(p3_data));
`ifdef OC8051_PORTS
oc8051_ports oc8051_ports1(.clk(clk),
.rst(rst),
.bit_in(bit_in),
.data_in(dat1),
.wr(we),
.wr_bit(wr_bit_r),
.wr_addr(adr1),
 
`ifdef OC8051_PORT0
.p0_out(p0_out),
.p0_in(p0_in),
.p0_data(p0_data),
`endif
 
`ifdef OC8051_PORT1
.p1_out(p1_out),
.p1_in(p1_in),
.p1_data(p1_data),
`endif
 
`ifdef OC8051_PORT2
.p2_out(p2_out),
.p2_in(p2_in),
.p2_data(p2_data),
`endif
 
`ifdef OC8051_PORT3
.p3_out(p3_out),
.p3_in(p3_in),
.p3_data(p3_data),
`endif
 
.rmw(rmw));
`endif
 
//
// serial interface
// SCON, SBUF
oc8051_uart oc8051_uatr1 (.clk(clk), .rst(rst), .bit_in(bit_in),
.data_in(dat1), .wr(we), .wr_bit(wr_bit_r), .wr_addr(adr1),
.rxd(rxd), .txd(txd), .intr(uart_int),
.rclk(rclk), .tclk(tclk), .brate2(brate2),
.t1_ow(tf1), .pres_ow(pres_ow),
.scon(scon), .pcon(pcon), .sbuf(sbuf));
`ifdef OC8051_UART
oc8051_uart oc8051_uatr1 (.clk(clk),
.rst(rst),
.bit_in(bit_in),
.data_in(dat1),
.wr(we),
.wr_bit(wr_bit_r),
.wr_addr(adr1),
.rxd(rxd),
.txd(txd),
// interrupt
.intr(uart_int),
// baud rate sources
.brate2(brate2),
.t1_ow(tf1),
.pres_ow(pres_ow),
.rclk(rclk),
.tclk(tclk),
//registers
.scon(scon),
.pcon(pcon),
.sbuf(sbuf));
`else
assign uart_int = 1'b0;
`endif
 
//
// interrupt control
// IP, IE, TCON
oc8051_int oc8051_int1 (.clk(clk), .rst(rst), .wr_addr(adr1), .bit_in(bit_in),
.ack(int_ack), .data_in(dat1),
.wr(we), .wr_bit(wr_bit_r),
.tf0(tf0), .tf1(tf1), .t2_int(tc2_int), .tr0(tr0), .tr1(tr1),
.ie0(int0), .ie1(int1),
.uart_int(uart_int),
.reti(reti), .intr(intr), .int_vec(int_src),
.ie(ie), .tcon(tcon), .ip(ip));
oc8051_int oc8051_int1 (.clk(clk),
.rst(rst),
.wr_addr(adr1),
.bit_in(bit_in),
.ack(int_ack),
.data_in(dat1),
.wr(we),
.wr_bit(wr_bit_r),
.tf0(tf0),
.tf1(tf1),
.t2_int(tc2_int),
.tr0(tr0),
.tr1(tr1),
.ie0(int0),
.ie1(int1),
.uart_int(uart_int),
.reti(reti),
.intr(intr),
.int_vec(int_src),
.ie(ie),
.tcon(tcon),
.ip(ip));
 
 
//
// timer/counter control
// TH0, TH1, TL0, TH1, TMOD
oc8051_tc oc8051_tc1(.clk(clk), .rst(rst), .wr_addr(adr1),
.data_in(dat1), .wr(we), .wr_bit(wr_bit_r), .ie0(int0), .ie1(int1), .tr0(tr0),
.tr1(tr1), .t0(t0), .t1(t1), .tf0(tf0), .tf1(tf1), .pres_ow(pres_ow),
.tmod(tmod), .tl0(tl0), .th0(th0), .tl1(tl1), .th1(th1));
`ifdef OC8051_TC01
oc8051_tc oc8051_tc1(.clk(clk),
.rst(rst),
.wr_addr(adr1),
.data_in(dat1),
.wr(we),
.wr_bit(wr_bit_r),
.ie0(int0),
.ie1(int1),
.tr0(tr0),
.tr1(tr1),
.t0(t0),
.t1(t1),
.tf0(tf0),
.tf1(tf1),
.pres_ow(pres_ow),
.tmod(tmod),
.tl0(tl0),
.th0(th0),
.tl1(tl1),
.th1(th1));
`else
assign tf0 = 1'b0;
assign tf1 = 1'b0;
`endif
 
//
// timer/counter 2
// TH2, TL2, RCAPL2L, RCAPL2H, T2CON
oc8051_tc2 oc8051_tc21(.clk(clk), .rst(rst), .wr_addr(adr1), .data_in(dat1), .wr(we),
.wr_bit(wr_bit_r), .bit_in(bit_in), .t2(t2), .t2ex(t2ex),
.rclk(rclk), .tclk(tclk), .brate2(brate2), .tc2_int(tc2_int), .pres_ow(pres_ow),
.t2con(t2con), .tl2(tl2), .th2(th2), .rcap2l(rcap2l), .rcap2h(rcap2h));
`ifdef OC8051_TC2
oc8051_tc2 oc8051_tc21(.clk(clk),
.rst(rst),
.wr_addr(adr1),
.data_in(dat1),
.wr(we),
.wr_bit(wr_bit_r),
.bit_in(bit_in),
.t2(t2),
.t2ex(t2ex),
.rclk(rclk),
.tclk(tclk),
.brate2(brate2),
.tc2_int(tc2_int),
.pres_ow(pres_ow),
.t2con(t2con),
.tl2(tl2),
.th2(th2),
.rcap2l(rcap2l),
.rcap2h(rcap2h));
`else
assign tc2_int = 1'b0;
assign rclk = 1'b0;
assign tclk = 1'b0;
assign brate2 = 1'b0;
`endif
 
 
 
301,88 → 526,8
wr_bit_r <= #1 wr_bit;
end
 
/*
//
//set output in case of address (byte)
always @(adr0_r or psw or acc or dptr_hi or dptr_lo or b_reg or
//ports
p0_data or p1_data or p2_data or p3_data or
//interrupt control
ie or tcon or ip or
// t/c 2
t2con or tl2 or th2 or rcap2l or rcap2h or
// t/c 0,1
tmod or tl0 or th0 or tl1 or th1 or
// serial interface
scon or pcon or sbuf or
// stack
sp_out)
begin
case (adr0_r)
`OC8051_SFR_ACC: dat0 = acc;
`OC8051_SFR_PSW: dat0 = psw;
`OC8051_SFR_P0: dat0 = p0_data;
`OC8051_SFR_P1: dat0 = p1_data;
`OC8051_SFR_P2: dat0 = p2_data;
`OC8051_SFR_P3: dat0 = p3_data;
`OC8051_SFR_SP: dat0 = sp_out;
`OC8051_SFR_B: dat0 = b_reg;
`OC8051_SFR_DPTR_HI: dat0 = dptr_hi;
`OC8051_SFR_DPTR_LO: dat0 = dptr_lo;
`OC8051_SFR_SCON: dat0 = scon;
`OC8051_SFR_SBUF: dat0 = sbuf;
`OC8051_SFR_PCON: dat0 = pcon;
`OC8051_SFR_TH0: dat0 = th0;
`OC8051_SFR_TH1: dat0 = th1;
`OC8051_SFR_TL0: dat0 = tl0;
`OC8051_SFR_TL1: dat0 = tl1;
`OC8051_SFR_TMOD: dat0 = tmod;
`OC8051_SFR_IP: dat0 = ip;
`OC8051_SFR_IE: dat0 = ie;
`OC8051_SFR_TCON: dat0 = tcon;
`OC8051_SFR_RCAP2H: dat0 = rcap2h;
`OC8051_SFR_RCAP2L: dat0 = rcap2l;
`OC8051_SFR_TH2: dat0 = th2;
`OC8051_SFR_TL2: dat0 = tl2;
`OC8051_SFR_T2CON: dat0 = t2con;
default: dat0 = 8'h00;
endcase
end
 
 
//
//set output in case of address (bit)
always @(adr0_r or psw or acc or b_reg or
//ports
p0_data or p1_data or p2_data or p3_data or
//interrupt control
ie or tcon or ip or
// t/c 2
t2con or
// serial interface
scon)
begin
case (adr0_r[7:3])
`OC8051_SFR_B_ACC: bit_out = acc[adr0_r[2:0]];
`OC8051_SFR_B_PSW: bit_out = psw[adr0_r[2:0]];
`OC8051_SFR_B_P0: bit_out = p0_data[adr0_r[2:0]];
`OC8051_SFR_B_P1: bit_out = p1_data[adr0_r[2:0]];
`OC8051_SFR_B_P2: bit_out = p2_data[adr0_r[2:0]];
`OC8051_SFR_B_P3: bit_out = p3_data[adr0_r[2:0]];
`OC8051_SFR_B_B: bit_out = b_reg[adr0_r[2:0]];
`OC8051_SFR_B_IP: bit_out = ip[adr0_r[2:0]];
`OC8051_SFR_B_IE: bit_out = ie[adr0_r[2:0]];
`OC8051_SFR_B_TCON: bit_out = tcon[adr0_r[2:0]];
`OC8051_SFR_B_SCON: bit_out = scon[adr0_r[2:0]];
`OC8051_SFR_B_T2CON: bit_out = t2con[adr0_r[2:0]];
default: bit_out = 1'b0;
endcase
end
*/
 
 
 
//
//set output in case of address (byte)
always @(posedge clk or posedge rst)
begin
389,63 → 534,75
if (rst) begin
dat0 <= #1 8'h00;
wait_data <= #1 1'b0;
/* end else if (((adr0==`OC8051_SFR_PSW) & (((adr1==`OC8051_SFR_ACC) & we & !wr_bit_r)) |
(({adr1[7:3], 3'b000}==adr0) & we & wr_bit_r)) & !wait_data) begin
// dat0 <= #1 {dat1[7:1], p};
wait_data <= #1 1'b1;
end else if ((adr0==`OC8051_SFR_PSW) & (adr1==adr0) & we & !wr_bit_r & !wait_data) begin
// dat0 <= #1 {dat1[7:1], p};
wait_data <= #1 1'b1;*/
end else if ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) begin //write and read same address
dat0 <= #1 dat1;
wait_data <= #1 1'b0;
end else if (
(((wr_sfr==`OC8051_WRS_ACC1) & (adr0==`OC8051_SFR_ACC)) | //write to acc
(((wr_sfr==`OC8051_WRS_ACC1) & (adr0==`OC8051_SFR_ACC)) | //write to acc
((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) | //write to dpl
// ((wr_sfr==`OC8051_WRS_BA) & (adr0==`OC8051_SFR_B)) | //write to b
(adr1[7] & (adr1==adr0) & we & !wr_bit_r)) & !wait_data) begin //write and read same address
// dat0 <= #1 dat1;
(adr1[7] & (adr1==adr0) & we & !wr_bit_r)) & !wait_data) begin //write and read same address
wait_data <= #1 1'b1;
 
end else if (
(((wr_sfr==`OC8051_WRS_ACC2) & (adr0==`OC8051_SFR_ACC)) | //write to acc
((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_HI)) //write to dph
// ((wr_sfr==`OC8051_WRS_BA) & (adr0==`OC8051_SFR_ACC))
) & !wait_data) begin //write to b
// dat0 <= #1 dat2;
) & !wait_data) begin
wait_data <= #1 1'b1;
 
// else if (({adr1[7:3], 3'b000}==adr0_r) & we & wr_bit_r)
// dat0 <= #1 dat1;
end else begin
case (adr0)
`OC8051_SFR_ACC: dat0 <= #1 acc;
`OC8051_SFR_PSW: dat0 <= #1 psw;
 
`ifdef OC8051_PORTS
`ifdef OC8051_PORT0
`OC8051_SFR_P0: dat0 <= #1 p0_data;
`endif
 
`ifdef OC8051_PORT1
`OC8051_SFR_P1: dat0 <= #1 p1_data;
`endif
 
`ifdef OC8051_PORT2
`OC8051_SFR_P2: dat0 <= #1 p2_data;
`endif
 
`ifdef OC8051_PORT3
`OC8051_SFR_P3: dat0 <= #1 p3_data;
// `OC8051_SFR_SP: dat0 <= #1 sp_out;
`endif
`endif
 
`OC8051_SFR_SP: dat0 <= #1 sp;
`OC8051_SFR_B: dat0 <= #1 b_reg;
`OC8051_SFR_DPTR_HI: dat0 <= #1 dptr_hi;
`OC8051_SFR_DPTR_LO: dat0 <= #1 dptr_lo;
 
`ifdef OC8051_UART
`OC8051_SFR_SCON: dat0 <= #1 scon;
`OC8051_SFR_SBUF: dat0 <= #1 sbuf;
`OC8051_SFR_PCON: dat0 <= #1 pcon;
`endif
 
`ifdef OC8051_TC01
`OC8051_SFR_TH0: dat0 <= #1 th0;
`OC8051_SFR_TH1: dat0 <= #1 th1;
`OC8051_SFR_TL0: dat0 <= #1 tl0;
`OC8051_SFR_TL1: dat0 <= #1 tl1;
`OC8051_SFR_TMOD: dat0 <= #1 tmod;
`endif
 
`OC8051_SFR_IP: dat0 <= #1 ip;
`OC8051_SFR_IE: dat0 <= #1 ie;
`OC8051_SFR_TCON: dat0 <= #1 tcon;
 
`ifdef OC8051_TC2
`OC8051_SFR_RCAP2H: dat0 <= #1 rcap2h;
`OC8051_SFR_RCAP2L: dat0 <= #1 rcap2l;
`OC8051_SFR_TH2: dat0 <= #1 th2;
`OC8051_SFR_TL2: dat0 <= #1 tl2;
`OC8051_SFR_T2CON: dat0 <= #1 t2con;
`endif
 
default: dat0 <= #1 8'h00;
endcase
wait_data <= #1 1'b0;
462,8 → 619,7
else if (
((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) & we & !wr_bit_r) |
((wr_sfr==`OC8051_WRS_ACC1) & (adr0[7:3]==`OC8051_SFR_B_ACC)) //write to acc
// ((wr_sfr==`OC8051_WRS_BA) & (adr0[7:3]==`OC8051_SFR_B_B))
) //write to b
)
 
bit_out <= #1 dat1[adr0[2:0]];
else if ((adr1==adr0) & we & wr_bit_r)
472,19 → 628,54
case (adr0[7:3])
`OC8051_SFR_B_ACC: bit_out <= #1 acc[adr0[2:0]];
`OC8051_SFR_B_PSW: bit_out <= #1 psw[adr0[2:0]];
 
`ifdef OC8051_PORTS
`ifdef OC8051_PORT0
`OC8051_SFR_B_P0: bit_out <= #1 p0_data[adr0[2:0]];
`endif
 
`ifdef OC8051_PORT1
`OC8051_SFR_B_P1: bit_out <= #1 p1_data[adr0[2:0]];
`endif
 
`ifdef OC8051_PORT2
`OC8051_SFR_B_P2: bit_out <= #1 p2_data[adr0[2:0]];
`endif
 
`ifdef OC8051_PORT3
`OC8051_SFR_B_P3: bit_out <= #1 p3_data[adr0[2:0]];
`endif
`endif
 
`OC8051_SFR_B_B: bit_out <= #1 b_reg[adr0[2:0]];
`OC8051_SFR_B_IP: bit_out <= #1 ip[adr0[2:0]];
`OC8051_SFR_B_IE: bit_out <= #1 ie[adr0[2:0]];
`OC8051_SFR_B_TCON: bit_out <= #1 tcon[adr0[2:0]];
 
`ifdef OC8051_UART
`OC8051_SFR_B_SCON: bit_out <= #1 scon[adr0[2:0]];
`endif
 
`ifdef OC8051_TC2
`OC8051_SFR_B_T2CON: bit_out <= #1 t2con[adr0[2:0]];
`endif
 
default: bit_out <= #1 1'b0;
endcase
end
 
always @(posedge clk or posedge rst)
begin
if (rst) begin
prescaler <= #1 4'h0;
pres_ow <= #1 1'b0;
end else if (prescaler==4'b1011) begin
prescaler <= #1 4'h0;
pres_ow <= #1 1'b1;
end else begin
prescaler <= #1 prescaler + 4'h1;
pres_ow <= #1 1'b0;
end
end
 
endmodule
/trunk/rtl/verilog/oc8051_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.22 2003/04/09 16:24:04 simont
// change wr_sft to 2 bit wire.
//
// Revision 1.21 2003/04/09 15:49:42 simont
// Register oc8051_sfr dato output, add signal wait_data.
//
80,159 → 83,228
 
module oc8051_top (wb_rst_i, wb_clk_i,
//interface to instruction rom
wbi_adr_o, wbi_dat_i, wbi_stb_o, wbi_ack_i, wbi_cyc_o, wbi_err_i,
wbi_adr_o,
wbi_dat_i,
wbi_stb_o,
wbi_ack_i,
wbi_cyc_o,
wbi_err_i,
 
//interface to data ram
wbd_dat_i, wbd_dat_o,
wbd_adr_o, wbd_we_o, wbd_ack_i, wbd_stb_o, wbd_cyc_o, wbd_err_i,
wbd_dat_i,
wbd_dat_o,
wbd_adr_o,
wbd_we_o,
wbd_ack_i,
wbd_stb_o,
wbd_cyc_o,
wbd_err_i,
 
// interrupt interface
int0_i, int1_i,
int0_i,
int1_i,
 
// external access (active low)
ea_in,
 
// port interface
p0_i, p1_i, p2_i, p3_i,
p0_o, p1_o, p2_o, p3_o,
`ifdef OC8051_PORTS
`ifdef OC8051_PORT0
p0_i,
p0_o,
`endif
 
`ifdef OC8051_PORT1
p1_i,
p1_o,
`endif
 
`ifdef OC8051_PORT2
p2_i,
p2_o,
`endif
 
`ifdef OC8051_PORT3
p3_i,
p3_o,
`endif
`endif
 
// serial interface
`ifdef OC8051_UART
rxd_i, txd_o,
`endif
 
// counter interface
t0_i, t1_i, t2_i, t2ex_i);
`ifdef OC8051_TC01
t0_i, t1_i,
`endif
 
`ifdef OC8051_TC2
t2_i, t2ex_i
`endif
);
 
 
 
input wb_rst_i, // reset input
wb_clk_i, // clock input
int0_i, // interrupt 0
int1_i, // interrupt 1
ea_in, // external access
rxd_i, // receive
t0_i, // counter 0 input
t1_i, // counter 1 input
wbd_ack_i, // data acknowalge
wbi_ack_i, // instruction acknowlage
wbd_err_i, // data error
wbi_err_i, // instruction error
t2_i, // counter 2 input
t2ex_i; // ???
wbi_err_i; // instruction error
 
input [7:0] wbd_dat_i, // ram data input
p0_i, // port 0 input
p1_i, // port 1 input
p2_i, // port 2 input
p3_i; // port 3 input
input [7:0] wbd_dat_i; // ram data input
input [31:0] wbi_dat_i; // rom data input
 
output wbd_we_o, // data write enable
txd_o, // transnmit
wbd_stb_o, // data strobe
wbd_cyc_o, // data cycle
wbi_stb_o, // instruction strobe
wbi_cyc_o; // instruction cycle
 
output [7:0] wbd_dat_o, // data output
p0_o, // port 0 output
p1_o, // port 1 output
p2_o, // port 2 output
p3_o; // port 3 output
output [7:0] wbd_dat_o; // data output
 
output [15:0] wbd_adr_o, // data address
wbi_adr_o; // instruction address
 
`ifdef OC8051_PORTS
 
wire [7:0] op1_i, op2_i, op3_i, dptr_hi, dptr_lo, ri, rn_mem, data_out;
wire [7:0] op1, op2, op3;
wire [7:0] acc, p0_out, p1_out, p2_out, p3_out;
wire [7:0] sp, sp_w;
`ifdef OC8051_PORT0
input [7:0] p0_i; // port 0 input
output [7:0] p0_o; // port 0 output
`endif
 
wire [15:0] pc;
`ifdef OC8051_PORT1
input [7:0] p1_i; // port 1 input
output [7:0] p1_o; // port 1 output
`endif
 
assign wbd_cyc_o = wbd_stb_o;
//assign wbi_cyc_o = wbi_stb_o;
`ifdef OC8051_PORT2
input [7:0] p2_i; // port 2 input
output [7:0] p2_o; // port 2 output
`endif
 
//
// ram_rd_sel ram read (internal)
// ram_wr_sel ram write (internal)
// src_sel1, src_sel2 from decoder to register
wire src_sel3;
wire [1:0] wr_sfr;
wire [2:0] ram_rd_sel, ram_wr_sel;
wire [2:0] src_sel2, src_sel1;
`ifdef OC8051_PORT3
input [7:0] p3_i; // port 3 input
output [7:0] p3_o; // port 3 output
`endif
 
//
// wr_addr ram write addres
// ram_out data from ram
// rd_addr data ram read addres
// rd_addr_r data ram read addres registerd
wire [7:0] ram_data, ram_out, sfr_out, wr_dat;
wire [7:0] wr_addr, rd_addr;
wire sfr_bit;
`endif
 
 
//
// cy_sel carry select; from decoder to cy_selct1
// rom_addr_sel rom addres select; alu or pc
// ext_adddr_sel external addres select; data pointer or Ri
// write_p output from decoder; write to external ram, go to register;
wire [1:0] cy_sel, bank_sel;
wire rom_addr_sel, rmw, ea_int;
 
//
// int_uart interrupt from uart
// tf0 interrupt from t/c 0
// tf1 interrupt from t/c 1
// tr0 timer 0 run
// tr1 timer 1 run
wire reti, intr, int_ack, istb;
wire [7:0] int_src;
 
//
//alu_op alu operation (from decoder)
//psw_set write to psw or not; from decoder to psw (through register)
wire mem_wait;
wire [2:0] mem_act;
wire [3:0] alu_op;
wire [1:0] psw_set;
 
//
// immediate1_r from imediate_sel1 to alu_src1_sel1
// immediate2_r from imediate_sel1 to alu_src2_sel1
// src1. src2, src2 alu sources
// des2, des2 alu destinations
// des1_r destination 1 registerd (to comp1)
// desCy carry out
// desAc
// desOv overflow
// wr write to data ram
wire [7:0] src1, src2, des1, des2, des1_r;
wire [7:0] src3;
wire desCy, desAc, desOv, alu_cy, wr, wr_o;
 
`ifdef OC8051_UART
input rxd_i; // receive
output txd_o; // transnmit
`endif
 
//
// rd read program rom
// pc_wr_sel program counter write select (from decoder to pc)
wire rd, pc_wr;
wire [2:0] pc_wr_sel;
`ifdef OC8051_TC01
input t0_i, // counter 0 input
t1_i; // counter 1 input
`endif
 
//
// op1_n from op_select to decoder
// op2_n, output of op_select, to immediate_sel1, pc1, comp1
// op3_n, output of op_select, to immediate_sel1, ram_wr_sel1
// op2_dr, output of op_select, to ram_rd_sel1, ram_wr_sel1
wire [7:0] op1_n, op2_n, op3_n;
`ifdef OC8051_TC2
input t2_i, // counter 2 input
t2ex_i; //
`endif
 
//
// comp_sel select source1 and source2 to compare
// eq result (from comp1 to decoder)
wire [1:0] comp_sel;
wire eq, srcAc, cy, rd_ind, wr_ind;
wire [2:0] op1_cur;
wire [7:0] op1_i,
op2_i,
op3_i,
dptr_hi,
dptr_lo,
ri,
rn_mem,
data_out,
op1,
op2,
op3,
acc,
p0_out,
p1_out,
p2_out,
p3_out,
sp,
sp_w;
 
wire [15:0] pc;
 
//
// bit_addr bit addresable instruction
// bit_data bit data from ram to ram_select
// bit_out bit data from ram_select to alu and cy_select
wire bit_addr, bit_data, bit_out, bit_addr_o;
assign wbd_cyc_o = wbd_stb_o;
 
wire src_sel3;
wire [1:0] wr_sfr;
wire [2:0] ram_rd_sel, // ram read
ram_wr_sel, // ram write
src_sel2,
src_sel1;
 
wire [7:0] ram_data,
ram_out, //data from ram
sfr_out,
wr_dat,
wr_addr, //ram write addres
rd_addr; //data ram read addres
wire sfr_bit;
 
wire [1:0] cy_sel, //carry select; from decoder to cy_selct1
bank_sel;
wire rom_addr_sel, //rom addres select; alu or pc
rmw,
ea_int;
 
wire reti,
intr,
int_ack,
istb;
wire [7:0] int_src;
 
wire mem_wait;
wire [2:0] mem_act;
wire [3:0] alu_op; //alu operation (from decoder)
wire [1:0] psw_set; //write to psw or not; from decoder to psw (through register)
 
wire [7:0] src1, //alu sources 1
src2, //alu sources 2
src3, //alu sources 3
des1, //alu destination 1
des2, //alu destinations 2
des1_r; //destination 1 registerd (to comp1)
wire desCy, //carry out
desAc,
desOv, //overflow
alu_cy,
wr, //write to data ram
wr_o;
 
wire rd, //read program rom
pc_wr;
wire [2:0] pc_wr_sel; //program counter write select (from decoder to pc)
 
wire [7:0] op1_n, //from memory_interface to decoder
op2_n,
op3_n;
 
wire [1:0] comp_sel; //select source1 and source2 to compare
wire eq, //result (from comp1 to decoder)
srcAc,
cy,
rd_ind,
wr_ind;
wire [2:0] op1_cur;
 
wire bit_addr, //bit addresable instruction
bit_data, //bit data from ram to ram_select
bit_out, //bit data from ram_select to alu and cy_select
bit_addr_o,
wait_data;
 
//
// cpu to cache/wb_interface
wire iack_i,
240,63 → 312,133
icyc_o;
wire [31:0] idat_i;
wire [15:0] iadr_o;
wire wait_data;
 
 
//
// decoder
oc8051_decoder oc8051_decoder1(.clk(wb_clk_i), .rst(wb_rst_i), .op_in(op1_n), .op1_c(op1_cur),
.ram_rd_sel_o(ram_rd_sel), .ram_wr_sel_o(ram_wr_sel), .bit_addr(bit_addr),
.src_sel1(src_sel1), .src_sel2(src_sel2),
.src_sel3(src_sel3), .alu_op_o(alu_op), .psw_set(psw_set),
.cy_sel(cy_sel), .wr_o(wr), .pc_wr(pc_wr),
.pc_sel(pc_wr_sel), .comp_sel(comp_sel), .eq(eq),
.wr_sfr_o(wr_sfr), .rd(rd), .rmw(rmw),
.istb(istb), .mem_act(mem_act), .mem_wait(mem_wait),
.wait_data(wait_data));
oc8051_decoder oc8051_decoder1(.clk(wb_clk_i),
.rst(wb_rst_i),
.op_in(op1_n),
.op1_c(op1_cur),
.ram_rd_sel_o(ram_rd_sel),
.ram_wr_sel_o(ram_wr_sel),
.bit_addr(bit_addr),
 
.src_sel1(src_sel1),
.src_sel2(src_sel2),
.src_sel3(src_sel3),
 
.alu_op_o(alu_op),
.psw_set(psw_set),
.cy_sel(cy_sel),
.wr_o(wr),
.pc_wr(pc_wr),
.pc_sel(pc_wr_sel),
.comp_sel(comp_sel),
.eq(eq),
.wr_sfr_o(wr_sfr),
.rd(rd),
.rmw(rmw),
.istb(istb),
.mem_act(mem_act),
.mem_wait(mem_wait),
.wait_data(wait_data));
 
 
//
//alu
oc8051_alu oc8051_alu1(.rst(wb_rst_i), .clk(wb_clk_i), .op_code(alu_op), .rd(rd),
.src1(src1), .src2(src2), .src3(src3), .srcCy(alu_cy), .srcAc(srcAc),
.des1(des1), .des2(des2), .des1_r(des1_r), .desCy(desCy),
.desAc(desAc), .desOv(desOv), .bit_in(bit_out));
oc8051_alu oc8051_alu1(.rst(wb_rst_i),
.clk(wb_clk_i),
.op_code(alu_op),
.rd(rd),
.src1(src1),
.src2(src2),
.src3(src3),
.srcCy(alu_cy),
.srcAc(srcAc),
.des1(des1),
.des2(des2),
.des1_r(des1_r),
.desCy(desCy),
.desAc(desAc),
.desOv(desOv),
.bit_in(bit_out));
 
//
//data ram
oc8051_ram_top oc8051_ram_top1(.clk(wb_clk_i), .rst(wb_rst_i), .rd_addr(rd_addr), .rd_data(ram_data),
.wr_addr(wr_addr), .bit_addr(bit_addr_o), .wr_data(wr_dat), .wr(wr_o && (!wr_addr[7] || wr_ind)),
.bit_data_in(desCy), .bit_data_out(bit_data));
oc8051_ram_top oc8051_ram_top1(.clk(wb_clk_i),
.rst(wb_rst_i),
.rd_addr(rd_addr),
.rd_data(ram_data),
.wr_addr(wr_addr),
.bit_addr(bit_addr_o),
.wr_data(wr_dat),
.wr(wr_o && (!wr_addr[7] || wr_ind)),
.bit_data_in(desCy),
.bit_data_out(bit_data));
 
//
 
oc8051_alu_src_sel oc8051_alu_src_sel1(.clk(wb_clk_i), .rst(wb_rst_i), .rd(rd),
.sel1(src_sel1), .sel2(src_sel2), .sel3(src_sel3),
.acc(acc), .ram(ram_out), .pc(pc), .dptr({dptr_hi, dptr_lo}),
.op1(op1_n), .op2(op2_n), .op3(op3_n),
.src1(src1), .src2(src2), .src3(src3));
oc8051_alu_src_sel oc8051_alu_src_sel1(.clk(wb_clk_i),
.rst(wb_rst_i),
.rd(rd),
 
.sel1(src_sel1),
.sel2(src_sel2),
.sel3(src_sel3),
 
.acc(acc),
.ram(ram_out),
.pc(pc),
.dptr({dptr_hi, dptr_lo}),
.op1(op1_n),
.op2(op2_n),
.op3(op3_n),
 
.src1(src1),
.src2(src2),
.src3(src3));
 
 
//
//
oc8051_comp oc8051_comp1(.sel(comp_sel), .eq(eq), .b_in(bit_out), .cy(cy), .acc(acc), .des(des1_r));
oc8051_comp oc8051_comp1(.sel(comp_sel),
.eq(eq),
.b_in(bit_out),
.cy(cy),
.acc(acc),
.des(des1_r));
 
 
//
//program rom
oc8051_rom oc8051_rom1(.rst(wb_rst_i), .clk(wb_clk_i), .ea_int(ea_int), .addr(iadr_o),
.data1(op1_i), .data2(op2_i), .data3(op3_i));
oc8051_rom oc8051_rom1(.rst(wb_rst_i),
.clk(wb_clk_i),
.ea_int(ea_int),
.addr(iadr_o),
.data1(op1_i),
.data2(op2_i),
.data3(op3_i));
 
//
//
oc8051_cy_select oc8051_cy_select1(.cy_sel(cy_sel), .cy_in(cy), .data_in(bit_out),
.data_out(alu_cy));
oc8051_cy_select oc8051_cy_select1(.cy_sel(cy_sel),
.cy_in(cy),
.data_in(bit_out),
.data_out(alu_cy));
//
//
oc8051_indi_addr oc8051_indi_addr1 (.clk(wb_clk_i), .rst(wb_rst_i), .rd_addr(rd_addr), .wr_addr(wr_addr),
.data_in(wr_dat), .wr(wr_o), .wr_bit(bit_addr_o), .rn_out(rn_mem),
.ri_out(ri), .sel(op1_cur), .bank(bank_sel));
oc8051_indi_addr oc8051_indi_addr1 (.clk(wb_clk_i),
.rst(wb_rst_i),
.rd_addr(rd_addr),
.wr_addr(wr_addr),
.data_in(wr_dat),
.wr(wr_o),
.wr_bit(bit_addr_o),
.rn_out(rn_mem),
.ri_out(ri),
.sel(op1_cur),
.bank(bank_sel));
 
 
 
303,81 → 445,169
assign icyc_o = istb_o;
//
//
oc8051_memory_interface oc8051_memory_interface1(.clk(wb_clk_i), .rst(wb_rst_i),
oc8051_memory_interface oc8051_memory_interface1(.clk(wb_clk_i),
.rst(wb_rst_i),
// internal ram
.wr_i(wr), .wr_o(wr_o), .wr_bit_i(bit_addr), .wr_bit_o(bit_addr_o), .wr_dat(wr_dat),
.des1(des1), .des2(des2),
.rd_addr(rd_addr), .wr_addr(wr_addr),
.wr_ind(wr_ind),
.bit_in(bit_data), .in_ram(ram_data),
.sfr(sfr_out), .sfr_bit(sfr_bit), .bit_out(bit_out), .iram_out(ram_out),
.wr_i(wr),
.wr_o(wr_o),
.wr_bit_i(bit_addr),
.wr_bit_o(bit_addr_o),
.wr_dat(wr_dat),
.des1(des1),
.des2(des2),
.rd_addr(rd_addr),
.wr_addr(wr_addr),
.wr_ind(wr_ind),
.bit_in(bit_data),
.in_ram(ram_data),
.sfr(sfr_out),
.sfr_bit(sfr_bit),
.bit_out(bit_out),
.iram_out(ram_out),
 
// external instrauction rom
.iack_i(iack_i),
.iadr_o(iadr_o),
.idat_i(idat_i),
.istb_o(istb_o),
.iack_i(iack_i),
.iadr_o(iadr_o),
.idat_i(idat_i),
.istb_o(istb_o),
 
// internal instruction rom
.op1_i(op1_i), .op2_i(op2_i), .op3_i(op3_i),
.op1_i(op1_i),
.op2_i(op2_i),
.op3_i(op3_i),
 
// data memory
.dadr_o(wbd_adr_o), .ddat_o(wbd_dat_o),
.dwe_o(wbd_we_o), .dstb_o(wbd_stb_o),
.ddat_i(wbd_dat_i), .dack_i(wbd_ack_i),
.dadr_o(wbd_adr_o),
.ddat_o(wbd_dat_o),
.dwe_o(wbd_we_o),
.dstb_o(wbd_stb_o),
.ddat_i(wbd_dat_i),
.dack_i(wbd_ack_i),
 
// from decoder
.rd_sel(ram_rd_sel), .wr_sel(ram_wr_sel), .rn({bank_sel, op1_n[2:0]}),
.rd_ind(rd_ind), .rd(rd),
.mem_act(mem_act), .mem_wait(mem_wait),
.rd_sel(ram_rd_sel),
.wr_sel(ram_wr_sel),
.rn({bank_sel, op1_n[2:0]}),
.rd_ind(rd_ind),
.rd(rd),
.mem_act(mem_act),
.mem_wait(mem_wait),
 
// external access
.ea(ea_in), .ea_int(ea_int),
.ea(ea_in),
.ea_int(ea_int),
 
// instructions outputs to cpu
.op1_out(op1_n), .op2_out(op2_n), .op3_out(op3_n),
.op1_out(op1_n),
.op2_out(op2_n),
.op3_out(op3_n),
 
// interrupt interface
.intr(intr), .int_v(int_src), .int_ack(int_ack), .istb(istb),
.reti(reti),
.intr(intr),
.int_v(int_src),
.int_ack(int_ack),
.istb(istb),
.reti(reti),
 
//pc
.pc_wr_sel(pc_wr_sel), .pc_wr(pc_wr), .pc(pc),
.pc_wr_sel(pc_wr_sel),
.pc_wr(pc_wr),
.pc(pc),
 
// sfr's
.sp_w(sp_w), .dptr({dptr_hi, dptr_lo}),
.ri(ri), .rn_mem(rn_mem),
.acc(acc), .sp(sp)
);
.sp_w(sp_w),
.dptr({dptr_hi, dptr_lo}),
.ri(ri),
.rn_mem(rn_mem),
.acc(acc),
.sp(sp)
);
 
 
//
//
 
oc8051_sfr oc8051_sfr1(.rst(wb_rst_i), .clk(wb_clk_i), .adr0(rd_addr[7:0]), .adr1(wr_addr[7:0]),
.dat0(sfr_out), .dat1(wr_dat), .dat2(des2), .we(wr_o && !wr_ind), .bit_in(desCy),
.bit_out(sfr_bit), .wr_bit(bit_addr_o), .ram_rd_sel(ram_rd_sel), .ram_wr_sel(ram_wr_sel),
.wr_sfr(wr_sfr),
oc8051_sfr oc8051_sfr1(.rst(wb_rst_i),
.clk(wb_clk_i),
.adr0(rd_addr[7:0]),
.adr1(wr_addr[7:0]),
.dat0(sfr_out),
.dat1(wr_dat),
.dat2(des2),
.we(wr_o && !wr_ind),
.bit_in(desCy),
.bit_out(sfr_bit),
.wr_bit(bit_addr_o),
.ram_rd_sel(ram_rd_sel),
.ram_wr_sel(ram_wr_sel),
.wr_sfr(wr_sfr),
// acc
.acc(acc),
.acc(acc),
// sp
.sp(sp), .sp_w(sp_w),
.sp(sp),
.sp_w(sp_w),
// psw
.bank_sel(bank_sel), .desAc(desAc), .desOv(desOv), .psw_set(psw_set),
.srcAc(srcAc), .cy(cy),
.bank_sel(bank_sel),
.desAc(desAc),
.desOv(desOv),
.psw_set(psw_set),
.srcAc(srcAc),
.cy(cy),
// ports
.rmw(rmw), .p0_out(p0_o), .p1_out(p1_o), .p2_out(p2_o), .p3_out(p3_o),
.p0_in(p0_i), .p1_in(p1_i), .p2_in(p2_i), .p3_in(p3_i),
.rmw(rmw),
 
`ifdef OC8051_PORTS
`ifdef OC8051_PORT0
.p0_out(p0_o),
.p0_in(p0_i),
`endif
 
`ifdef OC8051_PORT1
.p1_out(p1_o),
.p1_in(p1_i),
`endif
 
`ifdef OC8051_PORT2
.p2_out(p2_o),
.p2_in(p2_i),
`endif
 
`ifdef OC8051_PORT3
.p3_out(p3_o),
.p3_in(p3_i),
`endif
`endif
 
// uart
.rxd(rxd_i), .txd(txd_o),
`ifdef OC8051_UART
.rxd(rxd_i), .txd(txd_o),
`endif
 
// int
.int_ack(int_ack), .intr(intr), .int0(int0_i), .int1(int1_i),
.reti(reti), .int_src(int_src),
// t/c
.t0(t0_i), .t1(t1_i), .t2(t2_i), .t2ex(t2ex_i),
.int_ack(int_ack),
.intr(intr),
.int0(int0_i),
.int1(int1_i),
.reti(reti),
.int_src(int_src),
 
// t/c 0,1
`ifdef OC8051_TC01
.t0(t0_i),
.t1(t1_i),
`endif
 
// t/c 2
`ifdef OC8051_TC2
.t2(t2_i),
.t2ex(t2ex_i),
`endif
 
// dptr
.dptr_hi(dptr_hi), .dptr_lo(dptr_lo),
.wait_data(wait_data));
.dptr_hi(dptr_hi),
.dptr_lo(dptr_lo),
.wait_data(wait_data)
);
 
 
 
/trunk/rtl/verilog/oc8051_tc.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7 2003/04/07 14:58:02 simont
// change sfr's interface.
//
// Revision 1.6 2003/04/04 10:34:13 simont
// change timers to meet timing specifications (add divider with 12)
//
86,23 → 89,20
tr0,
tr1,
t0,
t1;
output [7:0] tmod,
tl0,
th0,
tl1,
t1,
pres_ow;
output [7:0] tmod,
tl0,
th0,
tl1,
th1;
output tf0,
tf1,
pres_ow;
tf1;
 
 
reg [7:0] tmod, tl0, th0, tl1, th1;
reg tf0, tf1_0, tf1_1, t0_buff, t1_buff;
 
reg pres_ow;
reg [3:0] prescaler;
 
wire tc0_add, tc1_add;
 
assign tc0_add = (tr0 & (!tmod[3] | !ie0) & ((!tmod[2] & pres_ow) | (tmod[2] & !t0 & t0_buff)));
228,21 → 228,7
 
 
always @(posedge clk or posedge rst)
begin
if (rst) begin
prescaler <= #1 4'h0;
pres_ow <= #1 1'b0;
end else if (prescaler==4'b1011) begin
prescaler <= #1 4'h0;
pres_ow <= #1 1'b1;
end else begin
prescaler <= #1 prescaler + 4'h1;
pres_ow <= #1 1'b0;
end
end
 
always @(posedge clk or posedge rst)
if (rst) begin
t0_buff <= #1 1'b0;
t1_buff <= #1 1'b0;
end else begin
/trunk/rtl/verilog/oc8051_ports.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8 2003/04/07 14:58:02 simont
// change sfr's interface.
//
// Revision 1.7 2003/01/13 14:14:41 simont
// replace some modules
//
60,60 → 63,129
`include "oc8051_defines.v"
 
 
module oc8051_ports (clk, rst,
bit_in, data_in,
wr, wr_bit,
wr_addr, rmw,
p0_out, p1_out, p2_out, p3_out,
p0_in, p1_in, p2_in, p3_in,
p0_data, p1_data, p2_data, p3_data);
//
// clk (in) clock
// rst (in) reset
// bit_in (in) bit input [oc8051_alu.desCy]
// data_in (in) data input (from alu destiantion 1) [oc8051_alu.des1]
// wr (in) write [oc8051_decoder.wr -r]
// wr_bit (in) write bit addresable [oc8051_decoder.bit_addr -r]
// wr_addr (in) write address [oc8051_ram_wr_sel.out]
// rd_addr (in) read address [oc8051_ram_rd_sel.out]
// rmw (in) read modify write feature [oc8051_decoder.rmw]
// data_out (out) data output [oc8051_ram_sel.ports_in]
// p0_out, p1_out, p2_out, p3_out (out) port outputs [pin]
// p0_in, p1_in, p2_in, p3_in (in) port inputs [pin]
//
module oc8051_ports (clk,
rst,
bit_in,
data_in,
wr,
wr_bit,
wr_addr,
 
`ifdef OC8051_PORT0
p0_out,
p0_in,
p0_data,
`endif
 
input clk, rst, wr, wr_bit, bit_in, rmw;
input [7:0] wr_addr, data_in, p0_in, p1_in, p2_in, p3_in;
`ifdef OC8051_PORT1
p1_out,
p1_in,
p1_data,
 
output [7:0] p0_out, p1_out, p2_out, p3_out;
output [7:0] p0_data, p1_data, p2_data, p3_data;
`endif
 
reg [7:0] p0_out, p1_out, p2_out, p3_out;
`ifdef OC8051_PORT2
p2_out,
p2_in,
p2_data,
`endif
 
assign p0_data = rmw ? p0_out : p0_in;
assign p1_data = rmw ? p1_out : p1_in;
assign p2_data = rmw ? p2_out : p2_in;
assign p3_data = rmw ? p3_out : p3_in;
`ifdef OC8051_PORT3
p3_out,
p3_in,
p3_data,
`endif
 
rmw);
 
input clk, //clock
rst, //reset
wr, //write [oc8051_decoder.wr -r]
wr_bit, //write bit addresable [oc8051_decoder.bit_addr -r]
bit_in, //bit input [oc8051_alu.desCy]
rmw; //read modify write feature [oc8051_decoder.rmw]
input [7:0] wr_addr, //write address [oc8051_ram_wr_sel.out]
data_in; //data input (from alu destiantion 1) [oc8051_alu.des1]
 
`ifdef OC8051_PORT0
input [7:0] p0_in;
output [7:0] p0_out,
p0_data;
reg [7:0] p0_out;
 
assign p0_data = rmw ? p0_out : p0_in;
`endif
 
 
`ifdef OC8051_PORT1
input [7:0] p1_in;
output [7:0] p1_out,
p1_data;
reg [7:0] p1_out;
 
assign p1_data = rmw ? p1_out : p1_in;
`endif
 
 
`ifdef OC8051_PORT2
input [7:0] p2_in;
output [7:0] p2_out,
p2_data;
reg [7:0] p2_out;
 
assign p2_data = rmw ? p2_out : p2_in;
`endif
 
 
`ifdef OC8051_PORT3
input [7:0] p3_in;
output [7:0] p3_out,
p3_data;
reg [7:0] p3_out;
 
assign p3_data = rmw ? p3_out : p3_in;
`endif
 
//
// case of writing to port
always @(posedge clk or posedge rst)
begin
if (rst) begin
`ifdef OC8051_PORT0
p0_out <= #1 `OC8051_RST_P0;
`endif
 
`ifdef OC8051_PORT1
p1_out <= #1 `OC8051_RST_P1;
`endif
 
`ifdef OC8051_PORT2
p2_out <= #1 `OC8051_RST_P2;
`endif
 
`ifdef OC8051_PORT3
p3_out <= #1 `OC8051_RST_P3;
`endif
end else if (wr) begin
if (!wr_bit) begin
case (wr_addr)
//
// bytaddresable
`ifdef OC8051_PORT0
`OC8051_SFR_P0: p0_out <= #1 data_in;
`endif
 
`ifdef OC8051_PORT1
`OC8051_SFR_P1: p1_out <= #1 data_in;
`endif
 
`ifdef OC8051_PORT2
`OC8051_SFR_P2: p2_out <= #1 data_in;
`endif
 
`ifdef OC8051_PORT3
`OC8051_SFR_P3: p3_out <= #1 data_in;
`endif
endcase
end else begin
case (wr_addr[7:3])
120,10 → 192,21
 
//
// bit addressable
`ifdef OC8051_PORT0
`OC8051_SFR_B_P0: p0_out[wr_addr[2:0]] <= #1 bit_in;
`endif
 
`ifdef OC8051_PORT1
`OC8051_SFR_B_P1: p1_out[wr_addr[2:0]] <= #1 bit_in;
`endif
 
`ifdef OC8051_PORT2
`OC8051_SFR_B_P2: p2_out[wr_addr[2:0]] <= #1 bit_in;
`endif
 
`ifdef OC8051_PORT3
`OC8051_SFR_B_P3: p3_out[wr_addr[2:0]] <= #1 bit_in;
`endif
endcase
end
end

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