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https://opencores.org/ocsvn/or1k/or1k/trunk
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- from Rev 1191 to Rev 1192
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Rev 1191 → Rev 1192
/trunk/orp/orp_soc/rtl/verilog/xsv_fpga_top.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.8 2003/04/07 21:05:58 lampret |
// WB = 1/2 RISC clock test code enabled. |
// |
// Revision 1.7 2003/04/07 01:28:17 lampret |
// Adding OR1200_CLMODE_1TO2 test code. |
// |
65,7 → 68,10
// |
|
`include "xsv_fpga_defines.v" |
|
// synopsys translate_off |
`include "bench_defines.v" |
// synopsys translate_on |
|
module xsv_fpga_top ( |
|
603,12 → 609,17
// access to real Flash area will automatically |
// move SRAM to 0x0. |
// |
|
`ifdef NO_FLASH_INSTRUCION_ADDR |
always prefix_flash <= #1 1'b0; |
`else |
always @(posedge wb_clk or negedge rstn) |
if (!rstn) |
prefix_flash <= #1 1'b1; |
else if (wb_rim_cyc_o && |
(wb_rim_adr_o[31:32-`APP_ADDR_DEC_W] == `APP_ADDR_FLASH)) |
prefix_flash <= #1 1'b0; |
prefix_flash <= #1 1'b0; |
`endif |
assign wb_rif_adr = prefix_flash ? {`APP_ADDR_FLASH, wb_rim_adr_o[31-`APP_ADDR_DEC_W:0]} |
: wb_rim_adr_o; |
assign wb_rdm_ack_i = (wb_rdm_adr_o[31:28] == `APP_ADDR_FAKEMC) && |
620,38 → 631,38
ssvga_top ssvga_top ( |
|
// Clock and reset |
.wb_clk_i ( wb_clk ), |
.wb_clk_i ( wb_clk ), |
.wb_rst_i ( wb_rst ), |
|
|
// WISHBONE Master I/F |
.wbm_cyc_o ( wb_vm_cyc_o ), |
.wbm_stb_o ( wb_vm_stb_o ), |
.wbm_sel_o ( wb_vm_sel_o ), |
.wbm_cyc_o ( wb_vm_cyc_o ), |
.wbm_stb_o ( wb_vm_stb_o ), |
.wbm_sel_o ( wb_vm_sel_o ), |
.wbm_we_o ( wb_vm_we_o ), |
.wbm_adr_o ( wb_vm_adr_o ), |
.wbm_dat_o ( ), |
.wbm_adr_o ( wb_vm_adr_o ), |
.wbm_dat_o ( ), |
.wbm_cab_o ( wb_vm_cab_o ), |
.wbm_dat_i ( wb_vm_dat_i ), |
.wbm_ack_i ( wb_vm_ack_i ), |
.wbm_err_i ( wb_vm_err_i ), |
.wbm_dat_i ( wb_vm_dat_i ), |
.wbm_ack_i ( wb_vm_ack_i ), |
.wbm_err_i ( wb_vm_err_i ), |
.wbm_rty_i ( 1'b0 ), |
|
// WISHBONE Slave I/F |
.wbs_cyc_i ( wb_vs_cyc_i ), |
.wbs_stb_i ( wb_vs_stb_i ), |
.wbs_sel_i ( wb_vs_sel_i ), |
.wbs_cyc_i ( wb_vs_cyc_i ), |
.wbs_stb_i ( wb_vs_stb_i ), |
.wbs_sel_i ( wb_vs_sel_i ), |
.wbs_we_i ( wb_vs_we_i ), |
.wbs_adr_i ( wb_vs_adr_i ), |
.wbs_dat_i ( wb_vs_dat_i ), |
.wbs_adr_i ( wb_vs_adr_i ), |
.wbs_dat_i ( wb_vs_dat_i ), |
.wbs_cab_i ( 1'b0 ), |
.wbs_dat_o ( wb_vs_dat_o ), |
.wbs_ack_o ( wb_vs_ack_o ), |
.wbs_err_o ( wb_vs_err_o ), |
.wbs_dat_o ( wb_vs_dat_o ), |
.wbs_ack_o ( wb_vs_ack_o ), |
.wbs_err_o ( wb_vs_err_o ), |
.wbs_rty_o ( ), |
|
// Signals to VGA display |
.pad_hsync_o ( crt_hsync ), |
.pad_vsync_o ( crt_vsync ), |
.pad_hsync_o ( crt_hsync ), |
.pad_vsync_o ( crt_vsync ), |
.pad_rgb_o ( {vga_r_int, vga_g_int, vga_b_int} ), |
.led_o ( ) |
); |
674,7 → 685,7
// This controller connects to AK4520A Codec chip. |
// |
audio_top audio_top ( |
|
|
// WISHBONE common |
.wb_clk_i ( wb_clk ), |
.wb_rst_i ( wb_rst ), |
722,15 → 733,15
.tck_pad_i ( jtag_tck ), |
.trst_pad_i ( jtag_trst ), |
.tdi_pad_i ( jtag_tdi ), |
.tdo_pad_o ( jtag_tdo ), |
.tdo_pad_o ( jtag_tdo ), |
|
// Boundary Scan signals |
.capture_dr_o ( ), |
.shift_dr_o ( ), |
.update_dr_o ( ), |
.extest_selected_o ( ), |
.capture_dr_o ( ), |
.shift_dr_o ( ), |
.update_dr_o ( ), |
.extest_selected_o ( ), |
.bs_chain_i ( 1'b0 ), |
|
|
// RISC signals |
.risc_clk_i ( wb_clk ), |
.risc_data_i ( dbg_dat_risc ), |
775,10 → 786,10
.tdo_padoen_o ( ), |
|
// Boundary Scan signals |
.capture_dr_o ( ), |
.shift_dr_o ( ), |
.update_dr_o ( ), |
.extest_selected_o ( ), |
.capture_dr_o ( ), |
.shift_dr_o ( ), |
.update_dr_o ( ), |
.extest_selected_o ( ), |
.bs_chain_i ( 1'b0 ), |
.bs_chain_o ( ), |
|
964,7 → 975,7
uart_top uart_top ( |
|
// WISHBONE common |
.wb_clk_i ( wb_clk ), |
.wb_clk_i ( wb_clk ), |
.wb_rst_i ( wb_rst ), |
|
// WISHBONE slave |
1012,18 → 1023,18
.wb_cyc_i ( wb_es_cyc_i ), |
.wb_stb_i ( wb_es_stb_i ), |
.wb_ack_o ( wb_es_ack_o ), |
.wb_err_o ( wb_es_err_o ), |
.wb_err_o ( wb_es_err_o ), |
|
// WISHBONE master |
.m_wb_adr_o ( wb_em_adr_o ), |
.m_wb_sel_o ( wb_em_sel_o ), |
.m_wb_we_o ( wb_em_we_o ), |
.m_wb_we_o ( wb_em_we_o ), |
.m_wb_dat_o ( wb_em_dat_o ), |
.m_wb_dat_i ( wb_em_dat_i ), |
.m_wb_cyc_o ( wb_em_cyc_o ), |
.m_wb_cyc_o ( wb_em_cyc_o ), |
.m_wb_stb_o ( wb_em_stb_o ), |
.m_wb_ack_i ( wb_em_ack_i ), |
.m_wb_err_i ( wb_em_err_i ), |
.m_wb_err_i ( wb_em_err_i ), |
|
// TX |
.mtx_clk_pad_i ( eth_tx_clk ), |
1038,7 → 1049,7
.mrxerr_pad_i ( eth_rx_er ), |
.mcoll_pad_i ( eth_col ), |
.mcrs_pad_i ( eth_crs ), |
|
|
// MIIM |
.mdc_pad_o ( eth_mdc ), |
.md_pad_i ( eth_mdio ), |