OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

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Rev 1199 → Rev 1200

/trunk/or1200/rtl/verilog/or1200_spram_1024x8.v
63,6 → 63,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2003/08/19 16:41:23 simons
// Scan signals mess fixed.
//
// Revision 1.4 2003/08/11 13:32:19 simons
// BIST interface added for Artisan memory instances.
//
103,7 → 106,7
module or1200_spram_1024x8(
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
119,11 → 122,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
output mbist_so_o;
`endif
 
//
147,7 → 148,7
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
171,11 → 172,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
246,11 → 245,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
/trunk/or1200/rtl/verilog/or1200_ic_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.6 2002/03/29 15:16:55 lampret
// Some of the warnings fixed.
//
109,7 → 112,7
 
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
// SPRs
161,11 → 164,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
output mbist_so_o;
`endif
 
//
201,11 → 202,11
//
// RAM BIST
//
wire scanb_ram_so;
wire scanb_tag_so;
wire scanb_ram_si = scanb_si;
wire scanb_tag_si = scanb_ram_so;
assign scanb_so = scanb_tag_so;
wire mbist_ram_so;
wire mbist_tag_so;
wire mbist_ram_si = mbist_si_i;
wire mbist_tag_si = mbist_ram_so;
assign mbist_so_o = mbist_tag_so;
`endif
 
//
297,11 → 298,9
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_ram_si),
.scanb_so(scanb_ram_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_ram_si),
.mbist_so_o(mbist_ram_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.addr(ic_addr[`OR1200_ICINDXH:2]),
.en(ic_en),
318,11 → 317,9
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_tag_si),
.scanb_so(scanb_tag_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_tag_si),
.mbist_so_o(mbist_tag_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.addr(ictag_addr),
.en(ictag_en),
/trunk/or1200/rtl/verilog/or1200_defines.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.35 2003/04/24 00:16:07 lampret
// No functional changes. Added defines to disable implementation of multiplier/MAC
//
// Revision 1.34 2003/04/20 22:23:57 lampret
// No functional change. Only added customization for exception vectors.
//
60,7 → 63,7
// Previous check-in was done by mistake.
//
// Revision 1.29 2002/10/28 15:03:50 mohor
// Signal scanb_sen renamed to scanb_en.
// Signal mbist_sen renamed to mbist_ctrl_i.
//
// Revision 1.28 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
337,6 → 340,9
//
//`define OR1200_BIST
 
// width of MBIST control bus
`define OR1200_MBIST_CTRL_WIDTH 3
 
//
// Register OR1200 WISHBONE outputs
// (must be defined/enabled)
/trunk/or1200/rtl/verilog/or1200_dc_tag.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
75,7 → 78,7
 
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
// Internal i/f
101,11 → 104,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
output mbist_so_o;
`endif
 
`ifdef OR1200_NO_DC
116,7 → 117,7
assign tag = {dw-1{1'b0}};
assign tag_v = 1'b0;
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
assign mbist_so_o = mbist_si_i;
`endif
 
`else
132,11 → 133,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.clk(clk),
.rst(rst),
/trunk/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
63,6 → 63,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2003/09/12 09:03:54 dries
// correct all the syntax errors
//
// Revision 1.1 2003/08/26 09:37:02 simons
// Added support for rams with byte write access.
//
76,7 → 79,7
module or1200_spram_2048x32_bw(
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
86,11 → 89,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
output mbist_so_o;
`endif
 
//
114,7 → 115,7
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
138,11 → 139,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
203,19 → 202,19
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef OR1200_BIST
wire scanb_si_ram_0;
wire scanb_si_ram_1;
wire scanb_si_ram_2;
wire scanb_si_ram_3;
wire scanb_so_ram_0;
wire scanb_so_ram_1;
wire scanb_so_ram_2;
wire scanb_so_ram_3;
assign scanb_si_ram_0 = scanb_si;
assign scanb_si_ram_1 = scanb_so_ram_0;
assign scanb_si_ram_2 = scanb_so_ram_1;
assign scanb_si_ram_3 = scanb_so_ram_2;
assign scanb_so = scanb_so_ram_3;
wire mbist_si_i_ram_0;
wire mbist_si_i_ram_1;
wire mbist_si_i_ram_2;
wire mbist_si_i_ram_3;
wire mbist_so_o_ram_0;
wire mbist_so_o_ram_1;
wire mbist_so_o_ram_2;
wire mbist_so_o_ram_3;
assign mbist_si_i_ram_0 = mbist_si_i;
assign mbist_si_i_ram_1 = mbist_so_o_ram_0;
assign mbist_si_i_ram_2 = mbist_so_o_ram_1;
assign mbist_si_i_ram_3 = mbist_so_o_ram_2;
assign mbist_so_o = mbist_so_o_ram_3;
`endif
 
`ifdef UNUSED
229,11 → 228,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si_ram_0),
.scanb_so(scanb_so_ram_0),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i_ram_0),
.mbist_so_o(mbist_so_o_ram_0),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
255,11 → 252,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si_ram_1),
.scanb_so(scanb_so_ram_1),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i_ram_1),
.mbist_so_o(mbist_so_o_ram_1),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
281,11 → 276,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si_ram_2),
.scanb_so(scanb_so_ram_2),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i_ram_2),
.mbist_so_o(mbist_so_o_ram_2),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
307,11 → 300,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si_ram_3),
.scanb_so(scanb_so_ram_3),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i_ram_3),
.mbist_so_o(mbist_so_o_ram_3),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
/trunk/or1200/rtl/verilog/or1200_dc_ram.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2003/08/26 09:37:02 simons
// Added support for rams with byte write access.
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
79,7 → 82,7
 
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
// Internal i/f
104,11 → 107,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
output mbist_so_o;
`endif
 
`ifdef OR1200_NO_DC
118,7 → 119,7
//
assign dataout = {dw{1'b0}};
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
assign mbist_so_o = mbist_si_i;
`endif
 
`else
134,11 → 135,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.clk(clk),
.rst(rst),
/trunk/or1200/rtl/verilog/or1200_spram_1024x32.v
63,6 → 63,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2003/08/19 16:41:23 simons
// Scan signals mess fixed.
//
// Revision 1.4 2003/08/11 13:32:19 simons
// BIST interface added for Artisan memory instances.
//
103,7 → 106,7
module or1200_spram_1024x32(
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
119,11 → 122,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
output mbist_so_o;
`endif
 
//
147,7 → 148,7
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
170,11 → 171,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
245,11 → 244,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
/trunk/or1200/rtl/verilog/or1200_spram_64x22.v
63,6 → 63,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2003/08/19 16:41:23 simons
// Scan signals mess fixed.
//
// Revision 1.4 2003/08/11 13:32:19 simons
// BIST interface added for Artisan memory instances.
//
103,7 → 106,7
module or1200_spram_64x22(
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
119,11 → 122,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
output mbist_so_o;
`endif
 
//
148,7 → 149,7
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
171,11 → 172,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
246,11 → 245,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
/trunk/or1200/rtl/verilog/or1200_immu_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.12 2003/06/06 02:54:47 lampret
// When OR1200_NO_IMMU and OR1200_NO_IC are not both defined or undefined at the same time, results in a IC bug. Fixed.
//
// Revision 1.11 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
119,7 → 122,7
 
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
// IC i/f
165,11 → 168,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
output mbist_so_o;
`endif
 
//
261,7 → 262,7
assign icpu_err_o = icimmu_err_i;
assign icimmu_ci_o = `OR1200_IMMU_CI;
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
assign mbist_so_o = mbist_si_i;
`endif
`else
 
394,11 → 395,9
 
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
 
// SPR access
/trunk/or1200/rtl/verilog/or1200_spram_64x24.v
63,6 → 63,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2003/08/19 16:41:23 simons
// Scan signals mess fixed.
//
// Revision 1.4 2003/08/11 13:32:19 simons
// BIST interface added for Artisan memory instances.
//
106,7 → 109,7
module or1200_spram_64x24(
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
122,11 → 125,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
output mbist_so_o;
`endif
 
//
151,7 → 152,7
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
174,11 → 175,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
249,11 → 248,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
/trunk/or1200/rtl/verilog/or1200_spram_2048x32.v
63,6 → 63,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2003/08/19 16:41:23 simons
// Scan signals mess fixed.
//
// Revision 1.5 2003/08/11 13:32:19 simons
// BIST interface added for Artisan memory instances.
//
70,7 → 73,7
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.3 2002/10/28 15:03:50 mohor
// Signal scanb_sen renamed to scanb_en.
// Signal mbist_sen renamed to mbist_ctrl_i.
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
106,7 → 109,7
module or1200_spram_2048x32(
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
122,11 → 125,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
output mbist_so_o;
`endif
 
//
150,7 → 151,7
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
174,11 → 175,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
249,11 → 248,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
/trunk/or1200/rtl/verilog/or1200_immu_tlb.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2002/10/28 16:34:32 mohor
// RAMs wrong connected to the BIST scan chain.
//
// Revision 1.5 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
88,7 → 91,7
 
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
// SPR access
123,11 → 126,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
output mbist_so_o;
`endif
 
//
240,9 → 241,9
 
 
`ifdef OR1200_BIST
assign itlb_mr_ram_si = scanb_si;
assign itlb_mr_ram_si = mbist_si_i;
assign itlb_tr_ram_si = itlb_mr_ram_so;
assign scanb_so = itlb_tr_ram_so;
assign mbist_so_o = itlb_tr_ram_so;
`endif
 
 
254,11 → 255,9
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(itlb_mr_ram_si),
.scanb_so(itlb_mr_ram_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(itlb_mr_ram_si),
.mbist_so_o(itlb_mr_ram_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.ce(tlb_mr_en),
.we(tlb_mr_we),
276,11 → 275,9
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(itlb_tr_ram_si),
.scanb_so(itlb_tr_ram_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(itlb_tr_ram_si),
.mbist_so_o(itlb_tr_ram_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.ce(tlb_tr_en),
.we(tlb_tr_we),
/trunk/or1200/rtl/verilog/or1200_dc_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.5 2002/08/18 19:54:47 lampret
// Added store buffer.
//
106,7 → 109,7
 
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
// SPRs
160,11 → 163,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
output mbist_so_o;
`endif
 
//
201,11 → 202,11
//
// RAM BIST
//
wire scanb_ram_so;
wire scanb_tag_so;
wire scanb_ram_si = scanb_si;
wire scanb_tag_si = scanb_ram_so;
assign scanb_so = scanb_tag_so;
wire mbist_ram_so;
wire mbist_tag_so;
wire mbist_ram_si = mbist_si_i;
wire mbist_tag_si = mbist_ram_so;
assign mbist_so_o = mbist_tag_so;
`endif
 
//
301,11 → 302,9
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_ram_si),
.scanb_so(scanb_ram_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_ram_si),
.mbist_so_o(mbist_ram_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.addr(dc_addr[`OR1200_DCINDXH:2]),
.en(dc_en),
322,11 → 321,9
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_tag_si),
.scanb_so(scanb_tag_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_tag_si),
.mbist_so_o(mbist_tag_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.addr(dctag_addr),
.en(dctag_en),
/trunk/or1200/rtl/verilog/or1200_spram_256x21.v
63,6 → 63,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2003/08/19 16:41:23 simons
// Scan signals mess fixed.
//
// Revision 1.4 2003/08/11 13:32:19 simons
// BIST interface added for Artisan memory instances.
//
109,7 → 112,7
module or1200_spram_256x21(
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
125,11 → 128,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
output mbist_so_o;
`endif
 
//
154,7 → 155,7
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
178,11 → 179,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
253,11 → 252,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
/trunk/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
63,7 → 63,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2003/08/27 08:38:36 simons
// Added support for rams with byte write access.
//
//
 
// synopsys translate_off
`include "timescale.v"
73,7 → 76,7
module or1200_spram_1024x32_bw(
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
83,11 → 86,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
output mbist_so_o;
`endif
 
//
111,7 → 112,7
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
135,11 → 136,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
200,19 → 199,19
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef OR1200_BIST
wire scanb_si_ram_0;
wire scanb_si_ram_1;
wire scanb_si_ram_2;
wire scanb_si_ram_3;
wire scanb_so_ram_0;
wire scanb_so_ram_1;
wire scanb_so_ram_2;
wire scanb_so_ram_3;
assign scanb_si_ram_0 = scanb_si;
assign scanb_si_ram_1 = scanb_so_ram_0;
assign scanb_si_ram_2 = scanb_so_ram_1;
assign scanb_si_ram_3 = scanb_so_ram_2;
assign scanb_so = scanb_so_ram_3;
wire mbist_si_i_ram_0;
wire mbist_si_i_ram_1;
wire mbist_si_i_ram_2;
wire mbist_si_i_ram_3;
wire mbist_so_o_ram_0;
wire mbist_so_o_ram_1;
wire mbist_so_o_ram_2;
wire mbist_so_o_ram_3;
assign mbist_si_i_ram_0 = mbist_si_i;
assign mbist_si_i_ram_1 = mbist_so_o_ram_0;
assign mbist_si_i_ram_2 = mbist_so_o_ram_1;
assign mbist_si_i_ram_3 = mbist_so_o_ram_2;
assign mbist_so_o = mbist_so_o_ram_3;
`endif
 
`ifdef UNUSED
226,11 → 225,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si_ram_0),
.scanb_so(scanb_so_ram_0),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i_ram_0),
.mbist_so_o(mbist_so_o_ram_0),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
252,11 → 249,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si_ram_1),
.scanb_so(scanb_so_ram_1),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i_ram_1),
.mbist_so_o(mbist_so_o_ram_1),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
278,11 → 273,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si_ram_2),
.scanb_so(scanb_so_ram_2),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i_ram_2),
.mbist_so_o(mbist_so_o_ram_2),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
304,11 → 297,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si_ram_3),
.scanb_so(scanb_so_ram_3),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i_ram_3),
.mbist_so_o(mbist_so_o_ram_3),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
/trunk/or1200/rtl/verilog/or1200_spram_2048x8.v
63,6 → 63,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2003/08/19 16:41:23 simons
// Scan signals mess fixed.
//
// Revision 1.4 2003/08/11 13:32:19 simons
// BIST interface added for Artisan memory instances.
//
103,7 → 106,7
module or1200_spram_2048x8(
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
119,11 → 122,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
output mbist_so_o;
`endif
 
//
147,7 → 148,7
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
171,11 → 172,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
246,11 → 245,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
/trunk/or1200/rtl/verilog/or1200_dmmu_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.6 2002/03/29 15:16:55 lampret
// Some of the warnings fixed.
//
104,7 → 107,7
 
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
// DC i/f
149,11 → 152,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
output mbist_so_o;
`endif
 
//
211,7 → 212,7
assign dcpu_err_o = dcdmmu_err_i;
assign dcdmmu_ci_o = `OR1200_DMMU_CI;
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
assign mbist_so_o = mbist_si_i;
`endif
 
`else
324,11 → 325,9
 
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
 
// SPR access
/trunk/or1200/rtl/verilog/or1200_ic_tag.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2002/10/24 22:19:04 mohor
// Signal mbist_ctrl_ii renamed to mbist_ctrl_i
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
78,7 → 81,7
 
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
// Internal i/f
102,11 → 105,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
output mbist_so_o;
`endif
 
//
127,7 → 128,7
assign tag = {dw-1{1'b0}};
assign tag_v = 1'b0;
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
assign mbist_so_o = mbist_si_i;
`endif
 
`else
143,11 → 144,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.clk(clk),
.rst(rst),
/trunk/or1200/rtl/verilog/or1200_spram_64x14.v
63,6 → 63,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2003/08/19 16:41:23 simons
// Scan signals mess fixed.
//
// Revision 1.4 2003/08/11 13:32:19 simons
// BIST interface added for Artisan memory instances.
//
103,7 → 106,7
module or1200_spram_64x14(
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
119,11 → 122,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
output mbist_so_o;
`endif
 
//
148,7 → 149,7
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
171,11 → 172,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
246,11 → 245,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
/trunk/or1200/rtl/verilog/or1200_ic_ram.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
78,7 → 81,7
 
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
// Internal i/f
103,11 → 106,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
output mbist_so_o;
`endif
 
`ifdef OR1200_NO_IC
117,7 → 118,7
//
assign dataout = {dw{1'b0}};
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
assign mbist_so_o = mbist_si_i;
`endif
 
`else
133,11 → 134,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.clk(clk),
.rst(rst),
/trunk/or1200/rtl/verilog/or1200_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.10 2002/12/08 08:57:56 lampret
// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
//
// Revision 1.9 2002/10/17 20:04:41 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
137,7 → 140,7
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Power Management
pm_cpustall_i,
226,11 → 229,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
output mbist_so_o;
`endif
 
//
405,15 → 406,15
//
// RAM BIST
//
wire scanb_immu_so;
wire scanb_ic_so;
wire scanb_dmmu_so;
wire scanb_dc_so;
wire scanb_immu_si = scanb_si;
wire scanb_ic_si = scanb_immu_so;
wire scanb_dmmu_si = scanb_ic_so;
wire scanb_dc_si = scanb_dmmu_so;
assign scanb_so = scanb_dc_so;
wire mbist_immu_so;
wire mbist_ic_so;
wire mbist_dmmu_so;
wire mbist_dc_so;
wire mbist_immu_si = mbist_si_i;
wire mbist_ic_si = mbist_immu_so;
wire mbist_dmmu_si = mbist_ic_so;
wire mbist_dc_si = mbist_dmmu_so;
assign mbist_so_o = mbist_dc_so;
`endif
 
 
513,11 → 514,9
 
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_immu_si),
.scanb_so(scanb_immu_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_immu_si),
.mbist_so_o(mbist_immu_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
 
// CPU i/f
556,11 → 555,9
 
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_ic_si),
.scanb_so(scanb_ic_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_ic_si),
.mbist_so_o(mbist_ic_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
 
// IC and CPU/IMMU
678,11 → 675,9
 
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_dmmu_si),
.scanb_so(scanb_dmmu_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_dmmu_si),
.mbist_so_o(mbist_dmmu_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
 
// CPU i/f
719,11 → 714,9
 
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_dc_si),
.scanb_so(scanb_dc_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_dc_si),
.mbist_so_o(mbist_dc_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
 
// DC and CPU/DMMU
/trunk/or1200/rtl/verilog/or1200_dmmu_tlb.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.3 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
82,7 → 85,7
 
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
// SPR access
119,11 → 122,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
output mbist_so_o;
`endif
 
//
153,11 → 154,11
//
// RAM BIST
//
wire scanb_mr_so;
wire scanb_tr_so;
wire scanb_mr_si = scanb_si;
wire scanb_tr_si = scanb_mr_so;
assign scanb_so = scanb_tr_so;
wire mbist_mr_so;
wire mbist_tr_so;
wire mbist_mr_si = mbist_si_i;
wire mbist_tr_si = mbist_mr_so;
assign mbist_so_o = mbist_tr_so;
`endif
 
//
246,11 → 247,9
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_mr_si),
.scanb_so(scanb_mr_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_mr_si),
.mbist_so_o(mbist_mr_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.ce(tlb_mr_en),
.we(tlb_mr_we),
268,11 → 267,9
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_tr_si),
.scanb_so(scanb_tr_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_tr_si),
.mbist_so_o(mbist_tr_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.ce(tlb_tr_en),
.we(tlb_tr_we),
/trunk/or1200/rtl/verilog/or1200_spram_512x20.v
63,6 → 63,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2003/08/19 16:41:23 simons
// Scan signals mess fixed.
//
// Revision 1.4 2003/08/11 13:32:19 simons
// BIST interface added for Artisan memory instances.
//
109,7 → 112,7
module or1200_spram_512x20(
`ifdef OR1200_BIST
// RAM BIST
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
125,11 → 128,9
//
// RAM BIST
//
input scanb_rst,
scanb_si,
scanb_en,
scanb_clk;
output scanb_so;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
output mbist_so_o;
`endif
 
//
154,7 → 155,7
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign scanb_so = scanb_si;
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
178,11 → 179,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
253,11 → 252,9
`endif
`ifdef OR1200_BIST
// RAM BIST
.scanb_rst(scanb_rst),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en),
.scanb_clk(scanb_clk),
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),

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