URL
https://opencores.org/ocsvn/alternascope/alternascope/trunk
Subversion Repositories alternascope
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 12 to Rev 13
- ↔ Reverse comparison
Rev 12 → Rev 13
/tags/rels3/AdcDriver/d_Driver_RamBuffer.v
0,0 → 1,207
//================================================================== |
// File: d_Driver_RamBuffer.v |
// Version: 0.01 |
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
// Copyright Stephen Pickett |
// April 28, 2005 |
//------------------------------------------------------------------ |
// Revisions: |
// Ver 0.01 Apr 28, 2005 Initial Release |
// |
//================================================================== |
|
module ADCDataBuffer( |
CLK_64MHZ, MASTER_RST, |
CLK180_64MHZ, |
TIME_BASE, |
RAM_ADDR, RAM_DATA, RAM_CLK, |
ADC_DATA, ADC_CLK, |
TRIG_ADDR, |
VGA_WRITE_DONE, |
TRIGGER_LEVEL |
); |
|
//==================================================================// |
// PARAMETER DEFINITIONS // |
//==================================================================// |
parameter ss_wait_for_trig = 2'b00; |
parameter ss_fill_mem_half = 2'b01; |
parameter ss_write_buffer = 2'b11; |
parameter ss_invalid = 2'b10; |
parameter P_trigger_level = 8'h80; |
|
|
|
|
//==================================================================// |
// VARIABLE DEFINITIONS // |
//==================================================================// |
|
//----------------------// |
// INPUTS / OUTPUTS // |
//----------------------// |
input CLK_64MHZ; |
input CLK180_64MHZ; |
input MASTER_RST; // Global Asyncronous Reset |
input[5:0] TIME_BASE; // The selected V/Div |
input[10:0] RAM_ADDR; |
output[7:0] RAM_DATA; |
input RAM_CLK; |
input[7:0] ADC_DATA; |
output ADC_CLK; |
output[10:0] TRIG_ADDR; |
input VGA_WRITE_DONE; |
input[8:0] TRIGGER_LEVEL; |
|
//----------------------// |
// WIRES / NODES // |
//----------------------// |
wire CLK_64MHZ, MASTER_RST, CLK180_64MHZ; |
wire[5:0] TIME_BASE; |
wire[10:0] RAM_ADDR; |
wire[7:0] RAM_DATA; |
wire RAM_CLK; |
wire[7:0] ADC_DATA; |
wire ADC_CLK; |
reg[10:0] TRIG_ADDR; |
wire VGA_WRITE_DONE; |
wire[8:0] TRIGGER_LEVEL; |
|
//----------------------// |
// VARIABLES // |
//----------------------// |
|
|
|
//==================================================================// |
// 'SUB-ROUTINES' // |
//==================================================================// |
|
//------------------------------------------------------------------// |
// Instanstiate the ADC // |
//------------------------------------------------------------------// |
wire[7:0] DATA_FROM_ADC; |
Driver_ADC ADC( |
.CLK_64MHZ(CLK_64MHZ), |
.MASTER_RST(MASTER_RST), |
.TIME_BASE(TIME_BASE), |
.ADC_CLK(ADC_CLK), |
.ADC_DATA(ADC_DATA), |
.DATA_OUT(DATA_FROM_ADC) |
); |
|
//------------------------------------------------------------------// |
// Initialize the RAMs WE WILL NEED MORE! // |
// RAM is structured as follows: // |
// Dual-Access RAM // |
// 18kBits -> 2048Bytes + 1Parity/Byte // |
// Access A: 8bit + 1parity (ADC_Write) // |
// Access B: 8bit + 1parity (Read) // |
//------------------------------------------------------------------// |
reg[10:0] ADDRA; |
wire VCC, GND; |
assign VCC = 1'b1; |
assign GND = 1'b0; |
|
RAMB16_S9_S9 ADC_QuasiFifo_Buffer( |
.DOA(), .DOB(RAM_DATA), |
.DOPA(), .DOPB(), |
.ADDRA(ADDRA), .ADDRB(RAM_ADDR), |
.CLKA(CLK180_64MHZ), .CLKB(RAM_CLK), |
.DIA(DATA_FROM_ADC), .DIB(8'b0), |
.DIPA(GND), .DIPB(GND), |
.ENA(VCC), .ENB(VCC), |
.WEA(VCC), .WEB(GND), |
.SSRA(GND), .SSRB(GND) |
); |
|
//==================================================================// |
// FUNCTIONAL DEFINITIONS // |
//==================================================================// |
|
reg[1:0] sm_trig; |
reg trigger_detected; |
reg[9:0] cnt_1024bytes; |
reg mem_half_full; |
|
/* THE RAM WRITING TRIGGERING STATE MACHINE */ |
always @ (posedge CLK_64MHZ or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) |
sm_trig <= ss_wait_for_trig; |
else if(sm_trig == ss_wait_for_trig && trigger_detected == 1'b1) |
sm_trig <= ss_fill_mem_half; |
else if(sm_trig == ss_fill_mem_half && mem_half_full == 1'b1) |
sm_trig <= ss_write_buffer; |
else if(sm_trig == ss_write_buffer && trigger_detected == 1'b0 && VGA_WRITE_DONE == 1'b1) |
sm_trig <= ss_wait_for_trig; |
else if(sm_trig == ss_invalid) |
sm_trig <= ss_wait_for_trig; |
else |
sm_trig <= sm_trig; |
end |
|
|
/* THIS PART DEALS WITH THE ADDRESS OF THE ADC BUFFER */ |
/* Write in a Circular Buffer soft of way */ |
always @ (posedge ADC_CLK or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) begin |
ADDRA <= 11'b0; |
end else if(sm_trig == ss_wait_for_trig || sm_trig == ss_fill_mem_half) |
ADDRA <= ADDRA + 1; |
else |
ADDRA <= ADDRA; |
end |
|
/* LATCHING THE TRIGGER */ |
always @ (ADC_DATA) begin |
// if(ADC_DATA >= P_trigger_level) |
if(ADC_DATA >= TRIGGER_LEVEL) |
trigger_detected = 1'b1; |
else |
trigger_detected = 1'b0; |
end |
|
/* GATHERING 1024 MORE BYTES OF MEMORY */ |
always @ (posedge ADC_CLK or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) |
cnt_1024bytes <= 10'b0; |
else if(sm_trig == ss_fill_mem_half) |
cnt_1024bytes <= cnt_1024bytes + 1; |
else |
cnt_1024bytes <= cnt_1024bytes; |
end |
|
always @ (cnt_1024bytes) begin |
if(cnt_1024bytes == 10'h3FF) |
mem_half_full = 1'b1; |
else |
mem_half_full = 1'b0; |
end |
|
/* STORING THE TRIGGER ADDRESS */ |
always @ (posedge trigger_detected or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) |
TRIG_ADDR <= 11'd0; |
else |
TRIG_ADDR <= ADDRA; |
end |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
endmodule |
/tags/rels3/AdcDriver/d_DCM.xaw
0,0 → 1,3
XILINX-XDB 0.1 STUB 0.1 ASCII |
XILINX-XDM V1.2e |
$9ax4>7<8=1;"=7>;0685+5302;=+eM?813867=58;199?5<2695*6(7;`=0M_MGWHX23>GU_SUDBAWPC@Q@EAOIOVIGG<64ASUY[JHKQVIGGD@PEYVFVKGK9k1J^ZTPOONZ[AEJWZ]BXNFFNF]@HN773HX\VRAALX]G@WYD88:0M_YU_NLO]ZBCZVI:=<5NRVX\KKJ^WMNYSNBD179BVR\XGGFRSIJ]_GNJTCJHX8?0M_YU_NLO]Z@EWLR_I_@NL008EWQ]WFDGURGASU]MQHc<I[]QSB@CY^RNGA703HX\VRAALX]QAFIIN@MT\D@\149BVR\XGGFRS_K\EU]OKBOD911J^ZTPOONZ[SGKAMUOJ^QBOEGb?DUTGJU\EYF>3:CT^ZEKCK_M=RLCKOCNA43<I^PTOAEMUG3\MZUNOGKFI<;4AVX\GIME]O;TCR]FGOCNAc=F_SUH@FLZFU[SA4b<I^PTOAEBUY]J5f=F_SUM@BY[YQG;?DQ]WYKYXi5NW[]P]KRO\FEG86L@TI68FP@@:01H6QA|c]ZjhlhTMxbzh||\@f`@woqm{VoSIMB.yct0>EKC9<0OAE>81a8GIM609U=8@FU6:AOO717=2IGG?V7;BNH6]7?8<1H@F7?5:AOOAPd3JF@H[QKIWKGA0=DDBLI96MCKGZ;?FJLNQ;3<n5LLJD[5=6XJ\L:>6MCKGZ2<5YE]OMTEC][9:AOOC^XJ\Lm7NBDFY]AQCAXAGY_o6MCKGZ\@LPNLLo0OAEIX^OVHQOWDP?0OAEFN038GIMNFVNBZDJJ_C[\6g=DDBCESDLZFF33?FJLAGUBNXHH_HLPPc=DDBCESDLZFF]LQQ><KEABBRGAc:AOOLHXXLXBCIk4CMIJJZUUKV^R\H?=;BNHKPRXXAKXIR]GIGV:?FJLW?>FDWm4CMI\B@CCJHI@j6MCK^MVPUSSW]S[I45LOLOJPQCC?2IYILZJD29GGH><LJGTEC][d:FFWNCPWHNAY^Z>2:FEWZ@UMX_NBNWPMNFF57=CDEUM^H_ZEOAZ[HICM<1O_^KA149GQQ_XKPIGIRM@RSG@PLII?2NTZLBZE99F\QCUFHFj7KOLTNPZ[O@23OKG_H74FC]PKPTDM01MECQZNHVPe>@H]]U^BDZ\a:DLQQYQIE_N>6HW1:K6?LDRNN;:7GG[TDP\MKVR\V^R\Hm4JHVWAWYWC;Z@o6DFTUGQ[SGK]L<0@BOKEEa8HJEFD[E^XD@H6:NLGNCCi2FDOFKK_NWW7>JH_k1GCZ]DEVNJJ@5<EAPi7@QNNE]G[VRU?2GTZLBZE69MAQQHZB>0BB@J1:M;?J@CL[I[Io5_H@QF[VNNN]30\D@GAR@VWd=WAGCXKCJJD99SMKQNL]B37]\FMU[SA46<X[E[S]GAIRC@PLPB=2ZXOAE9;QQGKKC33YYNB55_SHL@@@E43[Y_:6\\T^KMf>UNOLR_I_@NL79PMKAKMj1XXL\[UQ]TELR13Z^JXX]>2:QZWQCJWZSEOE\@NNWP7>RHX=1_^XKi;TQFHJEFD[E^XD@Hf:WPAIIP[BO\@D@JS99VW@YE]OM37X]J_FPJ@0=QAL]:n6VNW^TFVVOHF8n0TDBFNY/[@G&7&8*XXXL/0/3#EVENA:1S_Y84Xe`\Ma773QnfS@oeosTfvvohf8:0TicPMhllvScu{`ee96U?:1_6?^6=?T>0myu3:f`ig=qm{ybcc.>.168rmbkm2rh?~<?0,6ep731uIJ{?:5O@y07>C<?28qX89477;::>456n;>j6?m934ym<6<63g2?6?5+838;4>{T<:03;766:012b72f2;i2oo5\5`8;3?>>289:j?:m:9353>U3;32<6575123e61d=08ih7^;n:959<<<6;8l98o4746;8W15=0>0357?<1g07f?>30?1X9l477;::>456n;>i6n6>a:Q77?>02131=>?i25`9g=be3m2<6=4>:0yP01<??3226<=>f36b>7e1;<1}X:k50;395??|[=>14:479;305c43i38h:>;4b6:94?6=:33p(o478:&2b?>f3-8;65l4$339<4=#?o0j7o:9:1827?6=8r.=n7::;%a96f=#l3=?7)k5249'b?423-;;6?84$03960=#9;0=:6*>3;57?!732:1/=8494:&23?2a3-;36?<4$53921=#:m0=7)=::99'73<>3-9369h4$2f93>"4m3>o7)=i:768 11=?>1/8n47;%6;>0c<,=319h5+4c84=>"3m3?0(8>5659'14<182.>>78?;%70>5=#=>0==6*92;;8 31=92.<97:i;%5`>2b<,8<18k5+43860>"21380(8654:k03?6=,?k1485+6b84=>"6l3?=76g=e;29 3g=0<1/:4489:9j34<72-<j65;4$7a93<=<a?l1<7*9a;:6?!0>2>307d9?:18'2d<?=2.=5796;:k5`?6=,?k1485+6884=>=n<h0;6)8n:978 3?=?01/:n489:9l60<72-<j65;4;n0a>5<#>h03965`2783>!0f21?07b<7:18'2d<?=21d>n4?:%4b>=3<3f826=4+6`8;1>=h:h0;6)8n:978?j4a290/:l475:&5g?1>3-;n6=5+1e86b>"6k3>;76a<0;29 3g=0<1/:n489:&2a?6<,8n19k5+1b813>=h??0;6)8n:948 3>=?010c8m50;&5e?>23-<h6:74;n4f>5<#>h03965rb2c94?4=83:p(;l5579j10<72-<j65;4$7a93<=#9k08o65`6483>!0f21?0(;m5789'5f<4121v>750;0x910=;>16?l495:&2=?5e3ty<>7>51z?72?163-=868;4}r10>5<6s4>=6?h4$6c94>"613>;7)9m:19~w67=83;p1985319'3d<73-;26?94$6`94>{t=m0;6<u24786g>"0;3<>7p}<c;295~;4i3?>7)9<:478yv27290;w)9<:778yv40290;w)9<:778yv5e290;w)9<:778yxh5=3:1=vsa2783>4}zf;=1<7?t}o0;>5<6std957>51zm6d<728qvb?l50;3xyk4d290:wp`=d;295~{zutJKOv=8:0227=7dntJKNv>r@ARxyEF |
/tags/rels3/AdcDriver/d_Driver_ADC.v
0,0 → 1,197
//================================================================== |
// File: d_Driver_ADC.v |
// Version: 0.01 |
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
// Copyright Stephen Pickett |
// April 28, 2005 |
//------------------------------------------------------------------ |
// Revisions: |
// Ver 0.01 Apr 28, 2005 Initial Release |
// |
//================================================================== |
|
module Driver_ADC( |
CLK_64MHZ, MASTER_RST, |
TIME_BASE, |
ADC_CLK, ADC_DATA, |
DATA_OUT |
); |
|
//==================================================================// |
// DEFINITIONS // |
//==================================================================// |
parameter US1 = 5'd0; |
parameter US2 = 5'd1; |
parameter US4 = 5'd2; |
parameter US8 = 5'd3; |
parameter US16 = 5'd4; |
parameter US32 = 5'd5; |
parameter US64 = 5'd6; |
parameter US128 = 5'd7; |
parameter US512 = 5'd8; |
parameter US1024 = 5'd9; |
parameter US2048 = 5'd10; |
parameter US4096 = 5'd11; |
parameter US8192 = 5'd12; |
parameter US16384 = 5'd13; |
parameter US32768 = 5'd14; |
parameter US65536 = 5'd15; |
parameter US131072 = 5'd16; |
parameter US262144 = 5'd17; |
parameter US524288 = 5'd18; |
parameter US1048576 = 5'd19; |
parameter US2097152 = 5'd20; |
parameter US4194304 = 5'd21; |
parameter US8388608 = 5'd22; |
|
|
//==================================================================// |
// VARIABLE DEFINITIONS // |
//==================================================================// |
|
//----------------------// |
// INPUTS / OUTPUTS // |
//----------------------// |
input CLK_64MHZ; // Global System Clock |
input MASTER_RST; // Global Asyncronous Reset |
input[5:0] TIME_BASE; // The selected V/Div |
input[7:0] ADC_DATA; // Data recieved from ADC |
output ADC_CLK; // Clock out to the ADC |
output[7:0] DATA_OUT; // Data output (essentially buffered from ADC by one clk) |
|
//----------------------// |
// WIRES / NODES // |
//----------------------// |
wire CLK_64MHZ, MASTER_RST; |
wire[5:0] TIME_BASE; |
wire[7:0] ADC_DATA; |
reg ADC_CLK; |
wire [7:0] DATA_OUT; |
|
//----------------------// |
// VARIABLES // |
//----------------------// |
|
|
|
|
//==================================================================// |
// FUNCTIONAL DEFINITIONS // |
//==================================================================// |
|
|
|
//------------------------------------------------------------------// |
// CLOCK GENERATION AND SELECTION // |
//------------------------------------------------------------------// |
reg[15:0] Counter_CLK; |
wire CLK_32MHZ, CLK_16MHZ, CLK_8MHZ, CLK_4MHZ, CLK_2MHZ, CLK_1MHZ, CLK_500KHZ, CLK_250KHZ, CLK_125KHZ, |
CLK_62KHZ, CLK_31KHZ, CLK_16KHZ, CLK_8KHZ, CLK_4KHZ, CLK_2KHZ, CLK_1KHZ; |
|
always @ (posedge CLK_64MHZ or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) begin |
Counter_CLK <= 16'b0; |
end else begin |
Counter_CLK <= Counter_CLK + 1; |
end |
end |
|
assign CLK_32MHZ = Counter_CLK[0]; |
assign CLK_16MHZ = Counter_CLK[1]; |
assign CLK_8MHZ = Counter_CLK[2]; |
assign CLK_4MHZ = Counter_CLK[3]; |
assign CLK_2MHZ = Counter_CLK[4]; |
assign CLK_1MHZ = Counter_CLK[5]; |
assign CLK_500KHZ = Counter_CLK[6]; |
assign CLK_250KHZ = Counter_CLK[7]; |
assign CLK_125KHZ = Counter_CLK[8]; |
assign CLK_62KHZ = Counter_CLK[9]; |
assign CLK_31KHZ = Counter_CLK[10]; |
assign CLK_16KHZ = Counter_CLK[11]; |
assign CLK_8KHZ = Counter_CLK[12]; |
assign CLK_4KHZ = Counter_CLK[13]; |
assign CLK_2KHZ = Counter_CLK[14]; |
assign CLK_1KHZ = Counter_CLK[15]; |
//assign CLK_500HZ = Counter_CLK[16]; |
|
|
always @ (TIME_BASE or MASTER_RST or CLK_64MHZ or CLK_32MHZ or CLK_16MHZ or |
CLK_8MHZ or CLK_4MHZ or CLK_2MHZ or CLK_1MHZ or CLK_500KHZ or CLK_250KHZ or |
CLK_125KHZ or CLK_62KHZ or CLK_31KHZ or CLK_16KHZ or CLK_8KHZ or CLK_4KHZ or |
CLK_2KHZ or CLK_1KHZ) begin |
if(MASTER_RST == 1'b1) begin |
ADC_CLK = 1'b0; |
end else if(TIME_BASE == 6'd0) begin // 1us/Div, 1samp/pxl |
ADC_CLK = CLK_64MHZ; |
end else if(TIME_BASE == 6'd1) begin // 2us/Div, 2samp/pxl |
ADC_CLK = CLK_64MHZ; |
end else if(TIME_BASE == 6'd2) begin // 4us/Div, 2samp/pxl |
ADC_CLK = CLK_32MHZ; |
end else if(TIME_BASE == 6'd3) begin // 8us/Div, 2samp/pxl |
ADC_CLK = CLK_16MHZ; |
end else if(TIME_BASE == 6'd4) begin // 16us/Div, 2samp/pxl |
ADC_CLK = CLK_8MHZ; |
end else if(TIME_BASE == 6'd5) begin // 32us/Div, 2samp/pxl |
ADC_CLK = CLK_4MHZ; |
end else if(TIME_BASE == 6'd6) begin // 64us/Div, 2samp/pxl |
ADC_CLK = CLK_2MHZ; |
end else if(TIME_BASE == 6'd7) begin // 128us/Div, 2samp/pxl |
ADC_CLK = CLK_1MHZ; |
end else if(TIME_BASE == 6'd8) begin // 256us/Div, 2samp/pxl |
ADC_CLK = CLK_500KHZ; |
end else if(TIME_BASE == 6'd9) begin // 512us/Div, 2samp/pxl |
ADC_CLK = CLK_250KHZ; |
end else if(TIME_BASE == 6'd10) begin // ... |
ADC_CLK = CLK_125KHZ; |
end else if(TIME_BASE == 6'd11) begin |
ADC_CLK = CLK_62KHZ; |
end else if(TIME_BASE == 6'd12) begin |
ADC_CLK = CLK_31KHZ; |
end else if(TIME_BASE == 6'd13) begin |
ADC_CLK = CLK_16KHZ; |
end else if(TIME_BASE == 6'd14) begin |
ADC_CLK = CLK_8KHZ; |
end else if(TIME_BASE == 6'd15) begin |
ADC_CLK = CLK_4KHZ; |
end else if(TIME_BASE == 6'd16) begin |
ADC_CLK = CLK_2KHZ; |
end else if(TIME_BASE == 6'd17) begin |
ADC_CLK = CLK_1KHZ; |
// end else if(TIME_BASE == 6'd18) begin |
// ADC_CLK = CLK_500HZ; |
/* |
end else if(TIME_BASE == 6'd19) begin |
ADC_CLK = CLK_US524288; |
end else if(TIME_BASE == 6'd20) begin |
ADC_CLK = CLK_US1048576; |
end else if(TIME_BASE == 6'd21) begin |
ADC_CLK = CLK_US2097152; |
end else if(TIME_BASE == 6'd22) begin |
ADC_CLK = CLK_US4194304; |
end else if(TIME_BASE == 6'd23) begin |
ADC_CLK = CLK_US8388608; |
*/ |
end else begin |
ADC_CLK = 1'b0; |
end |
end |
|
//------------------------------------------------------------------// |
// ADC DATA READING // |
//------------------------------------------------------------------// |
/* |
always @ (negedge ADC_CLK or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) begin |
DATA_OUT <= 8'b0; |
end else begin |
DATA_OUT <= ADC_DATA; |
end |
end |
*/ |
|
assign DATA_OUT = ADC_DATA; |
|
endmodule |
|
|
|
/tags/rels3/Mouse/.#d_DriverMouse.v.1.1
0,0 → 1,359
//================================================================== |
// File: d_MouseDriver.v |
// Version: 0.01 |
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
// Copyright Stephen Pickett |
// April 28, 2005 |
//------------------------------------------------------------------ |
// Revisions: |
// Ver 0.01 Apr 28, 2005 Initial Release |
// |
//================================================================== |
|
module Driver_mouse( |
CLK_50MHZ, MASTER_RST, |
PS2C, PS2D, |
XCOORD, YCOORD, |
L_BUTTON, R_BUTTON, M_BUTTON |
); |
|
//==================================================================// |
// DEFINITIONS // |
//==================================================================// |
parameter ss_CLK_LOW_100US = 4'b0000; |
parameter ss_DATA_LOW = 4'b0001; |
parameter ss_SET_BIT_0 = 4'b0011; |
parameter ss_SET_BIT_1 = 4'b0010; |
parameter ss_SET_BIT_2 = 4'b0110; |
parameter ss_SET_BIT_3 = 4'b0111; |
parameter ss_SET_BIT_4 = 4'b0101; |
parameter ss_SET_BIT_5 = 4'b0100; |
parameter ss_SET_BIT_6 = 4'b1100; |
parameter ss_SET_BIT_7 = 4'b1101; |
parameter ss_SET_BIT_PARITY = 4'b1111; |
parameter ss_SET_BIT_STOP = 4'b1110; |
parameter ss_WAIT_BIT_ACK = 4'b1010; |
parameter ss_GET_MOVEMENT = 4'b1000; |
|
parameter P_Lbut_index = 1; |
parameter P_Mbut_index = 2; |
parameter P_Rbut_index = 3; |
|
|
//==================================================================// |
// VARIABLE DEFINITIONS // |
//==================================================================// |
//----------------------// |
// INPUTS // |
//----------------------// |
input CLK_50MHZ; // System wide clock |
input MASTER_RST; // System wide reset |
inout PS2C; // PS2 clock |
inout PS2D; // PS2 data |
|
//----------------------// |
// OUTPUTS // |
//----------------------// |
output[11:0] XCOORD; // X coordinate of the cursor |
output[11:0] YCOORD; // Y coordinate of the cursor |
output L_BUTTON, R_BUTTON, M_BUTTON; |
|
//----------------------// |
// WIRES / NODES // |
//----------------------// |
wire CLK_50MHZ, MASTER_RST; |
wire PS2C, PS2D; |
reg[11:0] XCOORD; |
reg[11:0] YCOORD; |
reg L_BUTTON, R_BUTTON, M_BUTTON; |
|
//----------------------// |
// REGISTERS // |
//----------------------// |
reg[12:0] Counter_timer; |
reg[5:0] Counter_bits; |
reg[3:0] sm_ps2mouse; |
reg[32:0] data_in_buf; |
|
|
|
|
//==================================================================// |
// FUNCTIONAL DEFINITIONS // |
//==================================================================// |
|
//------------------------------------------------------------------// |
// INTERMEDIATE VALUES // |
//------------------------------------------------------------------// |
reg[7:0] Counter_PS2C; |
reg CLK_ps2c_debounced; |
|
// Debounce the PS2C line. |
// The mouse is generally not outputting a nice rising clock edge. |
// To eliminate the false edge detection, make sure it is high/low |
// for at least 256 counts before triggering the CLK. |
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) begin |
Counter_PS2C <= 8'b0; |
end else begin |
if(PS2C == 1'b1) begin |
if(Counter_PS2C == 8'hFF) |
Counter_PS2C <= Counter_PS2C; |
else |
Counter_PS2C <= Counter_PS2C + 1; |
end else begin |
if(Counter_PS2C == 8'b0) |
Counter_PS2C <= Counter_PS2C; |
else |
Counter_PS2C <= Counter_PS2C - 1; |
end |
end |
end |
|
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) |
CLK_ps2c_debounced <= 1'b0; |
else if(Counter_PS2C == 8'b0) |
CLK_ps2c_debounced <= 1'b0; |
else if(Counter_PS2C == 8'hFF) |
CLK_ps2c_debounced <= 1'b1; |
else |
CLK_ps2c_debounced <= CLK_ps2c_debounced; |
end |
|
|
//------------------------------------------------------------------// |
// INTERPRETING MOVEMENTS // |
//------------------------------------------------------------------// |
reg[7:0] xcoord_buf; |
reg[7:0] ycoord_buf; |
|
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) begin |
xcoord_buf <= 8'b0; |
end else if(data_in_buf[5] == 1'b0) begin |
xcoord_buf <= data_in_buf[19:12]; |
end else begin |
xcoord_buf <= ((~(data_in_buf[19:12]))+1); |
end |
end |
|
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) begin |
ycoord_buf <= 8'b0; |
end else if(data_in_buf[6] == 1'b0) begin |
ycoord_buf <= data_in_buf[30:23]; |
end else begin |
ycoord_buf <= ((~(data_in_buf[30:23]))+1); |
end |
end |
|
|
always @ (posedge CLK_ps2c_debounced or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) begin |
XCOORD <= 12'd320; |
end else if(Counter_bits == 6'd32 && (data_in_buf[7] == 1'b0)) begin |
if(data_in_buf[5] == 1'b1) begin // NEGITIVE |
if(XCOORD <= xcoord_buf) |
XCOORD <= 12'b0; |
else |
XCOORD <= XCOORD - xcoord_buf; |
end else begin // POSITIVE |
if((XCOORD + xcoord_buf) >= 11'd639) |
XCOORD <= 12'd639; |
else |
XCOORD <= XCOORD + xcoord_buf; |
end |
end else begin |
XCOORD <= XCOORD; |
end |
end |
|
always @ (posedge CLK_ps2c_debounced or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) begin |
YCOORD <= 12'd100; |
end else if(Counter_bits == 6'd32 && (data_in_buf[8] == 1'b0)) begin |
if(data_in_buf[6] == 1'b1) begin // POSITIVE |
if((YCOORD + ycoord_buf) >= 11'd479) |
YCOORD <= 12'd479; |
else |
YCOORD <= YCOORD + ycoord_buf; |
end else begin // POSITIVE |
if(YCOORD <= ycoord_buf) |
YCOORD <= 12'd0; |
else |
YCOORD <= YCOORD - ycoord_buf; |
end |
end else begin |
YCOORD <= YCOORD; |
end |
end |
|
//------------------------------------------------------------------// |
// INTERPRETING BUTTONS // |
//------------------------------------------------------------------// |
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) begin |
L_BUTTON <= 1'b0; |
M_BUTTON <= 1'b0; |
R_BUTTON <= 1'b0; |
end else if(Counter_bits == 6'd32) begin |
L_BUTTON <= data_in_buf[P_Lbut_index]; |
M_BUTTON <= data_in_buf[P_Mbut_index]; |
R_BUTTON <= data_in_buf[P_Rbut_index]; |
end else begin |
L_BUTTON <= L_BUTTON; |
M_BUTTON <= M_BUTTON; |
R_BUTTON <= R_BUTTON; |
end |
end |
|
|
|
|
//------------------------------------------------------------------// |
// SENDING DATA // |
//------------------------------------------------------------------// |
reg PS2C_out, PS2D_out; |
|
assign PS2C = PS2C_out; |
assign PS2D = PS2D_out; |
|
|
always @ (Counter_timer or MASTER_RST) begin |
if(MASTER_RST == 1'b1) begin |
PS2C_out = 1'bZ; |
end else if((Counter_timer <= 13'd5500) && (MASTER_RST == 1'b0)) |
PS2C_out = 1'b0; |
else |
PS2C_out = 1'bZ; |
end |
|
always @ (sm_ps2mouse or Counter_timer or MASTER_RST) begin |
if(MASTER_RST == 1'b1) begin |
PS2D_out = 1'bZ; |
end else if(Counter_timer >= 13'd5000 && sm_ps2mouse == ss_DATA_LOW) begin |
PS2D_out = 1'b0; |
end else if(sm_ps2mouse == ss_SET_BIT_0) begin |
PS2D_out = 1'b0; |
end else if(sm_ps2mouse == ss_SET_BIT_1) begin |
PS2D_out = 1'b0; |
end else if(sm_ps2mouse == ss_SET_BIT_2) begin |
PS2D_out = 1'b1; |
end else if(sm_ps2mouse == ss_SET_BIT_3) begin |
PS2D_out = 1'b0; |
end else if(sm_ps2mouse == ss_SET_BIT_4) begin |
PS2D_out = 1'b1; |
end else if(sm_ps2mouse == ss_SET_BIT_5) begin |
PS2D_out = 1'b1; |
end else if(sm_ps2mouse == ss_SET_BIT_6) begin |
PS2D_out = 1'b1; |
end else if(sm_ps2mouse == ss_SET_BIT_7) begin |
PS2D_out = 1'b1; |
end else if(sm_ps2mouse == ss_SET_BIT_PARITY) begin |
PS2D_out = 1'b0; |
end else if(sm_ps2mouse == ss_SET_BIT_STOP) begin |
PS2D_out = 1'b1; |
end else begin |
PS2D_out = 1'bZ; |
end |
end |
|
//------------------------------------------------------------------// |
// RECIEVING DATA // |
//------------------------------------------------------------------// |
always @ (negedge CLK_ps2c_debounced or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) begin |
data_in_buf <= 33'b0; |
end else if(sm_ps2mouse == ss_GET_MOVEMENT) begin |
data_in_buf <= data_in_buf >> 1; |
data_in_buf[32] <= PS2D; |
end else |
data_in_buf <= data_in_buf; |
end |
|
|
|
//------------------------------------------------------------------// |
// COUNTERS FOR STATE MACHINE // |
//------------------------------------------------------------------// |
// COUNTER: timer |
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) |
Counter_timer <= 13'b0; |
else if(Counter_timer == 13'd6000) |
Counter_timer <= Counter_timer; |
else |
Counter_timer <= Counter_timer + 1; |
end |
|
// COUNTER: rec_data_bit_cnt |
always @ (negedge CLK_ps2c_debounced or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) begin |
Counter_bits <= 6'd22; |
end else if(sm_ps2mouse == ss_GET_MOVEMENT) begin |
if(Counter_bits == 6'd32) |
Counter_bits <= 6'd0; |
else |
Counter_bits <= Counter_bits + 1; |
end else begin |
Counter_bits <= Counter_bits; |
end |
end |
|
|
//------------------------------------------------------------------// |
// MOUSE STATE MACHINE // |
//------------------------------------------------------------------// |
always @ (negedge CLK_ps2c_debounced or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) begin |
sm_ps2mouse <= ss_DATA_LOW; |
end else if(sm_ps2mouse == ss_DATA_LOW) begin |
sm_ps2mouse <= ss_SET_BIT_0; |
end else if(sm_ps2mouse == ss_SET_BIT_0) begin |
sm_ps2mouse <= ss_SET_BIT_1; |
end else if(sm_ps2mouse == ss_SET_BIT_1) begin |
sm_ps2mouse <= ss_SET_BIT_2; |
end else if(sm_ps2mouse == ss_SET_BIT_2) begin |
sm_ps2mouse <= ss_SET_BIT_3; |
end else if(sm_ps2mouse == ss_SET_BIT_3) begin |
sm_ps2mouse <= ss_SET_BIT_4; |
end else if(sm_ps2mouse == ss_SET_BIT_4) begin |
sm_ps2mouse <= ss_SET_BIT_5; |
end else if(sm_ps2mouse == ss_SET_BIT_5) begin |
sm_ps2mouse <= ss_SET_BIT_6; |
end else if(sm_ps2mouse == ss_SET_BIT_6) begin |
sm_ps2mouse <= ss_SET_BIT_7; |
end else if(sm_ps2mouse == ss_SET_BIT_7) begin |
sm_ps2mouse <= ss_SET_BIT_PARITY; |
end else if(sm_ps2mouse == ss_SET_BIT_PARITY) begin |
sm_ps2mouse <= ss_SET_BIT_STOP; |
end else if(sm_ps2mouse == ss_SET_BIT_STOP) begin |
sm_ps2mouse <= ss_WAIT_BIT_ACK; |
end else if(sm_ps2mouse == ss_WAIT_BIT_ACK) begin |
sm_ps2mouse <= ss_GET_MOVEMENT; |
end else if(sm_ps2mouse == ss_GET_MOVEMENT) begin |
sm_ps2mouse <= sm_ps2mouse; |
end else begin |
sm_ps2mouse <= ss_DATA_LOW; |
end |
end |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
endmodule |
|
/tags/rels3/Mouse/d_DriverMouse.v
0,0 → 1,359
//================================================================== |
// File: d_MouseDriver.v |
// Version: 0.01 |
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
// Copyright Stephen Pickett |
// April 28, 2005 |
//------------------------------------------------------------------ |
// Revisions: |
// Ver 0.01 Apr 28, 2005 Initial Release |
// |
//================================================================== |
|
module Driver_mouse( |
CLK_50MHZ, MASTER_RST, |
PS2C, PS2D, |
XCOORD, YCOORD, |
L_BUTTON, R_BUTTON, M_BUTTON |
); |
|
//==================================================================// |
// DEFINITIONS // |
//==================================================================// |
parameter ss_CLK_LOW_100US = 4'b0000; |
parameter ss_DATA_LOW = 4'b0001; |
parameter ss_SET_BIT_0 = 4'b0011; |
parameter ss_SET_BIT_1 = 4'b0010; |
parameter ss_SET_BIT_2 = 4'b0110; |
parameter ss_SET_BIT_3 = 4'b0111; |
parameter ss_SET_BIT_4 = 4'b0101; |
parameter ss_SET_BIT_5 = 4'b0100; |
parameter ss_SET_BIT_6 = 4'b1100; |
parameter ss_SET_BIT_7 = 4'b1101; |
parameter ss_SET_BIT_PARITY = 4'b1111; |
parameter ss_SET_BIT_STOP = 4'b1110; |
parameter ss_WAIT_BIT_ACK = 4'b1010; |
parameter ss_GET_MOVEMENT = 4'b1000; |
|
parameter P_Lbut_index = 1; |
parameter P_Mbut_index = 2; |
parameter P_Rbut_index = 3; |
|
|
//==================================================================// |
// VARIABLE DEFINITIONS // |
//==================================================================// |
//----------------------// |
// INPUTS // |
//----------------------// |
input CLK_50MHZ; // System wide clock |
input MASTER_RST; // System wide reset |
inout PS2C; // PS2 clock |
inout PS2D; // PS2 data |
|
//----------------------// |
// OUTPUTS // |
//----------------------// |
output[11:0] XCOORD; // X coordinate of the cursor |
output[11:0] YCOORD; // Y coordinate of the cursor |
output L_BUTTON, R_BUTTON, M_BUTTON; |
|
//----------------------// |
// WIRES / NODES // |
//----------------------// |
wire CLK_50MHZ, MASTER_RST; |
wire PS2C, PS2D; |
reg[11:0] XCOORD; |
reg[11:0] YCOORD; |
reg L_BUTTON, R_BUTTON, M_BUTTON; |
|
//----------------------// |
// REGISTERS // |
//----------------------// |
reg[12:0] Counter_timer; |
reg[5:0] Counter_bits; |
reg[3:0] sm_ps2mouse; |
reg[32:0] data_in_buf; |
|
|
|
|
//==================================================================// |
// FUNCTIONAL DEFINITIONS // |
//==================================================================// |
|
//------------------------------------------------------------------// |
// INTERMEDIATE VALUES // |
//------------------------------------------------------------------// |
reg[7:0] Counter_PS2C; |
reg CLK_ps2c_debounced; |
|
// Debounce the PS2C line. |
// The mouse is generally not outputting a nice rising clock edge. |
// To eliminate the false edge detection, make sure it is high/low |
// for at least 256 counts before triggering the CLK. |
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) begin |
Counter_PS2C <= 8'b0; |
end else begin |
if(PS2C == 1'b1) begin |
if(Counter_PS2C == 8'hFF) |
Counter_PS2C <= Counter_PS2C; |
else |
Counter_PS2C <= Counter_PS2C + 1; |
end else begin |
if(Counter_PS2C == 8'b0) |
Counter_PS2C <= Counter_PS2C; |
else |
Counter_PS2C <= Counter_PS2C - 1; |
end |
end |
end |
|
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) |
CLK_ps2c_debounced <= 1'b0; |
else if(Counter_PS2C == 8'b0) |
CLK_ps2c_debounced <= 1'b0; |
else if(Counter_PS2C == 8'hFF) |
CLK_ps2c_debounced <= 1'b1; |
else |
CLK_ps2c_debounced <= CLK_ps2c_debounced; |
end |
|
|
//------------------------------------------------------------------// |
// INTERPRETING MOVEMENTS // |
//------------------------------------------------------------------// |
reg[7:0] xcoord_buf; |
reg[7:0] ycoord_buf; |
|
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) begin |
xcoord_buf <= 8'b0; |
end else if(data_in_buf[5] == 1'b0) begin |
xcoord_buf <= data_in_buf[19:12]; |
end else begin |
xcoord_buf <= ((~(data_in_buf[19:12]))+1); |
end |
end |
|
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) begin |
ycoord_buf <= 8'b0; |
end else if(data_in_buf[6] == 1'b0) begin |
ycoord_buf <= data_in_buf[30:23]; |
end else begin |
ycoord_buf <= ((~(data_in_buf[30:23]))+1); |
end |
end |
|
|
always @ (posedge CLK_ps2c_debounced or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) begin |
XCOORD <= 12'd320; |
end else if(Counter_bits == 6'd32 && (data_in_buf[7] == 1'b0)) begin |
if(data_in_buf[5] == 1'b1) begin // NEGITIVE |
if(XCOORD <= xcoord_buf) |
XCOORD <= 12'b0; |
else |
XCOORD <= XCOORD - xcoord_buf; |
end else begin // POSITIVE |
if((XCOORD + xcoord_buf) >= 11'd639) |
XCOORD <= 12'd639; |
else |
XCOORD <= XCOORD + xcoord_buf; |
end |
end else begin |
XCOORD <= XCOORD; |
end |
end |
|
always @ (posedge CLK_ps2c_debounced or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) begin |
YCOORD <= 12'd199; |
end else if(Counter_bits == 6'd32 && (data_in_buf[8] == 1'b0)) begin |
if(data_in_buf[6] == 1'b0) begin |
if((YCOORD + ycoord_buf) >= 11'd479) |
YCOORD <= 12'd479; |
else |
YCOORD <= YCOORD + ycoord_buf; |
end else begin |
if(YCOORD <= ycoord_buf) |
YCOORD <= 12'd0; |
else |
YCOORD <= YCOORD - ycoord_buf; |
end |
end else begin |
YCOORD <= YCOORD; |
end |
end |
|
//------------------------------------------------------------------// |
// INTERPRETING BUTTONS // |
//------------------------------------------------------------------// |
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) begin |
L_BUTTON <= 1'b0; |
M_BUTTON <= 1'b0; |
R_BUTTON <= 1'b0; |
end else if(Counter_bits == 6'd32) begin |
L_BUTTON <= data_in_buf[P_Lbut_index]; |
M_BUTTON <= data_in_buf[P_Mbut_index]; |
R_BUTTON <= data_in_buf[P_Rbut_index]; |
end else begin |
L_BUTTON <= L_BUTTON; |
M_BUTTON <= M_BUTTON; |
R_BUTTON <= R_BUTTON; |
end |
end |
|
|
|
|
//------------------------------------------------------------------// |
// SENDING DATA // |
//------------------------------------------------------------------// |
reg PS2C_out, PS2D_out; |
|
assign PS2C = PS2C_out; |
assign PS2D = PS2D_out; |
|
|
always @ (Counter_timer or MASTER_RST) begin |
if(MASTER_RST == 1'b1) begin |
PS2C_out = 1'bZ; |
end else if((Counter_timer <= 13'd5500) && (MASTER_RST == 1'b0)) |
PS2C_out = 1'b0; |
else |
PS2C_out = 1'bZ; |
end |
|
always @ (sm_ps2mouse or Counter_timer or MASTER_RST) begin |
if(MASTER_RST == 1'b1) begin |
PS2D_out = 1'bZ; |
end else if(Counter_timer >= 13'd5000 && sm_ps2mouse == ss_DATA_LOW) begin |
PS2D_out = 1'b0; |
end else if(sm_ps2mouse == ss_SET_BIT_0) begin |
PS2D_out = 1'b0; |
end else if(sm_ps2mouse == ss_SET_BIT_1) begin |
PS2D_out = 1'b0; |
end else if(sm_ps2mouse == ss_SET_BIT_2) begin |
PS2D_out = 1'b1; |
end else if(sm_ps2mouse == ss_SET_BIT_3) begin |
PS2D_out = 1'b0; |
end else if(sm_ps2mouse == ss_SET_BIT_4) begin |
PS2D_out = 1'b1; |
end else if(sm_ps2mouse == ss_SET_BIT_5) begin |
PS2D_out = 1'b1; |
end else if(sm_ps2mouse == ss_SET_BIT_6) begin |
PS2D_out = 1'b1; |
end else if(sm_ps2mouse == ss_SET_BIT_7) begin |
PS2D_out = 1'b1; |
end else if(sm_ps2mouse == ss_SET_BIT_PARITY) begin |
PS2D_out = 1'b0; |
end else if(sm_ps2mouse == ss_SET_BIT_STOP) begin |
PS2D_out = 1'b1; |
end else begin |
PS2D_out = 1'bZ; |
end |
end |
|
//------------------------------------------------------------------// |
// RECIEVING DATA // |
//------------------------------------------------------------------// |
always @ (negedge CLK_ps2c_debounced or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) begin |
data_in_buf <= 33'b0; |
end else if(sm_ps2mouse == ss_GET_MOVEMENT) begin |
data_in_buf <= data_in_buf >> 1; |
data_in_buf[32] <= PS2D; |
end else |
data_in_buf <= data_in_buf; |
end |
|
|
|
//------------------------------------------------------------------// |
// COUNTERS FOR STATE MACHINE // |
//------------------------------------------------------------------// |
// COUNTER: timer |
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) |
Counter_timer <= 13'b0; |
else if(Counter_timer == 13'd6000) |
Counter_timer <= Counter_timer; |
else |
Counter_timer <= Counter_timer + 1; |
end |
|
// COUNTER: rec_data_bit_cnt |
always @ (negedge CLK_ps2c_debounced or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) begin |
Counter_bits <= 6'd22; |
end else if(sm_ps2mouse == ss_GET_MOVEMENT) begin |
if(Counter_bits == 6'd32) |
Counter_bits <= 6'd0; |
else |
Counter_bits <= Counter_bits + 1; |
end else begin |
Counter_bits <= Counter_bits; |
end |
end |
|
|
//------------------------------------------------------------------// |
// MOUSE STATE MACHINE // |
//------------------------------------------------------------------// |
always @ (negedge CLK_ps2c_debounced or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) begin |
sm_ps2mouse <= ss_DATA_LOW; |
end else if(sm_ps2mouse == ss_DATA_LOW) begin |
sm_ps2mouse <= ss_SET_BIT_0; |
end else if(sm_ps2mouse == ss_SET_BIT_0) begin |
sm_ps2mouse <= ss_SET_BIT_1; |
end else if(sm_ps2mouse == ss_SET_BIT_1) begin |
sm_ps2mouse <= ss_SET_BIT_2; |
end else if(sm_ps2mouse == ss_SET_BIT_2) begin |
sm_ps2mouse <= ss_SET_BIT_3; |
end else if(sm_ps2mouse == ss_SET_BIT_3) begin |
sm_ps2mouse <= ss_SET_BIT_4; |
end else if(sm_ps2mouse == ss_SET_BIT_4) begin |
sm_ps2mouse <= ss_SET_BIT_5; |
end else if(sm_ps2mouse == ss_SET_BIT_5) begin |
sm_ps2mouse <= ss_SET_BIT_6; |
end else if(sm_ps2mouse == ss_SET_BIT_6) begin |
sm_ps2mouse <= ss_SET_BIT_7; |
end else if(sm_ps2mouse == ss_SET_BIT_7) begin |
sm_ps2mouse <= ss_SET_BIT_PARITY; |
end else if(sm_ps2mouse == ss_SET_BIT_PARITY) begin |
sm_ps2mouse <= ss_SET_BIT_STOP; |
end else if(sm_ps2mouse == ss_SET_BIT_STOP) begin |
sm_ps2mouse <= ss_WAIT_BIT_ACK; |
end else if(sm_ps2mouse == ss_WAIT_BIT_ACK) begin |
sm_ps2mouse <= ss_GET_MOVEMENT; |
end else if(sm_ps2mouse == ss_GET_MOVEMENT) begin |
sm_ps2mouse <= sm_ps2mouse; |
end else begin |
sm_ps2mouse <= ss_DATA_LOW; |
end |
end |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
endmodule |
|
/tags/rels3/UserInput/.#d_MouseInput.v.1.1
0,0 → 1,144
//==================================================================// |
// File: d_MouseInput.v // |
// Version: 0.0.0.2 // |
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -// |
// Copyright (C) Stephen Pickett // |
// Jun 08, 2005 // |
// // |
// This program is free software; you can redistribute it and/or // |
// modify it under the terms of the GNU General Public License // |
// as published by the Free Software Foundation; either version 2 // |
// of the License, or (at your option) any later version. // |
// // |
// This program is distributed in the hope that it will be useful, // |
// but WITHOUT ANY WARRANTY; without even the implied warranty of // |
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // |
// GNU General Public License for more details. // |
// // |
// If you have not received a copy of the GNU General Public License// |
// along with this program; write to: // |
// Free Software Foundation, Inc., // |
// 51 Franklin Street, Fifth Floor, // |
// Boston, MA 02110-1301, USA. // |
// // |
//------------------------------------------------------------------// |
// Revisions: // |
// Ver 0.0.0.1 May , 2005 Under Development // |
// Ver 0.0.0.2 Jun 08, 2005 Modulized 'UserLines' // |
// // |
//==================================================================// |
|
module Driver_MouseInput( |
CLK_50MHZ, MASTER_RST, |
XCOORD, YCOORD, L_BUTTON, R_BUTTON, M_BUTTON, |
TRIGGER_LEVEL |
); |
|
|
//==================================================================// |
// PARAMETER DEFINITIONS // |
//==================================================================// |
parameter P_trigger_clickLimit_left = 10'd556; |
parameter P_trigger_clickLimit_right = 10'd558; |
|
|
//==================================================================// |
// VARIABLE DEFINITIONS // |
//==================================================================// |
//----------------------// |
// INPUTS / OUTPUTS // |
//----------------------// |
input CLK_50MHZ; // System wide clock |
input MASTER_RST; // System wide reset |
input[9:0] XCOORD; // X coordinate of the cursor |
input[9:0] YCOORD; // Y coordinate of the cursor |
input L_BUTTON; // Left Mouse Button Press |
input R_BUTTON; // Right Mouse Button Press |
input M_BUTTON; // Middle Mouse Button Press |
output[9:0] TRIGGER_LEVEL; // Current Trigger Level |
|
//----------------------// |
// WIRES / NODES // |
//----------------------// |
wire CLK_50MHZ, MASTER_RST; |
wire[9:0] XCOORD; |
wire[9:0] YCOORD; |
wire L_BUTTON, R_BUTTON, M_BUTTON; |
wire[9:0] TRIGGER_LEVEL; |
|
//----------------------// |
// REGISTERS // |
//----------------------// |
|
|
//----------------------// |
// TESTING // |
//----------------------// |
|
|
|
|
//==================================================================// |
// FUNCTIONAL DEFINITIONS // |
//==================================================================// |
|
//------------------------------------------------------------------// |
// INTERMEDIATES // |
//------------------------------------------------------------------// |
|
// -- LEFT BUTTON -- |
wire Lrise, Lfall; |
reg Lbuf; |
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) Lbuf <= 1'b0; |
else Lbuf <= L_BUTTON; |
end |
|
assign Lrise = (!Lbuf & L_BUTTON); |
assign Lfall = ( Lbuf & !L_BUTTON); |
|
// -- RIGHT BUTTON -- |
wire Rrise, Rfall; |
reg Rbuf; |
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) Rbuf <= 1'b0; |
else Rbuf <= R_BUTTON; |
end |
|
assign Rrise = (!Rbuf & R_BUTTON); |
assign Rfall = ( Rbuf & !R_BUTTON); |
|
|
// -- MIDDLE BUTTON -- |
wire Mrise, Mfall; |
reg Mbuf; |
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) Mbuf <= 1'b0; |
else Mbuf <= M_BUTTON; |
end |
|
assign Mrise = (!Mbuf & M_BUTTON); |
assign Mfall = ( Mbuf & !M_BUTTON); |
|
|
//------------------------------------------------------------------// |
// USER MODIFIABLE LINES // |
//------------------------------------------------------------------// |
sub_UserLines set_trigger( |
.MASTER_CLK(CLK_50MHZ), .MASTER_RST(MASTER_RST), |
.LINE_VALUE_OUT(TRIGGER_LEVEL), |
.BUTTON_RISE(Lrise), |
.BUTTON_FALL(Lfall), |
.XCOORD(XCOORD), |
.YCOORD(YCOORD), |
.LEFT(P_trigger_clickLimit_left), |
.RGHT(P_trigger_clickLimit_right), |
.BOT(TRIGGER_LEVEL-1'b1), |
.TOP(TRIGGER_LEVEL+1'b1), |
.SETXnY(1'b0) |
); |
|
|
|
endmodule |
|
/tags/rels3/UserInput/d_MouseInput.v
0,0 → 1,144
//==================================================================// |
// File: d_MouseInput.v // |
// Version: 0.0.0.2 // |
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -// |
// Copyright (C) Stephen Pickett // |
// Jun 08, 2005 // |
// // |
// This program is free software; you can redistribute it and/or // |
// modify it under the terms of the GNU General Public License // |
// as published by the Free Software Foundation; either version 2 // |
// of the License, or (at your option) any later version. // |
// // |
// This program is distributed in the hope that it will be useful, // |
// but WITHOUT ANY WARRANTY; without even the implied warranty of // |
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // |
// GNU General Public License for more details. // |
// // |
// If you have not received a copy of the GNU General Public License// |
// along with this program; write to: // |
// Free Software Foundation, Inc., // |
// 51 Franklin Street, Fifth Floor, // |
// Boston, MA 02110-1301, USA. // |
// // |
//------------------------------------------------------------------// |
// Revisions: // |
// Ver 0.0.0.1 May , 2005 Under Development // |
// Ver 0.0.0.2 Jun 08, 2005 Modulized 'UserLines' // |
// // |
//==================================================================// |
|
module Driver_MouseInput( |
CLK_50MHZ, MASTER_RST, |
XCOORD, YCOORD, L_BUTTON, R_BUTTON, M_BUTTON, |
TRIGGER_LEVEL |
); |
|
|
//==================================================================// |
// PARAMETER DEFINITIONS // |
//==================================================================// |
parameter P_trigger_clickLimit_left = 10'd556; |
parameter P_trigger_clickLimit_right = 10'd558; |
|
|
//==================================================================// |
// VARIABLE DEFINITIONS // |
//==================================================================// |
//----------------------// |
// INPUTS / OUTPUTS // |
//----------------------// |
input CLK_50MHZ; // System wide clock |
input MASTER_RST; // System wide reset |
input[9:0] XCOORD; // X coordinate of the cursor |
input[9:0] YCOORD; // Y coordinate of the cursor |
input L_BUTTON; // Left Mouse Button Press |
input R_BUTTON; // Right Mouse Button Press |
input M_BUTTON; // Middle Mouse Button Press |
output[9:0] TRIGGER_LEVEL; // Current Trigger Level |
|
//----------------------// |
// WIRES / NODES // |
//----------------------// |
wire CLK_50MHZ, MASTER_RST; |
wire[9:0] XCOORD; |
wire[9:0] YCOORD; |
wire L_BUTTON, R_BUTTON, M_BUTTON; |
wire[9:0] TRIGGER_LEVEL; |
|
//----------------------// |
// REGISTERS // |
//----------------------// |
|
|
//----------------------// |
// TESTING // |
//----------------------// |
|
|
|
|
//==================================================================// |
// FUNCTIONAL DEFINITIONS // |
//==================================================================// |
|
//------------------------------------------------------------------// |
// INTERMEDIATES // |
//------------------------------------------------------------------// |
|
// -- LEFT BUTTON -- |
wire Lrise, Lfall; |
reg Lbuf; |
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) Lbuf <= 1'b0; |
else Lbuf <= L_BUTTON; |
end |
|
assign Lrise = (!Lbuf & L_BUTTON); |
assign Lfall = ( Lbuf & !L_BUTTON); |
|
// -- RIGHT BUTTON -- |
wire Rrise, Rfall; |
reg Rbuf; |
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) Rbuf <= 1'b0; |
else Rbuf <= R_BUTTON; |
end |
|
assign Rrise = (!Rbuf & R_BUTTON); |
assign Rfall = ( Rbuf & !R_BUTTON); |
|
|
// -- MIDDLE BUTTON -- |
wire Mrise, Mfall; |
reg Mbuf; |
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) Mbuf <= 1'b0; |
else Mbuf <= M_BUTTON; |
end |
|
assign Mrise = (!Mbuf & M_BUTTON); |
assign Mfall = ( Mbuf & !M_BUTTON); |
|
|
//------------------------------------------------------------------// |
// USER MODIFIABLE LINES // |
//------------------------------------------------------------------// |
sub_UserLines set_trigger( |
.MASTER_CLK(CLK_50MHZ), .MASTER_RST(MASTER_RST), |
.LINE_VALUE_OUT(TRIGGER_LEVEL), |
.BUTTON_RISE(Lrise), |
.BUTTON_FALL(Lfall), |
.XCOORD(XCOORD), |
.YCOORD(YCOORD), |
.LEFT(P_trigger_clickLimit_left), |
.RGHT(P_trigger_clickLimit_right), |
.BOT(TRIGGER_LEVEL-1'b1), |
.TOP(TRIGGER_LEVEL+1'b1), |
.SETXnY(1'b0) |
); |
|
|
|
endmodule |
|
/tags/rels3/UserInput/sub_UserLines.v
0,0 → 1,117
//==================================================================// |
// File: sub_UserLines.v // |
// Version: 0.0.0.1 // |
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -// |
// Copyright (C) Stephen Pickett // |
// Jun 08, 2005 // |
// // |
// This program is free software; you can redistribute it and/or // |
// modify it under the terms of the GNU General Public License // |
// as published by the Free Software Foundation; either version 2 // |
// of the License, or (at your option) any later version. // |
// // |
// This program is distributed in the hope that it will be useful, // |
// but WITHOUT ANY WARRANTY; without even the implied warranty of // |
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // |
// GNU General Public License for more details. // |
// // |
// If you have not received a copy of the GNU General Public License// |
// along with this program; write to: // |
// Free Software Foundation, Inc., // |
// 51 Franklin Street, Fifth Floor, // |
// Boston, MA 02110-1301, USA. // |
// // |
//------------------------------------------------------------------// |
// Revisions: // |
// Ver 0.0.0.1 Jun 08, 2005 Under Development // |
// // |
//==================================================================// |
|
module sub_UserLines( |
MASTER_CLK, MASTER_RST, |
LINE_VALUE_OUT, |
BUTTON_RISE, BUTTON_FALL, |
XCOORD, YCOORD, |
LEFT, RGHT, BOT, TOP, |
SETXnY |
); |
|
//==================================================================// |
// DEFINITIONS // |
//==================================================================// |
|
|
//==================================================================// |
// VARIABLE DEFINITIONS // |
//==================================================================// |
//----------------------// |
// INPUTS / OUTPUTS // |
//----------------------// |
input MASTER_CLK; // global master clock |
input MASTER_RST; // global master reset |
input XCOORD, YCOORD; // X and Y coordinates of the current mouse |
// position. See the documentation for details |
input LEFT, RGHT; // Left and Right limits for 'InRange' |
input TOP, BOT; // Top and Bottom limits for 'InRange' |
input SETXnY; // Upon trigger, either set the 'Value' to the |
// X or Y coord. |
input BUTTON_RISE; // Trigger has risen |
input BUTTON_FALL; // Trigger has fallen |
|
output[9:0] LINE_VALUE_OUT; // a 10 bit register to store the X or Y value |
|
//----------------------// |
// NODES // |
//----------------------// |
wire MASTER_CLK, MASTER_RST; |
wire[9:0] XCOORD, YCOORD; |
wire[9:0] LEFT, RGHT, TOP, BOT; |
wire SETXnY; |
wire BUTTON_RISE, BUTTON_FALL; |
|
reg[9:0] LINE_VALUE_OUT; |
|
|
|
|
//==================================================================// |
// T E S T I N G // |
//==================================================================// |
// NOTHING TO TEST |
|
//==================================================================// |
// FUNCTIONAL DEFINITIONS // |
//==================================================================// |
wire in_range; |
reg drag; |
|
assign in_range = (((YCOORD >= BOT) && (YCOORD <= TOP)) && ((XCOORD >= LEFT && XCOORD <= RGHT))); |
|
// the 'DRAG' state machine |
always @ (posedge MASTER_CLK or posedge MASTER_RST) begin |
if(MASTER_RST) |
drag <= 1'b0; |
else if(BUTTON_RISE && in_range) |
drag <= 1'b1; |
else if(BUTTON_FALL) |
drag <= 1'b0; |
else |
drag <= drag; |
end |
|
|
always @ (posedge MASTER_CLK or posedge MASTER_RST) begin |
if(MASTER_RST) |
LINE_VALUE_OUT <= 10'd200; |
else if(drag && SETXnY) |
LINE_VALUE_OUT <= XCOORD; |
else if(drag && !SETXnY) |
LINE_VALUE_OUT <= YCOORD; |
else |
LINE_VALUE_OUT <= LINE_VALUE_OUT; |
end |
|
|
|
endmodule |
|
/tags/rels3/d_TopLevel.v
0,0 → 1,254
//==================================================================// |
// File: d_TopLevel.v // |
// Version: 0.0.0.3 // |
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -// |
// Copyright (C) Stephen Pickett // |
// Jun 08, 2005 // |
// // |
// This program is free software; you can redistribute it and/or // |
// modify it under the terms of the GNU General Public License // |
// as published by the Free Software Foundation; either version 2 // |
// of the License, or (at your option) any later version. // |
// // |
// This program is distributed in the hope that it will be useful, // |
// but WITHOUT ANY WARRANTY; without even the implied warranty of // |
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // |
// GNU General Public License for more details. // |
// // |
// If you have not received a copy of the GNU General Public License// |
// along with this program; write to: // |
// Free Software Foundation, Inc., // |
// 51 Franklin Street, Fifth Floor, // |
// Boston, MA 02110-1301, USA. // |
// // |
//------------------------------------------------------------------// |
// Revisions: // |
// Ver 0.0.0.1 Apr , 2005 Under Development // |
// Ver 0.0.0.2 Jun 08, 2005 Updates // |
// Ver 0.0.0.3 Jun 19, 2005 Added Character Display // |
// // |
//==================================================================// |
|
module TopLevel( |
CLK_50MHZ_IN, MASTER_RST, |
H_SYNC, V_SYNC, VGA_OUTPUT, |
PS2C, PS2D, |
// TIME_BASE, |
ADC_DATA, ADC_CLK, |
VGA_RAM_ADDR, VGA_RAM_DATA, |
VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS, |
|
SEG_OUT, SEG_SEL, leds, SHOW_LEVELS_BUTTON |
); |
|
//==================================================================// |
// DEFINITIONS // |
//==================================================================// |
|
//==================================================================// |
// VARIABLE DEFINITIONS // |
//==================================================================// |
|
//----------------------// |
// INPUTS / OUTPUTS // |
//----------------------// |
input CLK_50MHZ_IN, MASTER_RST; |
output H_SYNC, V_SYNC; |
output[2:0] VGA_OUTPUT; |
//input[5:0] TIME_BASE; |
inout PS2C, PS2D; |
input[7:0] ADC_DATA; |
output ADC_CLK; |
output[17:0] VGA_RAM_ADDR; |
inout[15:0] VGA_RAM_DATA; |
output VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS; |
|
output[7:0] leds; |
output[6:0] SEG_OUT; |
output[3:0] SEG_SEL; |
input SHOW_LEVELS_BUTTON; |
wire SHOW_LEVELS_BUTTON; |
|
|
//----------------------// |
// WIRES / NODES // |
//----------------------// |
wire CLK_50MHZ_IN, MASTER_RST; |
wire H_SYNC, V_SYNC; |
wire[2:0] VGA_OUTPUT; |
wire[5:0] TIME_BASE; |
wire PS2C, PS2D; |
wire[7:0] ADC_DATA; |
wire ADC_CLK; |
wire[17:0] VGA_RAM_ADDR; |
wire[15:0] VGA_RAM_DATA; |
wire VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS; |
|
|
//----------------------// |
// VARIABLES // |
//----------------------// |
assign TIME_BASE = 6'b0; |
|
|
//==================================================================// |
// TEMP // |
//==================================================================// |
wire[17:0] VGA_RAM_ADDRESS_w; |
wire[15:0] VGA_RAM_DATA_w; |
wire L_BUTTON, R_BUTTON, M_BUTTON; |
|
wire VGA_RAM_ACCESS_OK; |
wire CLK_50MHZ, CLK_64MHZ, CLK180_64MHZ; |
reg CLK_VGA; |
wire[6:0] SEG_OUT; |
wire[3:0] SEG_SEL; |
|
wire[7:0] data_charRamRead; |
reg[7:0] data_charRamRead_buf; |
wire[7:0] mask_charMap; |
reg[7:0] mask_charMap_buf; |
|
always @ (posedge CLK_50MHZ) begin |
if(R_BUTTON) begin |
data_charRamRead_buf <= data_charRamRead_buf; |
mask_charMap_buf <= mask_charMap_buf; |
end else begin |
data_charRamRead_buf <= data_charRamRead; |
mask_charMap_buf <= mask_charMap; |
end |
end |
|
sub_SegDriver segs( |
.CLK_50MHZ(CLK_50MHZ), .MASTER_RST(MASTER_RST), |
.DATA_IN(data_charRamRead_buf), |
.SEG_OUT(SEG_OUT), .SEG_SEL(SEG_SEL) |
); |
|
wire[7:0] leds; |
assign leds = mask_charMap_buf; |
|
//==================================================================// |
// SUBROUTINES // |
//==================================================================// |
//d_DCM_VGA clock_gen_VGA ( |
// .CLKIN_IN(CLK_50MHZ_IN), |
// .RST_IN(MASTER_RST), |
// .CLKFX_OUT(CLK_VGA), |
// .CLKIN_IBUFG_OUT(CLK_50MHZ_B), |
// .LOCKED_OUT(CLK_VGA_LOCKED) |
// ); |
|
always @ (posedge CLK_50MHZ or posedge MASTER_RST) |
if(MASTER_RST) CLK_VGA <= 1'b0; |
else CLK_VGA <= ~CLK_VGA; |
|
|
wire CLK_64MHZ_LOCKED; |
d_DCM clock_generator( |
.CLKIN_IN(CLK_50MHZ_IN), |
.RST_IN(MASTER_RST), |
.CLKIN_IBUFG_OUT(CLK_50MHZ), |
.CLK_64MHZ(CLK_64MHZ), |
.CLK180_64MHZ(CLK180_64MHZ), |
.LOCKED_OUT(CLK_64MHZ_LOCKED) |
); |
|
wire[11:0] XCOORD, YCOORD; |
wire[9:0] TRIGGER_LEVEL; |
Driver_mouse driver_MOUSE( |
.CLK_50MHZ(CLK_50MHZ), .MASTER_RST(MASTER_RST), |
.PS2C(PS2C), .PS2D(PS2D), |
.XCOORD(XCOORD), .YCOORD(YCOORD), |
.L_BUTTON(L_BUTTON), .M_BUTTON(M_BUTTON), .R_BUTTON(R_BUTTON) |
); |
|
Driver_MouseInput Driver_MouseInput_inst( |
.CLK_50MHZ(CLK_50MHZ), .MASTER_RST(MASTER_RST), |
.XCOORD(XCOORD[9:0]), .YCOORD(YCOORD[9:0]), |
.L_BUTTON(L_BUTTON), .M_BUTTON(M_BUTTON), .R_BUTTON(R_BUTTON), |
.TRIGGER_LEVEL(TRIGGER_LEVEL) |
); |
|
|
|
wire[7:0] ADC_RAM_DATA; |
wire[10:0] ADC_RAM_ADDR; |
wire ADC_RAM_CLK; |
wire[10:0] TRIG_ADDR; |
wire VGA_WRITE_DONE; |
ADCDataBuffer ram_ADC_databuffer( |
.CLK_64MHZ(CLK_64MHZ), .MASTER_RST(MASTER_RST), |
.CLK180_64MHZ(CLK180_64MHZ), |
.TIME_BASE(TIME_BASE), |
.RAM_ADDR(ADC_RAM_ADDR), .RAM_DATA(ADC_RAM_DATA), .RAM_CLK(ADC_RAM_CLK), |
.ADC_DATA(ADC_DATA), .ADC_CLK(ADC_CLK), |
.TRIG_ADDR(TRIG_ADDR), .VGA_WRITE_DONE(VGA_WRITE_DONE), |
.TRIGGER_LEVEL(TRIGGER_LEVEL[8:0]) |
); |
|
|
|
//------------------------------------------------------------------// |
// VGA // |
//------------------------------------------------------------------// |
wire[9:0] HCNT, VCNT; |
wire[2:0] RGB_CHAR; |
|
|
CharacterDisplay charTest( |
.MASTER_CLK(CLK_50MHZ), .MASTER_RST(MASTER_RST), |
.CLK_VGA(CLK_VGA), .HCNT(HCNT), .VCNT(VCNT), |
.RGB_OUT(RGB_CHAR), |
.data_charMap(mask_charMap), .data_charRamRead(data_charRamRead) |
); |
|
|
//wire[17:0] VGA_RAM_ADDRESS_w; |
//wire[15:0] VGA_RAM_DATA_w; |
wire VGA_RAM_OE_w, VGA_RAM_WE_w, VGA_RAM_CS_w; |
wire[17:0] VGA_RAM_ADDRESS_r; |
wire VGA_RAM_OE_r, VGA_RAM_WE_r, VGA_RAM_CS_r; |
//wire VGA_RAM_ACCESS_OK; |
|
assign VGA_RAM_ADDR = (VGA_RAM_ACCESS_OK) ? VGA_RAM_ADDRESS_w : VGA_RAM_ADDRESS_r; |
assign VGA_RAM_DATA = (VGA_RAM_ACCESS_OK) ? VGA_RAM_DATA_w : 16'bZ; |
assign VGA_RAM_OE = (VGA_RAM_ACCESS_OK) ? VGA_RAM_OE_w : VGA_RAM_OE_r; |
assign VGA_RAM_WE = (VGA_RAM_ACCESS_OK) ? VGA_RAM_WE_w : VGA_RAM_WE_r; |
assign VGA_RAM_CS = (VGA_RAM_ACCESS_OK) ? VGA_RAM_CS_w : VGA_RAM_CS_r; |
|
VGADataBuffer ram_VGA_ramwrite( |
.CLK_50MHZ(CLK_50MHZ), .MASTER_RST(MASTER_RST), |
.VGA_RAM_DATA(VGA_RAM_DATA_w), .VGA_RAM_ADDR(VGA_RAM_ADDRESS_w), |
.VGA_RAM_OE(VGA_RAM_OE_w), .VGA_RAM_WE(VGA_RAM_WE_w), .VGA_RAM_CS(VGA_RAM_CS_w), |
.VGA_RAM_ACCESS_OK(VGA_RAM_ACCESS_OK), |
.ADC_RAM_DATA(ADC_RAM_DATA), .ADC_RAM_ADDR(ADC_RAM_ADDR), .ADC_RAM_CLK(ADC_RAM_CLK), |
.TIME_BASE(TIME_BASE), |
.TRIG_ADDR(TRIG_ADDR), .VGA_WRITE_DONE(VGA_WRITE_DONE) |
); |
|
Driver_VGA driver_VGA( |
.CLK_50MHZ(CLK_50MHZ), .MASTER_RST(MASTER_RST), |
.CLK_VGA(CLK_VGA), |
.H_SYNC(H_SYNC), .V_SYNC(V_SYNC), .VGA_OUTPUT(VGA_OUTPUT), |
.XCOORD(XCOORD), .YCOORD(YCOORD), |
.VGA_RAM_DATA(VGA_RAM_DATA), .VGA_RAM_ADDR(VGA_RAM_ADDRESS_r), |
.VGA_RAM_OE(VGA_RAM_OE_r), .VGA_RAM_WE(VGA_RAM_WE_r), .VGA_RAM_CS(VGA_RAM_CS_r), |
.VGA_RAM_ACCESS_OK(VGA_RAM_ACCESS_OK), |
.TRIGGER_LEVEL(TRIGGER_LEVEL[8:0]), |
.SHOW_LEVELS(SHOW_LEVELS_BUTTON), |
.HCNT(HCNT), .VCNT(VCNT), |
.RGB_CHAR(RGB_CHAR) |
); |
|
|
|
|
|
|
//==================================================================// |
// FUNCTIONAL DEFINITIONS // |
//==================================================================// |
|
endmodule |
|
/tags/rels3/VGA/d_VGAdriver.v
0,0 → 1,318
//==================================================================// |
// File: d_VGAdriver.v // |
// Version: 0.0.0.2 // |
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -// |
// Copyright (C) Stephen Pickett // |
// Jun 09, 2005 // |
// // |
// This program is free software; you can redistribute it and/or // |
// modify it under the terms of the GNU General Public License // |
// as published by the Free Software Foundation; either version 2 // |
// of the License, or (at your option) any later version. // |
// // |
// This program is distributed in the hope that it will be useful, // |
// but WITHOUT ANY WARRANTY; without even the implied warranty of // |
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // |
// GNU General Public License for more details. // |
// // |
// If you have not received a copy of the GNU General Public License// |
// along with this program; write to: // |
// Free Software Foundation, Inc., // |
// 51 Franklin Street, Fifth Floor, // |
// Boston, MA 02110-1301, USA. // |
// // |
//------------------------------------------------------------------// |
// Revisions: // |
// Ver 0.0.0.1 Apr 28, 2005 Under Development // |
// 0.0.0.2 Jun 09, 2005 Cleaning // |
// 0.0.0.3 Jun 10, 2005 Re-structuerd the VCNT and HCNT // |
// so they line up with the PXLs. // |
// // |
//==================================================================// |
|
module Driver_VGA( |
CLK_50MHZ, MASTER_RST, |
CLK_VGA, |
VGA_RAM_DATA, VGA_RAM_ADDR, |
VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS, |
VGA_RAM_ACCESS_OK, |
H_SYNC, V_SYNC, VGA_OUTPUT, |
XCOORD, YCOORD, ram_vshift, |
TRIGGER_LEVEL, |
SHOW_LEVELS, |
HCNT, VCNT, |
RGB_CHAR |
); |
|
//==================================================================// |
// PARAMETER DEFINITIONS // |
//==================================================================// |
parameter P_black = 3'b000; |
parameter P_yellow = 3'b110; |
parameter P_cyan = 3'b011; |
parameter P_green = 3'b010; |
parameter P_white = 3'b111; |
|
//==================================================================// |
// VARIABLE DEFINITIONS // |
//==================================================================// |
//----------------------// |
// INPUTS / OUTPUTS // |
//----------------------// |
input CLK_50MHZ; // System wide clock |
input MASTER_RST; // System wide reset |
input CLK_VGA; |
output H_SYNC; // The H_SYNC timing signal to the VGA monitor |
output V_SYNC; // The V_SYNC timing signal to the VGA monitor |
output[2:0] VGA_OUTPUT; // The 3-bit VGA output |
input[11:0] XCOORD, YCOORD; |
input[15:0] VGA_RAM_DATA; |
output[17:0] VGA_RAM_ADDR; |
output VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS; |
output VGA_RAM_ACCESS_OK; |
input[8:0] TRIGGER_LEVEL; |
input SHOW_LEVELS; |
output[9:0] HCNT, VCNT; |
input[2:0] RGB_CHAR; |
|
output[15:0] ram_vshift; |
|
|
|
|
//----------------------// |
// WIRES / NODES // |
//----------------------// |
reg H_SYNC, V_SYNC; |
reg [2:0] VGA_OUTPUT; |
wire CLK_50MHZ, MASTER_RST; |
wire CLK_VGA; |
wire[11:0] XCOORD, YCOORD; |
wire[15:0] VGA_RAM_DATA; |
reg[17:0] VGA_RAM_ADDR; |
reg VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS; |
reg VGA_RAM_ACCESS_OK; |
wire[8:0] TRIGGER_LEVEL; |
wire SHOW_LEVELS; |
wire[9:0] HCNT, VCNT; |
wire[2:0] RGB_CHAR; |
|
|
//----------------------// |
// REGISTERS // |
//----------------------// |
//reg CLK_25MHZ; // General system clock for VGA timing |
wire CLK_25MHZ = CLK_VGA; |
reg [9:0] hcnt; // Counter - generates the H_SYNC signal |
reg [9:0] vcnt; // Counter - counts the H_SYNC pulses to generate V_SYNC signal |
reg[2:0] vga_out; |
|
//==================================================================// |
// FUNCTIONAL DEFINITIONS // |
//==================================================================// |
assign HCNT = hcnt; |
assign VCNT = vcnt; |
|
//------------------------------------------------------------------// |
// CLOCK FUNCTIONS // |
//------------------------------------------------------------------// |
//always @ (posedge CLK_50MHZ or posedge MASTER_RST) |
// if (MASTER_RST == 1'b1) |
// CLK_25MHZ <= 1'b0; |
// else |
// CLK_25MHZ <= ~CLK_25MHZ; |
|
|
//------------------------------------------------------------------// |
// SYNC TIMING COUNTERS // |
//------------------------------------------------------------------// |
always @ (posedge CLK_25MHZ or posedge MASTER_RST) begin |
if (MASTER_RST == 1'b1) begin |
hcnt <= 10'd0; |
vcnt <= 10'd430; |
end else if (hcnt == 10'd0799) begin |
hcnt <= 10'd0; |
if (vcnt == 10'd0) |
vcnt <= 10'd520; |
else |
vcnt <= vcnt - 1'b1; |
end else |
hcnt <= hcnt + 1'b1; |
end |
|
|
//------------------------------------------------------------------// |
// HORIZONTAL SYNC TIMING // |
//------------------------------------------------------------------// |
always @ (hcnt) |
if (hcnt >= 10'd656 && hcnt <= 10'd751) |
H_SYNC = 1'b0; |
else |
H_SYNC = 1'b1; |
|
|
//------------------------------------------------------------------// |
// VERTICAL SYNC TIMING // |
//------------------------------------------------------------------// |
always @ (vcnt) |
if (vcnt == 10'd430 || vcnt == 10'd429) |
V_SYNC = 1'b0; |
else |
V_SYNC = 1'b1; |
|
|
//------------------------------------------------------------------// |
// VGA DATA SIGNAL TIMING // |
//------------------------------------------------------------------// |
always @ (hcnt or vcnt or XCOORD or YCOORD or MASTER_RST or vga_out or SHOW_LEVELS or TRIGGER_LEVEL) begin |
if(MASTER_RST == 1'b1) begin |
VGA_OUTPUT = P_black; |
//------------------------------------------------------------------------------// |
// UNSEEN BORDERS // |
end else if( (vcnt >= 10'd400) && (vcnt <= 10'd440) ) begin |
VGA_OUTPUT = P_black; |
end else if( (hcnt >= 10'd640) ) begin |
VGA_OUTPUT = P_black; |
//------------------------------------------------------------------------------// |
// MOUSE CURSORS // |
end else if(vcnt == YCOORD) begin |
VGA_OUTPUT = P_green; |
end else if(hcnt == XCOORD) begin |
VGA_OUTPUT = P_green; |
//------------------------------------------------------------------------------// |
// TRIGGER SPRITE (shows as ------T------ ) // |
end else if(SHOW_LEVELS == 1'b1 && vcnt == (TRIGGER_LEVEL) && hcnt != 10'd556 && hcnt != 10'd558) begin |
VGA_OUTPUT = P_yellow; |
end else if(SHOW_LEVELS == 1'b1 && vcnt == (TRIGGER_LEVEL+1'b1) && hcnt >= 10'd556 && hcnt <= 10'd558) begin |
VGA_OUTPUT = P_yellow; |
end else if(SHOW_LEVELS == 1'b1 && vcnt == (TRIGGER_LEVEL-1'b1) && hcnt == 10'd557) begin |
VGA_OUTPUT = P_yellow; |
///* |
//------------------------------------------------------------------------------// |
// MOVE THE WAVEFORM TO THE 'TOP' // |
end else if(vga_out != 0) begin |
VGA_OUTPUT = vga_out; |
//*/ |
//------------------------------------------------------------------------------// |
// TOP, BOTTOM, LEFT AND RIGHT GRID LINES // |
end else if(vcnt == 10'd0 || vcnt == 10'd399 || vcnt == 10'd441) begin |
VGA_OUTPUT = P_cyan; |
end else if(hcnt == 10'd0 || hcnt == 10'd639) begin |
VGA_OUTPUT = P_cyan; |
//------------------------------------------------------------------------------// |
// MIDDLE GRID LINES (dashed at 8pxls) // |
end else if(vcnt == 10'd199 && hcnt[3] == 1'b1) begin |
VGA_OUTPUT = P_cyan; |
end else if((hcnt == 10'd319) && (vcnt <= 10'd399) && (vcnt[3] == 1'b1)) begin |
VGA_OUTPUT = P_cyan; |
//------------------------------------------------------------------------------// |
// OTHER HORIZONTAL LINES (dashed at 4pxls) // |
end else if((vcnt == 10'd39 || vcnt == 10'd79 || vcnt == 10'd119 || vcnt == 10'd159 || vcnt == 10'd239 || vcnt == 10'd279 || vcnt == 10'd319 || vcnt == 10'd359) && (hcnt[2] == 1'b1)) begin |
VGA_OUTPUT = P_cyan; |
//------------------------------------------------------------------------------// |
// OTHER VERTICAL LINES (dashed at 4pxls) // |
end else if(((hcnt[5:0] == 6'b111111) && (vcnt <= 10'd399)) && (vcnt[2] == 1'b1)) begin |
VGA_OUTPUT = P_cyan; |
//------------------------------------------------------------------------------// |
// CHARACTER DISPLAY |
end else if(vcnt <= 10'd520 && vcnt >= 10'd441) begin |
VGA_OUTPUT = RGB_CHAR; |
//------------------------------------------------------------------------------// |
// OTHERWISE... // |
end else |
VGA_OUTPUT = P_black; |
end |
|
//------------------------------------------------------------------// |
// RAM DATA READING // |
//------------------------------------------------------------------// |
// on reset, ram_addr = 24 and add 25 on each pxl |
// row 0: ram_addr = 24 and 25 for each pxl |
// row 1: ram_addr = 24 and 25 for each pxl |
// ... |
// row 15: ram_addr = 24 and 25 for each pxl |
// row 16: ram_addr = 23 and 25 for each pxl * |
// row 17: ram_addr = 23 and 25 for each pxl * |
// ... |
/*reg[9:0] ram_hcnt;*/ |
reg[4:0] ram_vcnt; |
reg[15:0] ram_vshift; |
|
/* |
always @ (posedge CLK_25MHZ or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) begin |
ram_hcnt <= 10'd639; |
end else if(hcnt >= 10'd143 && hcnt <= 782) begin |
if(ram_hcnt == 10'd639) |
ram_hcnt <= 10'b0; |
else |
ram_hcnt <= ram_hcnt + 1'b1; |
end else begin |
ram_hcnt <= 10'd639; |
end |
end |
*/ |
|
always @ (posedge CLK_25MHZ or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) begin |
ram_vshift <= 16'h8000; |
end else if(vcnt > 10'd399) begin |
ram_vshift <= 16'h8000; |
end else if((vcnt <= 10'd399) && (hcnt == 10'd655)) begin |
if(ram_vshift == 16'h0001) |
ram_vshift <= 16'h8000; |
else |
ram_vshift <= (ram_vshift >> 1); |
end else |
ram_vshift <= ram_vshift; |
end |
|
always @ (posedge CLK_25MHZ or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) begin |
ram_vcnt <= 5'd0; |
end else if(vcnt < 10'd30) begin |
ram_vcnt <= 5'd0; |
end else if((vcnt >= 10'd30) && (hcnt == 10'd655) && (ram_vshift == 16'h0001)) begin |
if(ram_vcnt == 5'd0) |
ram_vcnt <= 5'd24; |
else |
ram_vcnt <= ram_vcnt - 1'b1; |
end else begin |
ram_vcnt <= ram_vcnt; |
end |
end |
|
|
|
always @ (hcnt or ram_vcnt) begin |
VGA_RAM_ADDR = ram_vcnt + (hcnt * 7'd25); |
end |
|
|
always @ (VGA_RAM_DATA or ram_vshift) begin |
if((VGA_RAM_DATA & ram_vshift) != 16'b0) |
vga_out = P_white; |
else |
vga_out = 3'b0; |
end |
|
|
always begin |
VGA_RAM_CS = 1'b0; // #CS |
VGA_RAM_OE = 1'b0; // #OE |
VGA_RAM_WE = 1'b1; // #WE |
end |
|
|
//------------------------------------------------------------------// |
// ALL CLEAR? // |
//------------------------------------------------------------------// |
always @ (vcnt) begin |
if((vcnt >= 10'd400) && (vcnt <= 10'd440)) |
VGA_RAM_ACCESS_OK = 1'b1; |
else |
VGA_RAM_ACCESS_OK = 1'b0; |
end |
|
|
endmodule |
/tags/rels3/VGA/CharDecode/d_CharDecode.v
0,0 → 1,430
//==================================================================// |
// File: d_xxxxxxxxxxxx // |
// Version: 0.0.0.1 // |
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -// |
// Copyright (C) Stephen Pickett // |
// Jun 17, 2005 // |
// // |
// This program is free software; you can redistribute it and/or // |
// modify it under the terms of the GNU General Public License // |
// as published by the Free Software Foundation; either version 2 // |
// of the License, or (at your option) any later version. // |
// // |
// This program is distributed in the hope that it will be useful, // |
// but WITHOUT ANY WARRANTY; without even the implied warranty of // |
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // |
// GNU General Public License for more details. // |
// // |
// If you have not received a copy of the GNU General Public License// |
// along with this program; write to: // |
// Free Software Foundation, Inc., // |
// 51 Franklin Street, Fifth Floor, // |
// Boston, MA 02110-1301, USA. // |
// // |
//------------------------------------------------------------------// |
// Revisions: // |
// Ver 0.0.0.1 Jun 17, 2005 Initial Development Release // |
// // |
//==================================================================// |
|
module CharacterDisplay( |
MASTER_CLK, MASTER_RST, |
CLK_VGA, HCNT, VCNT, |
RGB_OUT, |
data_charRamRead, data_charMap |
); |
|
//==================================================================// |
// PARAMETER DEFINITIONS // |
//==================================================================// |
parameter P_black = 3'b000; |
parameter P_yellow = 3'b110; |
parameter P_cyan = 3'b011; |
parameter P_green = 3'b010; |
parameter P_white = 3'b111; |
parameter P_blue = 3'b111; |
|
//==================================================================// |
// VARIABLE DEFINITIONS // |
//==================================================================// |
//----------------------// |
// INPUTS / OUTPUTS // |
//----------------------// |
input MASTER_CLK; // System wide clock |
input MASTER_RST; // System wide reset |
input CLK_VGA; // Pixel Clk |
input[9:0] HCNT; // Horizontal Sync Counter |
input[9:0] VCNT; // Vertical Sync Counter |
output[2:0] RGB_OUT; // The RGB data |
|
output[7:0] data_charRamRead; |
output[7:0] data_charMap; |
|
|
//----------------------// |
// WIRES / NODES // |
//----------------------// |
wire MASTER_CLK, MASTER_RST, CLK_VGA; |
wire[9:0] HCNT, VCNT; |
reg[2:0] RGB_OUT; |
|
|
|
//----------------------// |
// REGISTERS // |
//----------------------// |
reg[3:0] cnt_charPxls; |
reg[5:0] cnt_Hchar; |
reg[10:0] cnt_Vchar; |
wire charRow1, charRow2, charRow3, charRow4; |
|
wire[10:0] addr_charRamRead; |
wire[7:0] data_charRamRead; |
|
reg[7:0] mask_charMap; |
wire[10:0] addr_charMap; |
wire[7:0] data_charMap; |
|
|
//==================================================================// |
// FUNCTIONAL DEFINITIONS // |
//==================================================================// |
|
|
|
//------------------------------------------------------------------// |
// Character Input / Storage // |
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - // |
// A useful description could go here! // |
//------------------------------------------------------------------// |
|
|
|
|
|
//------------------------------------------------------------------// |
// Character Decode // |
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - // |
// A useful description could go here! // |
//------------------------------------------------------------------// |
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - // |
// DECODE the Character RAM Address via HCNT and VCNT // |
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - // |
|
always @ (posedge CLK_VGA or posedge MASTER_RST) begin |
if(MASTER_RST) begin |
cnt_charPxls <= 4'd10; |
end else if(HCNT >= 10'd6) begin //7 |
if(cnt_charPxls == 4'd0) |
cnt_charPxls <= 4'd10; |
else |
cnt_charPxls <= cnt_charPxls-1; |
end else begin |
cnt_charPxls <= 4'd10; |
end |
end |
|
always @ (posedge CLK_VGA or posedge MASTER_RST) begin |
if(MASTER_RST) begin |
cnt_Hchar <= 6'd0; |
end else if(HCNT >= 10'd6 && cnt_charPxls == 4'd0) begin |
if(cnt_Hchar == 6'd56) |
cnt_Hchar <= 6'd0; |
else |
cnt_Hchar <= cnt_Hchar+1; |
end else if(HCNT < 10'd6) begin |
cnt_Hchar <= 6'd0; |
end else begin |
cnt_Hchar <= cnt_Hchar; |
end |
end |
|
assign charRow1 = ((VCNT <= 512) && (VCNT >= 498)); // one more |
assign charRow2 = ((VCNT <= 494) && (VCNT >= 480)); |
assign charRow3 = ((VCNT <= 476) && (VCNT >= 462)); |
assign charRow4 = ((VCNT <= 458) && (VCNT >= 444)); |
|
always @ (charRow1 or charRow2 or charRow3 or charRow4) begin |
if(charRow1) cnt_Vchar = 11'd0; |
else if(charRow2) cnt_Vchar = 11'd57; |
else if(charRow3) cnt_Vchar = 11'd114; |
else cnt_Vchar = 11'd174; |
end |
|
assign addr_charRamRead = cnt_Vchar + cnt_Hchar; |
|
|
|
|
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - // |
// DECODE the Character Map via HCNT and VCNT and CHAR_DATA // |
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - // |
always @ (posedge CLK_VGA or posedge MASTER_RST) begin |
if(MASTER_RST) begin |
mask_charMap <= 8'd0; |
end else if(VCNT <= 10'd512) begin |
if(HCNT == 10'd0 && VCNT[0] == 1'b1) begin //1B0 |
if(mask_charMap == 8'd0) |
mask_charMap <= 8'b10000000; |
else |
mask_charMap <= mask_charMap >> 1; |
end else |
mask_charMap <= mask_charMap; |
end else begin |
mask_charMap <= 8'd0; |
end |
end |
|
|
|
assign addr_charMap = (data_charRamRead * 8'd5) + (cnt_charPxls[3:1]); |
|
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - // |
// DECODE the VGA_OUTPUT via the Character Map // |
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - // |
reg[2:0] rgb_buf; |
|
always @ (mask_charMap or data_charMap) begin |
if((charRow1 | charRow2 | charRow3 | charRow4) && ((mask_charMap & data_charMap) != 8'b0) && (cnt_charPxls != 4'd10) && (HCNT >= 10'd7) && (HCNT <= 10'd632)) |
rgb_buf = P_yellow; |
else |
rgb_buf = P_black; |
end |
|
always @ (posedge CLK_VGA) begin |
RGB_OUT <= rgb_buf; |
end |
|
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - // |
// COUNTER TESTING // |
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - // |
reg[63:0] test_cnt; |
reg[10:0] test_cntAddr; |
reg[7:0] data_time; |
always @ (posedge MASTER_CLK or posedge MASTER_RST) begin |
if(MASTER_RST) |
test_cnt <= 64'd0; |
else |
test_cnt <= test_cnt+1; |
end |
|
always @ (posedge MASTER_CLK or posedge MASTER_RST) begin |
if(MASTER_RST) |
test_cntAddr <= 11'd41; |
else if(test_cntAddr == 11'd56) |
test_cntAddr <= 11'd41; |
else |
test_cntAddr <= test_cntAddr+1; |
end |
|
always @ (test_cntAddr or test_cnt) begin |
if(test_cntAddr == 11'd41) data_time[3:0] = test_cnt[63:60]; |
else if(test_cntAddr == 11'd42) data_time[3:0] = test_cnt[59:56]; |
else if(test_cntAddr == 11'd43) data_time[3:0] = test_cnt[55:52]; |
else if(test_cntAddr == 11'd44) data_time[3:0] = test_cnt[51:48]; |
else if(test_cntAddr == 11'd45) data_time[3:0] = test_cnt[47:44]; |
else if(test_cntAddr == 11'd46) data_time[3:0] = test_cnt[43:40]; |
else if(test_cntAddr == 11'd47) data_time[3:0] = test_cnt[39:36]; |
else if(test_cntAddr == 11'd48) data_time[3:0] = test_cnt[35:32]; |
else if(test_cntAddr == 11'd49) data_time[3:0] = test_cnt[31:28]; |
else if(test_cntAddr == 11'd50) data_time[3:0] = test_cnt[27:24]; |
else if(test_cntAddr == 11'd51) data_time[3:0] = test_cnt[23:20]; |
else if(test_cntAddr == 11'd52) data_time[3:0] = test_cnt[19:16]; |
else if(test_cntAddr == 11'd53) data_time[3:0] = test_cnt[15:12]; |
else if(test_cntAddr == 11'd54) data_time[3:0] = test_cnt[11:8]; |
else if(test_cntAddr == 11'd55) data_time[3:0] = test_cnt[7:4]; |
else if(test_cntAddr == 11'd56) data_time[3:0] = test_cnt[3:0]; |
else data_time[3:0] = 4'b0000; |
end |
|
always begin |
data_time[7:4] = 4'b0; |
end |
|
|
|
|
|
|
|
|
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - // |
// Character Decode RAM INSTANTIATION // |
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - // |
// A useful description could go here! // |
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - // |
wire VCC, GND; |
assign VCC = 1'b1; |
assign GND = 1'b0; |
|
RAMB16_S9_S9 #( |
// 6666555555555544444444443333333333222222222211111111110000000000 |
.INIT_00(256'h920de29292928ee0101010fe449292927c668A9292662242FE02027C8282827C), |
// CCCCCCCCBBBBBBBBBBAAAAAAAAAA999999999988888888887777777777666666 |
.INIT_01(256'h828282c6Fe9292926c7e9090907e609292927d6d9292926d808698a0C07d9292), |
// --SPACE---FFFFFFFFFFEEEEEEEEEEDDDDDDDDDDCC |
.INIT_02(256'h00000000000000000000000000000000Fe909090c0Fe929292c6FE8282827c7c), |
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000) |
) RAM_Character_Map ( |
.DOA(), .DOB(data_charMap), |
.DOPA(), .DOPB(), |
.ADDRA(11'b111), .ADDRB(addr_charMap), |
.CLKA(GND), .CLKB(MASTER_CLK), |
.DIA(8'b0), .DIB(8'b0), |
.DIPA(GND), .DIPB(GND), |
.ENA(GND), .ENB(VCC), |
.WEA(GND), .WEB(GND), |
.SSRA(GND), .SSRB(GND) |
); |
|
|
RAMB16_S9_S9 #( |
.INIT_00(256'h1010101010101010101010100F0E0D0C0B0A0908070605040302010010101010), |
.INIT_01(256'h1010101010101010101010101010101010101010101010101010101010101010), |
.INIT_02(256'h1010101010101010101010101010101010101010101010101010101010101010), |
.INIT_03(256'h1010101010101010101010101010101010101010101010101010101010101010), |
.INIT_04(256'h1010101010101010101010101010101010101010101010101010101010101010), |
.INIT_05(256'h1010101010101010101010101010101010101010101010101010101010101010), |
.INIT_06(256'h1010101010101010101010101010101010101010101010101010101010101010), |
.INIT_07(256'h1010101010101010101010101010101010101010101010101010101010101010), |
.INIT_08(256'h1010101010101010101010101010101010101010101010101010101010101010), |
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), |
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000) |
) RAM_Character_Test ( |
.DOA(), .DOB(data_charRamRead), |
.DOPA(), .DOPB(), |
.ADDRA(test_cntAddr), .ADDRB(addr_charRamRead), |
.CLKA(MASTER_CLK), .CLKB(MASTER_CLK), |
.DIA(data_time), .DIB(8'b0), |
.DIPA(GND), .DIPB(GND), |
.ENA(VCC), .ENB(VCC), |
.WEA(VCC), .WEB(GND), |
.SSRA(GND), .SSRB(GND) |
); |
|
|
|
|
|
|
|
|
endmodule |
/tags/rels3/VGA/d_VgaRamBuffer.v
0,0 → 1,297
//================================================================== |
// File: d_VgaRamBuffer.v |
// Version: 0.01 |
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
// Copyright Stephen Pickett |
// April 28, 2005 |
//------------------------------------------------------------------ |
// Revisions: |
// Ver 0.01 Apr 28, 2005 Initial Release |
// |
//================================================================== |
module VGADataBuffer( |
CLK_50MHZ, MASTER_RST, |
VGA_RAM_DATA, VGA_RAM_ADDR, VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS, |
VGA_RAM_ACCESS_OK, |
ADC_RAM_DATA, ADC_RAM_ADDR, ADC_RAM_CLK, |
TIME_BASE, |
TRIG_ADDR, VGA_WRITE_DONE |
); |
//==================================================================// |
// VARIABLE DEFINITIONS // |
//==================================================================// |
//----------------------// |
// INPUTS / OUTPUTS // |
//----------------------// |
input CLK_50MHZ; // System wide clock |
input MASTER_RST; // System wide reset |
|
output[15:0] VGA_RAM_DATA; |
output[17:0] VGA_RAM_ADDR; |
output VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS; |
input VGA_RAM_ACCESS_OK; |
|
input[7:0] ADC_RAM_DATA; |
output[10:0] ADC_RAM_ADDR; |
output ADC_RAM_CLK; |
|
input[5:0] TIME_BASE; |
|
output VGA_WRITE_DONE; |
input[10:0] TRIG_ADDR; |
|
|
//----------------------// |
// WIRES / NODES // |
//----------------------// |
wire CLK_50MHZ; // System wide clock |
wire MASTER_RST; // System wide reset |
wire[15:0] VGA_RAM_DATA; |
reg[17:0] VGA_RAM_ADDR; |
reg VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS; |
wire VGA_RAM_ACCESS_OK; |
wire[7:0] ADC_RAM_DATA; |
reg[10:0] ADC_RAM_ADDR; |
wire ADC_RAM_CLK; |
wire[5:0] TIME_BASE; |
reg VGA_WRITE_DONE; |
wire[10:0] TRIG_ADDR; |
|
|
//----------------------// |
// REGISTERS // |
//----------------------// |
reg[4:0] vcnt; |
reg[9:0] hcnt; |
reg[15:0] data_to_ram; |
reg[8:0] adc_data_scale; |
reg[10:0] TRIG_ADDR_buffered; |
|
|
//==================================================================// |
// FUNCTIONAL DEFINITIONS // |
//==================================================================// |
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) begin |
vcnt <= 5'd0; |
end else if(VGA_RAM_ACCESS_OK && hcnt != 10'd640) begin |
if(vcnt == 5'd24) |
vcnt <= 5'b0; |
else |
vcnt <= vcnt + 1'b1; |
end else begin |
vcnt <= 5'd0; |
end |
end |
|
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) begin |
hcnt <= 10'd0; |
end else if(VGA_RAM_ACCESS_OK) begin |
if(hcnt == 10'd640) |
hcnt <= hcnt; |
else if(vcnt == 5'd24) |
hcnt <= hcnt + 1'b1; |
else |
hcnt <= hcnt; |
end else begin |
hcnt <= 10'b0; |
end |
end |
|
/* VGA_WRITE_DONE -> BASED ON hcnt */ |
always @ (hcnt) begin |
if(hcnt == 10'd640) |
VGA_WRITE_DONE = 1'b1; |
else |
VGA_WRITE_DONE = 1'b0; |
end |
|
/* TRIG_ADDR modified */ |
always @ (TRIG_ADDR) begin |
if(TRIG_ADDR < 10'd320) |
TRIG_ADDR_buffered = (10'd2048 - 10'd1 - 10'd320) - TRIG_ADDR; |
else |
TRIG_ADDR_buffered = TRIG_ADDR; |
end |
|
|
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) begin |
ADC_RAM_ADDR <= 11'b0; |
end else if(VGA_RAM_ACCESS_OK) begin |
if((hcnt == 10'd640) || !(vcnt == 5'd24)) |
ADC_RAM_ADDR <= ADC_RAM_ADDR; |
else |
ADC_RAM_ADDR <= ADC_RAM_ADDR + 1'b1; |
end else begin |
ADC_RAM_ADDR <= TRIG_ADDR_buffered; |
end |
end |
|
always @ (ADC_RAM_DATA) begin |
adc_data_scale = ADC_RAM_DATA + (ADC_RAM_DATA>>1); |
end |
|
|
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) begin |
VGA_RAM_ADDR <= 18'b0; |
end else if(VGA_RAM_ACCESS_OK) begin |
if(hcnt == 10'd640) |
VGA_RAM_ADDR <= VGA_RAM_ADDR; |
else |
VGA_RAM_ADDR <= VGA_RAM_ADDR + 1'b1; |
end else begin |
VGA_RAM_ADDR <= 18'b0; |
end |
end |
/* |
always @ (vcnt or VGA_RAM_ACCESS_OK or adc_data_scale) begin |
if(VGA_RAM_ACCESS_OK) begin |
if(vcnt == adc_data_scale[8:4]) begin |
data_to_ram = (adc_data_scale[3:0] == 4'd0) & 16'h0001 | |
(adc_data_scale[3:0] == 4'd1) & 16'h0002 | |
(adc_data_scale[3:0] == 4'd2) & 16'h0004 | |
(adc_data_scale[3:0] == 4'd3) & 16'h0008 | |
(adc_data_scale[3:0] == 4'd4) & 16'h0010 | |
(adc_data_scale[3:0] == 4'd5) & 16'h0020 | |
(adc_data_scale[3:0] == 4'd6) & 16'h0040 | |
(adc_data_scale[3:0] == 4'd7) & 16'h0080 | |
(adc_data_scale[3:0] == 4'd8) & 16'h0100 | |
(adc_data_scale[3:0] == 4'd9) & 16'h0200 | |
(adc_data_scale[3:0] == 4'd10) & 16'h0400 | |
(adc_data_scale[3:0] == 4'd11) & 16'h0800 | |
(adc_data_scale[3:0] == 4'd12) & 16'h1000 | |
(adc_data_scale[3:0] == 4'd13) & 16'h2000 | |
(adc_data_scale[3:0] == 4'd14) & 16'h4000 | |
(adc_data_scale[3:0] == 4'd15) & 16'h8000; |
end else begin |
data_to_ram = 16'b0; |
end |
end else begin |
data_to_ram = 16'bZ; |
end |
end |
*/ |
|
always @ (vcnt or VGA_RAM_ACCESS_OK or adc_data_scale) begin |
if(VGA_RAM_ACCESS_OK) begin |
if(vcnt == adc_data_scale[8:4]) begin |
if(adc_data_scale[3:0] == 4'd0) |
data_to_ram = 16'h0001; |
else if(adc_data_scale[3:0] == 4'd1) |
data_to_ram = 16'h0002; |
else if(adc_data_scale[3:0] == 4'd2) |
data_to_ram = 16'h0004; |
else if(adc_data_scale[3:0] == 4'd3) |
data_to_ram = 16'h0008; |
else if(adc_data_scale[3:0] == 4'd4) |
data_to_ram = 16'h0010; |
else if(adc_data_scale[3:0] == 4'd5) |
data_to_ram = 16'h0020; |
else if(adc_data_scale[3:0] == 4'd6) |
data_to_ram = 16'h0040; |
else if(adc_data_scale[3:0] == 4'd7) |
data_to_ram = 16'h0080; |
else if(adc_data_scale[3:0] == 4'd8) |
data_to_ram = 16'h0100; |
else if(adc_data_scale[3:0] == 4'd9) |
data_to_ram = 16'h0200; |
else if(adc_data_scale[3:0] == 4'd10) |
data_to_ram = 16'h0400; |
else if(adc_data_scale[3:0] == 4'd11) |
data_to_ram = 16'h0800; |
else if(adc_data_scale[3:0] == 4'd12) |
data_to_ram = 16'h1000; |
else if(adc_data_scale[3:0] == 4'd13) |
data_to_ram = 16'h2000; |
else if(adc_data_scale[3:0] == 4'd14) |
data_to_ram = 16'h4000; |
else if(adc_data_scale[3:0] == 4'd15) |
data_to_ram = 16'h8000; |
else |
data_to_ram = 16'hFFFF; |
end else //end bigIF |
data_to_ram = 16'b0; |
end else begin |
data_to_ram = 16'bZ; |
end |
end |
|
/* |
always @ (vcnt or VGA_RAM_ACCESS_OK or ADC_RAM_DATA) begin |
if(VGA_RAM_ACCESS_OK) begin |
if((vcnt[3:0] == ADC_RAM_DATA[7:4]) && vcnt[4] != 1'b1) begin |
if(ADC_RAM_DATA[3:0] == 4'd0) |
data_to_ram = 16'h0001; |
else if(ADC_RAM_DATA[3:0] == 4'd1) |
data_to_ram = 16'h0002; |
else if(ADC_RAM_DATA[3:0] == 4'd2) |
data_to_ram = 16'h0004; |
else if(ADC_RAM_DATA[3:0] == 4'd3) |
data_to_ram = 16'h0008; |
else if(ADC_RAM_DATA[3:0] == 4'd4) |
data_to_ram = 16'h0010; |
else if(ADC_RAM_DATA[3:0] == 4'd5) |
data_to_ram = 16'h0020; |
else if(ADC_RAM_DATA[3:0] == 4'd6) |
data_to_ram = 16'h0040; |
else if(ADC_RAM_DATA[3:0] == 4'd7) |
data_to_ram = 16'h0080; |
else if(ADC_RAM_DATA[3:0] == 4'd8) |
data_to_ram = 16'h0100; |
else if(ADC_RAM_DATA[3:0] == 4'd9) |
data_to_ram = 16'h0200; |
else if(ADC_RAM_DATA[3:0] == 4'd10) |
data_to_ram = 16'h0400; |
else if(ADC_RAM_DATA[3:0] == 4'd11) |
data_to_ram = 16'h0800; |
else if(ADC_RAM_DATA[3:0] == 4'd12) |
data_to_ram = 16'h1000; |
else if(ADC_RAM_DATA[3:0] == 4'd13) |
data_to_ram = 16'h2000; |
else if(ADC_RAM_DATA[3:0] == 4'd14) |
data_to_ram = 16'h4000; |
else if(ADC_RAM_DATA[3:0] == 4'd15) |
data_to_ram = 16'h8000; |
else |
data_to_ram = 16'hFFFF; |
end else //end bigIF |
data_to_ram = 16'b0; |
end else begin |
data_to_ram = 16'bZ; |
end |
end |
*/ |
/* |
always @ (vcnt) begin |
if(vcnt == 5'd00 && hcnt <= 10'd319) |
data_to_ram = 16'h000F; |
else |
data_to_ram = 16'b0; |
end |
*/ |
|
assign ADC_RAM_CLK = CLK_50MHZ; |
|
assign VGA_RAM_DATA = data_to_ram; |
|
always begin |
VGA_RAM_OE = 1'b1; |
VGA_RAM_WE = 1'b0; |
VGA_RAM_CS = 1'b0; |
end |
|
|
|
|
|
|
|
|
|
|
|
|
endmodule |
/tags/rels3/TopLevel.ucf
0,0 → 1,74
NET "ADC_CLK" LOC = "D6"; |
NET "ADC_DATA<0>" LOC = "K13"; |
NET "ADC_DATA<1>" LOC = "K14"; |
NET "ADC_DATA<2>" LOC = "J13"; |
NET "ADC_DATA<3>" LOC = "J14"; |
NET "ADC_DATA<4>" LOC = "H13"; |
NET "ADC_DATA<5>" LOC = "H14"; |
NET "ADC_DATA<6>" LOC = "G12"; |
NET "ADC_DATA<7>" LOC = "F12"; |
NET "CLK_50MHZ_IN" LOC = "T9"; |
NET "H_SYNC" LOC = "R9"; |
NET "MASTER_RST" LOC = "L14"; |
NET "PS2C" LOC = "M16"; |
NET "PS2D" LOC = "M15"; |
NET "VGA_OUTPUT<1>" LOC = "T12"; |
NET "VGA_OUTPUT<2>" LOC = "R11"; |
NET "VGA_RAM_ADDR<0>" LOC = "L5"; |
NET "VGA_RAM_ADDR<1>" LOC = "N3"; |
NET "VGA_RAM_ADDR<2>" LOC = "M4"; |
NET "VGA_RAM_ADDR<3>" LOC = "M3"; |
NET "VGA_RAM_ADDR<4>" LOC = "L4"; |
NET "VGA_RAM_ADDR<5>" LOC = "G4"; |
NET "VGA_RAM_ADDR<6>" LOC = "F3"; |
NET "VGA_RAM_ADDR<7>" LOC = "F4"; |
NET "VGA_RAM_ADDR<8>" LOC = "E3"; |
NET "VGA_RAM_ADDR<9>" LOC = "E4"; |
NET "VGA_RAM_ADDR<10>" LOC = "G5"; |
NET "VGA_RAM_ADDR<11>" LOC = "H3"; |
NET "VGA_RAM_ADDR<12>" LOC = "H4"; |
NET "VGA_RAM_ADDR<13>" LOC = "J4"; |
NET "VGA_RAM_ADDR<14>" LOC = "J3"; |
NET "VGA_RAM_ADDR<15>" LOC = "K3"; |
NET "VGA_RAM_ADDR<16>" LOC = "K5"; |
NET "VGA_RAM_ADDR<17>" LOC = "L3"; |
NET "VGA_RAM_CS" LOC = "P7"; |
NET "VGA_RAM_DATA<0>" LOC = "N7"; |
NET "VGA_RAM_DATA<1>" LOC = "T8"; |
NET "VGA_RAM_DATA<2>" LOC = "R6"; |
NET "VGA_RAM_DATA<3>" LOC = "T5"; |
NET "VGA_RAM_DATA<4>" LOC = "R5"; |
NET "VGA_RAM_DATA<5>" LOC = "C2"; |
NET "VGA_RAM_DATA<6>" LOC = "C1"; |
NET "VGA_RAM_DATA<7>" LOC = "B1"; |
NET "VGA_RAM_DATA<8>" LOC = "D3"; |
NET "VGA_RAM_DATA<9>" LOC = "P8"; |
NET "VGA_RAM_DATA<10>" LOC = "F2"; |
NET "VGA_RAM_DATA<11>" LOC = "H1"; |
NET "VGA_RAM_DATA<12>" LOC = "J2"; |
NET "VGA_RAM_DATA<13>" LOC = "L2"; |
NET "VGA_RAM_DATA<14>" LOC = "P1"; |
NET "VGA_RAM_DATA<15>" LOC = "R1"; |
NET "VGA_RAM_OE" LOC = "K4"; |
NET "VGA_RAM_WE" LOC = "G3"; |
NET "V_SYNC" LOC = "T10"; |
NET "VGA_OUTPUT<0>" LOC = "R12"; |
NET "leds<0>" LOC = "K12"; |
NET "leds<1>" LOC = "P14"; |
NET "leds<2>" LOC = "L12"; |
NET "leds<3>" LOC = "N14"; |
NET "leds<4>" LOC = "P13"; |
NET "leds<5>" LOC = "N12"; |
NET "leds<6>" LOC = "P12"; |
NET "leds<7>" LOC = "P11"; |
NET "SEG_OUT<0>" LOC = "E14"; |
NET "SEG_OUT<1>" LOC = "G13"; |
NET "SEG_OUT<2>" LOC = "N15"; |
NET "SEG_OUT<3>" LOC = "P15"; |
NET "SEG_OUT<4>" LOC = "R16"; |
NET "SEG_OUT<5>" LOC = "F13"; |
NET "SEG_OUT<6>" LOC = "N16"; |
NET "SEG_SEL<0>" LOC = "D14"; |
NET "SEG_SEL<1>" LOC = "G14"; |
NET "SEG_SEL<2>" LOC = "F14"; |
NET "SEG_SEL<3>" LOC = "E13"; |
/tags/rels3/SegDriver/d_SegDriver.v
0,0 → 1,98
//================================================================== |
// File: d_MouseDriver.v |
// Version: 0.01 |
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
// Copyright Stephen Pickett, Clarke Ellis |
// April 28, 2005 |
//------------------------------------------------------------------ |
// Revisions: |
// Ver 0.01 Apr 28, 2005 Initial Release |
// |
//================================================================== |
|
module sub_SegDriver( |
CLK_50MHZ, MASTER_RST, |
DATA_IN, |
SEG_OUT, SEG_SEL |
); |
|
//==================================================================// |
// VARIABLE DEFINITIONS // |
//==================================================================// |
//----------------------// |
// INPUTS // |
//----------------------// |
input CLK_50MHZ; // System wide clock |
input MASTER_RST; // System wide reset |
input[15:0] DATA_IN; |
//----------------------// |
// OUTPUTS // |
//----------------------// |
output[6:0] SEG_OUT; |
output[3:0] SEG_SEL; |
|
//----------------------// |
// WIRES / NODES // |
//----------------------// |
wire CLK_50MHZ, MASTER_RST; |
wire[15:0] DATA_IN; |
reg [6:0] SEG_OUT; |
reg [3:0] SEG_SEL; |
|
//----------------------// |
// REGISTERS // |
//----------------------// |
wire[6:0] seg0, seg1, seg2, seg3; |
reg[7:0] clk_390kHz; |
|
//==================================================================// |
// FUNCTIONAL DEFINITIONS // |
//==================================================================// |
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) |
clk_390kHz <= 8'b0; |
else |
clk_390kHz <= clk_390kHz + 1; |
end |
|
always @ (posedge clk_390kHz[7] or posedge MASTER_RST) begin |
if(MASTER_RST == 1'b1) |
SEG_SEL <= 4'b1110; |
else begin |
SEG_SEL[3:1] <= SEG_SEL[2:0]; |
SEG_SEL[0] <= SEG_SEL[3]; |
end |
end |
|
always @ (SEG_SEL or seg0 or seg1 or seg2 or seg3) begin |
if(SEG_SEL == 4'b1110) |
SEG_OUT = seg0; |
else if(SEG_SEL == 4'b1101) |
SEG_OUT = seg1; |
else if(SEG_SEL == 4'b1011) |
SEG_OUT = seg2; |
else if(SEG_SEL == 4'b0111) |
SEG_OUT = seg3; |
else |
SEG_OUT = 7'b1111111; |
end |
|
sub_HexSeg sub_seg3( .DATA_IN(DATA_IN[15:12]), |
.SEG_OUT(seg3) |
); |
sub_HexSeg sub_seg2( .DATA_IN(DATA_IN[11:8]), |
.SEG_OUT(seg2) |
); |
sub_HexSeg sub_seg1( .DATA_IN(DATA_IN[7:4]), |
.SEG_OUT(seg1) |
); |
sub_HexSeg sub_seg0( .DATA_IN(DATA_IN[3:0]), |
.SEG_OUT(seg0) |
); |
|
endmodule |
|
|
|
|
|
/tags/rels3/SegDriver/d_HexSeg.v
0,0 → 1,146
//================================================================== |
// File: d_MouseDriver.v |
// Version: 0.01 |
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
// Copyright Stephen Pickett, Clarke Ellis |
// April 28, 2005 |
//------------------------------------------------------------------ |
// Revisions: |
// Ver 0.01 Apr 28, 2005 Initial Release |
// |
//================================================================== |
|
module sub_HexSeg( |
DATA_IN, |
SEG_OUT |
); |
|
//==================================================================// |
// VARIABLE DEFINITIONS // |
//==================================================================// |
//----------------------// |
// INPUTS // |
//----------------------// |
input[3:0] DATA_IN; |
//----------------------// |
// OUTPUTS // |
//----------------------// |
output[6:0] SEG_OUT; |
|
//----------------------// |
// WIRES / NODES // |
//----------------------// |
wire[3:0] DATA_IN; |
reg[6:0] SEG_OUT; |
|
//----------------------// |
// REGISTERS // |
//----------------------// |
|
//==================================================================// |
// FUNCTIONAL DEFINITIONS // |
//==================================================================// |
// ____ |
// 5 | 0 | 1 |
// |____| |
// 4 | 6 | 2 |
// |____| |
// 3 |
|
always @ (DATA_IN) begin |
SEG_OUT[6] = !((DATA_IN == 4'h2) | |
(DATA_IN == 4'h3) | |
(DATA_IN == 4'h4) | |
(DATA_IN == 4'h5) | |
(DATA_IN == 4'h6) | |
(DATA_IN == 4'h8) | |
(DATA_IN == 4'h9) | |
(DATA_IN == 4'hA) | |
(DATA_IN == 4'hB) | |
(DATA_IN == 4'hD) | |
(DATA_IN == 4'hE) | |
(DATA_IN == 4'hF)); |
|
SEG_OUT[5] = !((DATA_IN == 4'h0) || |
(DATA_IN == 4'h4) || |
(DATA_IN == 4'h5) || |
(DATA_IN == 4'h6) || |
(DATA_IN == 4'h8) || |
(DATA_IN == 4'h9) || |
(DATA_IN == 4'hA) || |
(DATA_IN == 4'hB) || |
(DATA_IN == 4'hC) || |
(DATA_IN == 4'hE) || |
(DATA_IN == 4'hF)); |
|
SEG_OUT[4] = !((DATA_IN == 4'h0) || |
(DATA_IN == 4'h2) || |
(DATA_IN == 4'h6) || |
(DATA_IN == 4'h8) || |
(DATA_IN == 4'hA) || |
(DATA_IN == 4'hB) || |
(DATA_IN == 4'hC) || |
(DATA_IN == 4'hD) || |
(DATA_IN == 4'hE) || |
(DATA_IN == 4'hF)); |
|
SEG_OUT[3] = !((DATA_IN == 4'h0) || |
(DATA_IN == 4'h2) || |
(DATA_IN == 4'h3) || |
(DATA_IN == 4'h5) || |
(DATA_IN == 4'h6) || |
(DATA_IN == 4'h8) || |
(DATA_IN == 4'h9) || |
(DATA_IN == 4'hB) || |
(DATA_IN == 4'hC) || |
(DATA_IN == 4'hD) || |
(DATA_IN == 4'hE)); |
|
SEG_OUT[2] = !((DATA_IN == 4'h0) || |
(DATA_IN == 4'h1) || |
(DATA_IN == 4'h3) || |
(DATA_IN == 4'h4) || |
(DATA_IN == 4'h5) || |
(DATA_IN == 4'h6) || |
(DATA_IN == 4'h7) || |
(DATA_IN == 4'h8) || |
(DATA_IN == 4'h9) || |
(DATA_IN == 4'hA) || |
(DATA_IN == 4'hB) || |
(DATA_IN == 4'hD)); |
|
SEG_OUT[1] = !((DATA_IN == 4'h0) || |
(DATA_IN == 4'h1) || |
(DATA_IN == 4'h2) || |
(DATA_IN == 4'h3) || |
(DATA_IN == 4'h4) || |
(DATA_IN == 4'h7) || |
(DATA_IN == 4'h8) || |
(DATA_IN == 4'h9) || |
(DATA_IN == 4'hA) || |
(DATA_IN == 4'hD)); |
|
SEG_OUT[0] = !((DATA_IN == 4'h0) || |
(DATA_IN == 4'h2) || |
(DATA_IN == 4'h3) || |
(DATA_IN == 4'h5) || |
(DATA_IN == 4'h6) || |
(DATA_IN == 4'h7) || |
(DATA_IN == 4'h8) || |
(DATA_IN == 4'h9) || |
(DATA_IN == 4'hA) || |
(DATA_IN == 4'hC) || |
(DATA_IN == 4'hE) || |
(DATA_IN == 4'hF)); |
|
|
end |
|
endmodule |
|
|
|
|
|
|
|