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/trunk/doc/single_port.html
1,21 → 1,21
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
<html>
<head>
<meta http-equiv="CONTENT-TYPE"
content="text/html; charset=iso-8859-1">
<title></title>
<meta name="GENERATOR" content="StarOffice/5.2 (Win32)">
<meta name="AUTHOR" content="Robert Paley">
<meta name="CREATED" content="20020728;14095738">
<meta name="CHANGEDBY" content="Robert Paley">
<meta name="CHANGED" content="20020728;15514460">
<style>
 
<!--
29,217 → 29,336
</style>
</head>
<body>
<p align="right"><font size="3"></font></p>
<h1 style="text-align: center;"><font size="4" style="font-size: 16pt;">Description
of single_port memory and test environment.</font></h1>
of single_port memory and test environment.</font></h1>
<h2>Abstract: </h2>
<p><span style="">A VHDL simulation model for an asynchronous single port
memory is described. The memory is implemented as three different architectures,
a simple one and 2 ones which are optimized for efficient use of simulator
memory. Data and address buses are unconstrained, so multiple instances
with different address and data bus widths can be implemented in one single
design. </span>A testbench is also provided.<br>
</p>
<p><span style="">A VHDL simulation model for an asynchronous static single
port memory is described. The memory is implemented as three different
architectures, a simple one and 2 ones which are optimized for efficient
use of simulator memory. Data and address buses are unconstrained, so
multiple instances with different address and data bus widths can be implemented
in one single design. </span>A testbench is also provided.<br>
</p>
<h2>Port Interface:</h2>
<table width="757" border="1" cellpadding="5" cellspacing="4">
<col width="108"> <col width="118"> <col width="483"> <thead> <tr
valign="top">
<th width="108">
<table width="100%" border="1" cellpadding="5" cellspacing="4">
<col width="108"> <col width="118"> <col width="483"> <thead>
<tr valign="top">
<th width="108" bgcolor="#cccccc">
<p>Port Name</p>
</th>
<th width="118">
</th>
<th width="118" bgcolor="#cccccc">
<p>Type</p>
</th>
<th width="483">
</th>
<th width="483" bgcolor="#cccccc">
<p>Description</p>
</th>
</tr>
</thead> <tbody>
<tr valign="top">
<td width="108">
</th>
</tr>
</thead> <tbody>
<tr valign="top">
<td width="108">
<p>rnwtQ</p>
</td>
<td width="118">
</td>
<td width="118">
<p>Time</p>
</td>
<td width="483">
<p>Time delay from rnw = read until data appears on q data bus.</p>
</td>
</tr>
<tr valign="top">
<td width="108">
</td>
<td width="483">
<p>Time delay until data or tristate appears on q data bus.</p>
</td>
</tr>
<tr valign="top">
<td width="108">
<p>d</p>
</td>
<td width="118"> STD_LOGIC_VECTOR<br>
</td>
<td width="483">
</td>
<td width="118"> STD_LOGIC_VECTOR<br>
</td>
<td width="483">
<p>Input data bus,&nbsp;unconstrained</p>
</td>
</tr>
<tr valign="top">
<td width="108">
</td>
</tr>
<tr valign="top">
<td width="108">
<p>q</p>
</td>
<td width="118">
</td>
<td width="118">
<p>STD_LOGIC_VECTOR<br>
</p>
</td>
<td width="483">
</p>
</td>
<td width="483">
<p>Output data bus,&nbsp;unconstrained</p>
</td>
</tr>
<tr valign="top">
<td width="108">
</td>
</tr>
<tr valign="top">
<td width="108">
<p>a</p>
</td>
<td width="118">
</td>
<td width="118">
<p>STD_LOGIC_VECTOR<br>
</p>
</td>
<td width="483">
</p>
</td>
<td width="483">
<p>Address bus, unconstrained</p>
</td>
</tr>
<tr valign="top">
<td width="108">
<p>rnw</p>
</td>
<td width="118">
</td>
</tr>
<tr valign="top">
<td width="108">
<p>nce</p>
</td>
<td width="118">
<p>STD_LOGIC</p>
</td>
<td width="483">
<p>Read not write port</p>
</td>
</tr>
<tr valign="top">
<td width="108">
</td>
<td width="483">
<p>not chip enable</p>
</td>
</tr>
<tr>
<td valign="top">nwe<br>
</td>
<td valign="top">STD_LOGIC<br>
</td>
<td valign="top">not write enable<br>
</td>
</tr>
<tr>
<td valign="top">noe<br>
</td>
<td valign="top">STD_LOGIC<br>
</td>
<td valign="top">not output enable<br>
</td>
</tr>
<tr valign="top">
<td width="108">
<p>dealloc_mem</p>
</td>
<td width="118">
</td>
<td width="118">
<p>BOOLEAN</p>
</td>
<td width="483">
</td>
<td width="483">
<p>When set to true, deallocate linked list memory.</p>
</td>
</tr>
</tbody>
</td>
</tr>
</tbody>
</table>
<h2>Functional Description:</h2>
<p><span style="">The first architecture is called ArrayMemNoFlag, and implements
the memory core as an array of STD_LOGIC_VECTOR. This is the simplest architecture.
It is provided for comparison with the models below but not recommended
for use in your design.<o:p></o:p></span></p>
<p><span style="">The second architecture is called ArrayMem, and implements
the memory core as an array of BIT_VECTOR. This arrangement allows less
workstation memory to be used than the ArrayMemNoFlag architecture. Use
this architecture if most addresses in the simulated memory are written
at least once.<o:p></o:p></span></p>
<span style="">The third architecture is called LinkedList, and implements
the memory core as a linked list of arrays of BIT_VECTOR. Each array in
the linked list is a page of memory whose size is specified with the constant
PAGEDEPTH in the package linked_list_mem_pkg. This arrangement allows less
workstation memory to be used than either the ArrayMemNoFlag or ArrayMem
architectures because memory representing the array data is only allocated
if the memory is actually written to. To de-allocate the memory in the linked
list, set dealloc_mem to true. Use this architecture if a significant portion
of your simulated memory (which need not be contiguous) is never written
to.<br>
<p><span style="">All 3 architectures functionally behave like commercially
available asynchronous SRAMs if you connect d and q to the same bus. </span><span
style="">If a memory location is read which was not written to during the
current simulation, 'U's are loaded onto the memory bus.</span> </p>
<table cellpadding="2" cellspacing="2" border="1" width="100%">
<tbody>
<tr>
<th valign="top" bgcolor="#cccccc">nce<br>
</th>
<th valign="top" bgcolor="#cccccc">nwe<br>
</th>
<th valign="top" bgcolor="#cccccc">noe<br>
</th>
<th valign="top" bgcolor="#cccccc">d<br>
</th>
<th valign="top" bgcolor="#cccccc">q<br>
</th>
<th valign="top" bgcolor="#cccccc">Mode<br>
</th>
</tr>
<tr>
<td valign="top">1<br>
</td>
<td valign="top">don't care<br>
</td>
<td valign="top">don't care<br>
</td>
<td valign="top">don't care<br>
</td>
<td valign="top">high Z<br>
</td>
<td valign="top">deselected<br>
</td>
</tr>
<tr>
<td valign="top">0<br>
</td>
<td valign="top">1<br>
</td>
<td valign="top">1<br>
</td>
<td valign="top">don't care<br>
</td>
<td valign="top">high Z<br>
</td>
<td valign="top">output disabled<br>
</td>
</tr>
<tr>
<td valign="top">0<br>
</td>
<td valign="top">0<br>
</td>
<td valign="top">don't care<br>
</td>
<td valign="top">input data<br>
</td>
<td valign="top">high Z<br>
</td>
<td valign="top">write<br>
</td>
</tr>
<tr>
<td valign="top">0<br>
</td>
<td valign="top">1<br>
</td>
<td valign="top">0<br>
</td>
<td valign="top">don't care<br>
</td>
<td valign="top">RAM content<br>
</td>
<td valign="top">read<br>
</td>
</tr>
</tbody>
</table>
<h3>Architecture <span style="">ArrayMemNoFlag</span></h3>
<p><span style="">This architecture implements the memory core as an array
of STD_LOGIC_VECTOR. This is the simplest architecture. It is provided
for comparison with the models below but not recommended for use in your
design.</span></p>
<p><span style=""><o:p></o:p></span></p>
<h3><span style="">Architecture </span><span style="">ArrayMem</span></h3>
<p><span style="">This architecture i</span><span style="">mplements the
memory core as an array of BIT_VECTOR. This arrangement allows less workstation
memory to be used than the ArrayMemNoFlag architecture. Use this architecture
if most addresses in the simulated memory are written at least once.<br>
<o:p></o:p></span></p>
<h3><span style="">Architecture LinkedList</span></h3>
<h3><span style=""></span></h3>
<span style="">This architecture implements the memory core as a linked
list of arrays of BIT_VECTOR. Each array in the linked list is a page
of memory whose size is specified with the constant PAGEDEPTH in the package
linked_list_mem_pkg. This arrangement allows less workstation memory
to be used than either the ArrayMemNoFlag or ArrayMem architectures because
memory representing the array data is only allocated if the memory is
actually written to. To de-allocate the memory in the linked list, set
dealloc_mem to true. A short pulse is sufficient. Use this architecture
if a significant portion of your simulated memory (which need not be
contiguous) is never written to.</span>
<h2>Example Timing:</h2>
<p><span style="">Clearing both nce and nwe to to '0' immediately causes
a write operation. Changing the address while nce and nwe are asserted causes
a write to the new address, too (But don't do that with real RAMs because
you could destroy more memory locations while the address bus settles).
Every read (and tristate) operation is delayed rnwtQ ns. The below sample
timing diagram illustrates both a read and write operation.</span></p>
<p><img src="../images/timing.png" alt="Timing diagram" width="752"
height="515">
<br>
All 3 architectures are asynchronous and triggered with any change of </span><span
style="">d, a or rnw</span> (and dealloc_mem for the LinkedList architecture).
<span style="">When rnw = '0', the data on bus "d" is loaded into the memory
at the location specified by the addres bus "a". When rnw = '1', the data
located in memory address "a" is loaded onto the output data bus "q". If
a memory location is read which was not written to during the current simulation,
'U's are loaded onto the memory bus.</span><br>
<h2>Functional Timing:</h2>
<p><span style="">The single port memory is asynchronous and is triggered
on any change of d, a or rnw. When rnw is cleared to '0', the write occurs
at the same time as rnw'transaction. When a read occurs, with rnw = '1'
, data appears on the Q bus rnwtQ ns after rnw is set to '1'. The below
sample timing diagram illustrates both a read and write operation.</span><br>
</p>
<p><img src="../images/timing.jpg" name="Graphic1" align="left"
width="958" height="251" border="0">
<br clear="left">
</p>
</p>
<h2>Testbench Description:</h2>
<p>The test bench is arranged as a client server architecture as specified
by Bergeron<a class="sdfootnoteanc" name="sdfootnote1anc"
by Bergeron<a class="sdfootnoteanc" name="sdfootnote1anc"
href="#sdfootnote1sym"><sup>1</sup></a>. A diagram illustrating the testbench
is given below.<br>
<br>
<img src="../images/tbschematic.jpg" name="Graphic2" align="left"
width="838" height="371" border="0">
<br clear="left">
Two tests are specified in tc_single_port component. The first test writes
data to two logical memory pages, and then reads them back verifying the
correct data. The test case writes an error message to the console for every
miscompare. The second case verifies that the single_port memory model outputs
unknowns to the q bus if a read occurs for an unwritten memory location.
Six configurations are specified in the test bench architecture tb_single_port,
running both tests for each single_port architecture. <br>
</p>
is given below.</p>
<p><img src="../images/tbschematic.png" alt="Testbench schematic"
width="712" height="244">
&nbsp; <br clear="left">
Two tests are specified in tc_single_port component. The first test
writes data to two logical memory pages, and then reads them back verifying
the correct data. The test case writes an error message to the console
for every miscompare. The second case verifies that the single_port memory
model outputs unknowns to the q bus if a read occurs for an unwritten memory
location. Six configurations are specified in the test bench architecture
tb_single_port, running both tests for each single_port architecture. <br>
</p>
<h2>Usage:</h2>
<p>A Makefile is used to compile and run all of the tests in a Unix or like
environment, such as Cygwin. The compilation and simulation is targetted
to the SymphonyEDA tool available at <a
environment, such as Cygwin. The compilation and simulation is targetted
to the SymphonyEDA tool available at <a
href="http://www.symphonyeda.com">www.symphonyeda.com</a>.</p>
<p>The source files and Makefile are located in {top}/VHDL<br>
<br>
To compile: make com</p>
<br>
To compile: make com</p>
<p>To simulate all of the tests: make sim<br>
</p>
</p>
<p>To clean the compiled library: make clean</p>
<p>The tests are labeled :</p>
<ul>
<li>ll_error</li>
<li>ll_main</li>
<li>mem_main<br>
</li>
<li>mem_error<br>
</li>
<li>memnoflag_main<br>
</li>
<li>memnoflag_error<br>
</li>
<li>ll_error</li>
<li>ll_main</li>
<li>mem_main<br>
</li>
<li>mem_error<br>
</li>
<li>memnoflag_main<br>
</li>
<li>memnoflag_error<br>
</li>
</ul>
<p>To simulate any of these tests, type make {testname}</p>
<p>Please contact Robert Paley at <a href="mailto:rpaley_yid@yahoo.com">rpaley_yid@opencores.org</a>
or Michael Geng at <a href="mailto:vhdl@michaelgeng.de">vhdl@michaelgeng.de</a>
if you have any questions or comments. </p>
<div id="sdfootnote1">
or Michael Geng at <a href="mailto:vhdl@michaelgeng.de">vhdl@michaelgeng.de</a>
if you have any questions or comments. </p>
<div id="sdfootnote1">
<p class="sdfootnote" style="margin-bottom: 0.2in;"><a
class="sdfootnotesym" name="sdfootnote1sym" href="#sdfootnote1anc">1</a>Writing
Testbenches , Functional Verification of HDL Testbenches. Chapter 6 &#8211; ISBN
0-7923-7766-4</p>
</div>
Testbenches , Functional Verification of HDL Testbenches. Chapter 6 &#8211;
ISBN 0-7923-7766-4<br>
</p>
</div>
<br>
<br>
<br>
/trunk/images/timing.dia Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/images/timing.dia
trunk/images/timing.dia Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/images/tbschematic.fig =================================================================== --- trunk/images/tbschematic.fig (nonexistent) +++ trunk/images/tbschematic.fig (revision 13) @@ -0,0 +1,62 @@ +#FIG 3.2 Produced by xfig version 3.2.5-alpha5 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 1 1 1.00 60.00 120.00 + 8325 540 6300 540 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 1 1 1.00 60.00 120.00 + 6300 225 8325 225 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 1 1 1.00 60.00 120.00 + 6300 855 8325 855 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 1 1 1.00 60.00 120.00 + 6300 1170 8325 1170 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 1 1 1.00 60.00 120.00 + 6300 1485 8325 1485 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 1 1 1.00 60.00 120.00 + 6300 1800 8325 1800 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 1 1 1.00 60.00 120.00 + 6300 2115 8325 2115 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 5490 450 6030 450 6030 2925 5490 2925 5490 450 +2 2 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5 + 3375 0 6300 0 6300 3375 3375 3375 3375 0 +2 2 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5 + 8325 0 10125 0 10125 2340 8325 2340 8325 0 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 1 1 1.00 60.00 120.00 + 3375 270 2025 270 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 1 1 1.00 60.00 120.00 + 2025 855 3375 855 +2 2 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5 + 0 0 2025 0 2025 1125 0 1125 0 0 +4 1 0 50 -1 0 16 1.5708 4 255 2070 5805 1710 single_port_server\001 +4 0 0 50 -1 1 16 0.0000 4 195 465 3645 1440 Test\001 +4 0 0 50 -1 1 16 0.0000 4 195 945 3645 1755 Harness\001 +4 0 0 50 -1 1 16 0.0000 4 270 1575 3645 2070 tb_single_port\001 +4 0 0 50 -1 0 16 0.0000 4 195 600 3600 405 Arch\001 +4 0 0 50 -1 0 16 0.0000 4 255 1455 8505 1350 (single_port)\001 +4 0 0 50 -1 0 16 0.0000 4 195 570 8505 945 DUT\001 +4 1 0 50 -1 0 16 0.0000 4 195 135 7290 495 q\001 +4 1 0 50 -1 0 16 0.0000 4 195 135 7290 180 d\001 +4 1 0 50 -1 0 16 0.0000 4 135 120 7290 810 a\001 +4 1 0 50 -1 0 16 0.0000 4 135 390 7290 1125 nce\001 +4 1 0 50 -1 0 16 0.0000 4 135 450 7290 1440 nwe\001 +4 1 0 50 -1 0 16 0.0000 4 135 405 7290 1755 noe\001 +4 1 0 50 -1 0 16 0.0000 4 255 1485 7290 2070 dealloc_mem\001 +4 1 0 50 -1 0 16 0.0000 4 255 900 2700 180 frm_srv\001 +4 1 0 50 -1 0 16 0.0000 4 225 705 2700 765 to_srv\001 +4 0 0 50 -1 0 16 0.0000 4 255 1590 225 765 tc_single_port\001 +4 0 0 50 -1 0 16 0.0000 4 195 960 225 450 Testcase\001 Index: trunk/VHDL/single_port.vhd =================================================================== --- trunk/VHDL/single_port.vhd (revision 12) +++ trunk/VHDL/single_port.vhd (revision 13) @@ -56,6 +56,9 @@ -- CVS Revision History -- -- $Log: not supported by cvs2svn $ +-- Revision 1.3 2005/10/25 18:26:52 mgeng +-- PAGENUM constant removed because the address bus width provides this information +-- -- Revision 1.2 2005/10/12 19:39:27 mgeng -- Buses unconstrained, LGPL header added -- @@ -78,24 +81,31 @@ GENERIC ( rnwtQ : TIME := 1 NS); PORT ( - d : IN STD_LOGIC_VECTOR; - q : OUT STD_LOGIC_VECTOR; - a : IN STD_LOGIC_VECTOR; - rnw : IN STD_LOGIC; - dealloc_mem : IN BOOLEAN := FALSE); + d : IN STD_LOGIC_VECTOR; -- data bus input + q : OUT STD_LOGIC_VECTOR; -- data bus output + a : IN STD_LOGIC_VECTOR; -- address bus + nce : IN STD_LOGIC; -- not chip enable + nwe : IN STD_LOGIC; -- not write enable + noe : IN STD_LOGIC; -- not output enable + dealloc_mem : IN BOOLEAN := FALSE); -- control signal for deallocating memory, + -- only used in the linked list implementation END ENTITY single_port; ARCHITECTURE ArrayMemNoFlag OF single_port IS BEGIN - mem_proc : PROCESS(d, a, rnw) + mem_proc : PROCESS(d, a, nce, nwe, noe) TYPE mem_typ IS ARRAY ( 0 TO 2**a'length-1 ) OF STD_LOGIC_VECTOR(d'RANGE); VARIABLE mem : mem_typ; BEGIN - IF ( rnw = '0') THEN -- Write + IF ( nce = '0' ) AND ( nwe = '0' ) THEN -- Write mem(TO_INTEGER(unsigned(a))) := d; - ELSE -- Read + END IF; + + IF ( nce = '0' ) AND ( noe = '0' ) THEN -- Read q <= mem(TO_INTEGER(unsigned(a))) AFTER rnwtQ; + ELSE + q <= (q'RANGE => 'Z') AFTER rnwtQ; END IF; END PROCESS mem_proc; @@ -104,22 +114,26 @@ ARCHITECTURE ArrayMem OF single_port IS BEGIN - mem_proc : PROCESS(d, a, rnw) + mem_proc : PROCESS(d, a, nce, nwe, noe) TYPE mem_typ IS ARRAY ( 0 TO 2**a'length-1 ) OF BIT_VECTOR(d'RANGE); TYPE flag_typ IS ARRAY ( 0 TO 2**a'length-1 ) OF BOOLEAN; VARIABLE mem : mem_typ; VARIABLE flag : flag_typ; BEGIN - IF ( rnw = '0') THEN -- Write - mem(TO_INTEGER(unsigned(a))) := TO_BITVECTOR(d); + IF ( nce = '0' ) AND ( nwe = '0' ) THEN -- Write + mem( TO_INTEGER(unsigned(a))) := TO_BITVECTOR(d); flag(TO_INTEGER(unsigned(a))) := true; -- set valid memory location flag - ELSE -- read data, either valid or 'U' - IF ( flag(TO_INTEGER(unsigned(a))) = true ) THEN + END IF; + + IF ( nce = '0' ) AND ( noe = '0' ) THEN -- Read + IF ( flag(TO_INTEGER(unsigned(a))) = true ) THEN -- read data, either valid or 'U' q <= TO_STDLOGICVECTOR(mem(TO_INTEGER(unsigned(a)))) AFTER rnwtQ; ELSE -- reading invalid memory location - q <= (q'RANGE => 'U') after rnwtQ; + q <= (q'RANGE => 'U') AFTER rnwtQ; END IF; - END IF; + ELSE + q <= (q'RANGE => 'Z') AFTER rnwtQ; + END IF; END PROCESS mem_proc; END ArrayMem; @@ -128,7 +142,7 @@ CONSTANT READ_MEM : BOOLEAN := false; BEGIN - mem_proc : PROCESS(d, a, rnw, dealloc_mem) + mem_proc : PROCESS(d, a, nce, nwe, noe, dealloc_mem) VARIABLE mem_page_v : mem_page_ptr; VARIABLE d_v : STD_LOGIC_VECTOR(d'RANGE); VARIABLE a_v : addr_typ; @@ -136,21 +150,24 @@ IF NOT dealloc_mem THEN d_v := d; a_v := TO_INTEGER(unsigned(a)); - IF ( rnw = '0' ) THEN -- write to linked list memory + IF ( nce = '0' ) AND ( nwe = '0' ) THEN -- Write rw_mem( data => d_v, addr => a_v, next_cell => mem_page_v, write_flag => WRITE_MEM); - ELSE -- read from linked list memory + END IF; + + IF ( nce = '0' ) AND ( noe = '0' ) THEN -- Read rw_mem( data => d_v, addr => a_v, next_cell => mem_page_v, write_flag => READ_MEM); - q <= d_v after rnwtQ; + q <= d_v AFTER rnwtQ; + ELSE + q <= (q'RANGE => 'Z') AFTER rnwtQ; END IF; ELSE -- Deallocate memory from work station memory. deallocate_mem(mem_page_v); END IF; END PROCESS mem_proc; - END LinkedList;
/trunk/VHDL/tb_single_port.vhd
49,6 → 49,9
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.2 2005/10/12 19:39:27 mgeng
-- Buses unconstrained, LGPL header added
--
-- Revision 1.1.1.1 2003/01/14 21:48:11 rpaley_yid
-- initial checkin
--
80,7 → 83,9
d : IN STD_LOGIC_VECTOR;
q : OUT STD_LOGIC_VECTOR;
a : IN STD_LOGIC_VECTOR;
rnw : IN STD_LOGIC;
nce : IN STD_LOGIC;
nwe : IN STD_LOGIC;
noe : IN STD_LOGIC;
dealloc_mem : BOOLEAN);
END COMPONENT single_port;
 
92,14 → 97,14
CONSTANT DATA_WIDTH : INTEGER := 32;
CONSTANT ADDR_WIDTH : INTEGER := 16;
 
SIGNAL d : STD_LOGIC_VECTOR(DATA_WIDTH - 1 DOWNTO 0);
SIGNAL q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 DOWNTO 0);
SIGNAL a : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
SIGNAL rnw : STD_LOGIC;
SIGNAL dealloc_mem : BOOLEAN;
SIGNAL to_srv : to_srv_typ;
SIGNAL frm_srv : STD_LOGIC_VECTOR(d'RANGE);
SIGNAL tie_vdd : STD_LOGIC := '1';
SIGNAL d : STD_LOGIC_VECTOR(DATA_WIDTH - 1 DOWNTO 0);
SIGNAL q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 DOWNTO 0);
SIGNAL a : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
SIGNAL nce, nwe, noe : STD_LOGIC;
SIGNAL dealloc_mem : BOOLEAN;
SIGNAL to_srv : to_srv_typ;
SIGNAL frm_srv : STD_LOGIC_VECTOR(d'RANGE);
SIGNAL tie_vdd : STD_LOGIC := '1';
BEGIN
dut : single_port
PORT MAP (
106,7 → 111,9
d => d,
a => a,
q => q,
rnw => rnw,
nce => nce,
nwe => nwe,
noe => noe,
dealloc_mem => dealloc_mem);
 
tc : tc_single_port
128,13 → 135,17
WHEN read => -- perform memory read
d <= STD_LOGIC_VECTOR(TO_SIGNED(to_srv.data, d'length));
a <= STD_LOGIC_VECTOR(TO_UNSIGNED(to_srv.addr, a'length));
rnw <= '1';
nce <= '0';
noe <= '0';
nwe <= '1';
-- Wait for data to appear
WAIT FOR ACCESS_DELAY;
WHEN write => -- perform memory write
d <= STD_LOGIC_VECTOR(TO_SIGNED(to_srv.data, d'length));
a <= STD_LOGIC_VECTOR(TO_UNSIGNED(to_srv.addr, a'length));
rnw <= '0';
nce <= '0';
noe <= '1';
nwe <= '0';
WAIT FOR ACCESS_DELAY;
WHEN dealloc => -- deallocate the linked list for the LL architecture
dealloc_mem <= true;

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