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Rev 12 → Rev 13

/trunk/bench/verilog/can_testbench_defines.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2003/01/08 02:09:44 mohor
// Acceptance filter added.
//
// Revision 1.3 2002/12/28 04:13:53 mohor
// Backup version.
//
71,4 → 74,4
`define CAN_TIMING1_SAM 1'h0 // Triple sampling
 
// Clock Divider register
`define CAN_CLOCK_DIVIDER_MODE 1'h1 // Normal (not extended mode
`define CAN_CLOCK_DIVIDER_MODE 1'h0 // 0 - Normal mode, 1 - Extended mode
/trunk/rtl/verilog/can_fifo.v
45,9 → 45,12
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2003/01/08 02:10:55 mohor
// Acceptance filter added.
//
//
//
//
 
// synopsys translate_off
`include "timescale.v"
61,15 → 64,13
 
rd,
wr,
wr_length_info,
 
data_in,
data_out,
 
reset_mode,
release_buffer,
extended_mode
release_buffer
 
);
 
parameter Tp = 1;
78,42 → 79,95
input rst;
input rd;
input wr;
input wr_length_info;
input [7:0] data_in;
input reset_mode;
input release_buffer;
input extended_mode;
 
output [7:0] data_in;
output [7:0] data_out;
 
 
reg [7:0] fifo [0:63];
reg [5:0] rd_pointer;
reg [5:0] wr_pointer;
reg [3:0] length_info[0:6];
reg overrun_info[0:6];
 
reg [3:0] length_info[0:31];
reg [4:0] wr_info_pointer;
reg [4:0] rd_info_pointer;
reg overrun_info[0:31];
reg wr_q;
reg [3:0] len_cnt;
 
wire write_length_info;
 
 
assign write_length_info = (~wr) & wr_q;
 
// Delayed write signal
always @ (posedge clk or posedge rst)
begin
if (rst)
wr_q <= 0;
else if (reset_mode)
wr_q <=#Tp 0;
else
wr_q <=#Tp wr;
end
 
 
// length counter
always @ (posedge clk or posedge rst)
begin
if (rst)
len_cnt <= 0;
else if (reset_mode | write_length_info)
len_cnt <=#Tp 1'b0;
else if (wr)
len_cnt <=#Tp len_cnt + 1'b1;
end
 
 
// wr_info_pointer
always @ (posedge clk or posedge rst)
begin
if (rst)
wr_info_pointer <= 0;
else if (reset_mode)
wr_info_pointer <=#Tp 0;
else if (write_length_info)
wr_info_pointer <=#Tp wr_info_pointer + 1'b1;
end
 
 
// length_info
always @ (posedge clk)
begin
if (write_length_info)
length_info[wr_info_pointer] <=#Tp len_cnt;
end
 
 
// rd_info_pointer
always @ (posedge clk or posedge rst)
begin
if (rst)
length_info <= 0;
else if (wr_length_info)
length_info <=#Tp data_in;
rd_info_pointer <= 0;
else if (reset_mode)
length_info <=#Tp 0;
rd_info_pointer <=#Tp 0;
else if (release_buffer)
rd_info_pointer <=#Tp rd_info_pointer + 1'b1;
end
 
 
 
 
 
// rd_pointer
always @ (posedge clk or posedge rst)
begin
if (rst)
rd_pointer <= 0;
else if (rd)
rd_pointer <=#Tp rd_pointer + length_info;
else if (release_buffer)
rd_pointer <=#Tp rd_pointer + length_info[rd_info_pointer];
else if (reset_mode)
rd_pointer <=#Tp 0;
end
125,7 → 179,7
if (rst)
wr_pointer <= 0;
else if (wr)
wr_pointer <=#Tp wd_pointer + 1'b1;
wr_pointer <=#Tp wr_pointer + 1'b1;
else if (reset_mode)
wr_pointer <=#Tp 0;
end
138,9 → 192,9
fifo[wr_pointer] <=#Tp data_in;
end
 
assign data_out = fifo[rd_pointer];
 
 
 
 
 
endmodule
/trunk/rtl/verilog/can_bsp.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2003/01/08 13:30:31 mohor
// Temp version.
//
// Revision 1.4 2003/01/08 02:10:53 mohor
// Acceptance filter added.
//
692,131 → 695,121
 
 
 
reg [3:0] wr_fifo_cnt; // Counting the data written in FIFO
reg [3:0] data_cnt; // Counting the data bytes that are written to FIFO
reg [2:0] header_cnt; // Counting header length
reg wr_fifo; // Write data and header to 64-byte fifo
reg [7:0] data_for_fifo; // Multiplexed data that is stored to 64-byte fifo
 
reg wr_fifo_normal_mode; // Write fifo when in normal mode (clock divider register)
reg wr_fifo_ext_mode_std; // Write fifo when in extended mode (clock divider register) and receiving standard format msg
reg wr_fifo_ext_mode_ext; // Write fifo when in extended mode (clock divider register) and receiving extended format msg
 
wire reset_wr_fifo_normal_mode;
wire [2:0] header_len;
wire storing_header;
wire data_cnt_en;
wire [3:0] limited_data_len;
wire reset_wr_fifo_normal_mode;
 
wire [3:0] total_rx_byte = (data_len < 8)? data_len : 4'h8;
assign header_len[2:0] = extended_mode ? (ide? (3'h5) : (3'h3)) : 3'h2; // + 1 because data_cnt need to start with 0
assign storing_header = header_cnt < header_len;
assign data_cnt_en = header_cnt == header_len;
assign limited_data_len[3:0] = (data_len < 8)? (data_len -1'b1) : 4'h7; // - 1 because counter counts from 0
assign reset_wr_fifo_normal_mode = data_cnt == limited_data_len;
 
 
// Write enable signal for 64-byte rx fifo
always @ (posedge clk or posedge rst)
begin
if (rst)
wr_fifo <= 1'b0;
if (go_rx_ack_lim & (~extended_mode) & id_ok & (~crc_error))
wr_fifo <=#Tp 1'b1;
else if (reset_wr_fifo_normal_mode)
wr_fifo <=#Tp 1'b0;
end
 
 
 
assign reset_wr_fifo_normal_mode = wr_fifo_cnt == (1'b1 + total_rx_byte);
 
// Header counter. Header length depends on the mode of operation and frame format.
always @ (posedge clk or posedge rst)
begin
if (rst)
wr_fifo_normal_mode <= 1'b0;
if (go_rx_ack_lim & (~extended_mode) & id_ok & (~crc_error))
wr_fifo_normal_mode <=#Tp 1'b1;
header_cnt <= 0;
if (wr_fifo)
header_cnt <=#Tp header_cnt + 1;
else if (reset_wr_fifo_normal_mode)
wr_fifo_normal_mode <=#Tp 1'b0;
header_cnt <=#Tp 0;
end
 
 
// Data counter. Length of the data is limited to 8 bytes.
always @ (posedge clk or posedge rst)
begin
if (rst)
wr_fifo_cnt <= 0;
if (wr_fifo_normal_mode)
wr_fifo_cnt <=#Tp wr_fifo_cnt + 1;
data_cnt <= 0;
if (data_cnt_en)
data_cnt <=#Tp data_cnt + 1;
else if (reset_wr_fifo_normal_mode)
wr_fifo_cnt <=#Tp 0;
data_cnt <=#Tp 0;
end
 
 
reg [7:0] data_for_fifo;
always @ (extended_mode or ide or tmp_fifo or wr_fifo_cnt)
// Multiplexing data that is stored to 64-byte fifo depends on the mode of operation and frame format
always @ (extended_mode or ide or data_cnt or header_cnt or storing_header or id or rtr1 or rtr2 or data_len or
tmp_fifo[0] or tmp_fifo[2] or tmp_fifo[4] or tmp_fifo[6] or
tmp_fifo[1] or tmp_fifo[3] or tmp_fifo[5] or tmp_fifo[7])
begin
if (extended_mode) // extended mode
if (storing_header)
begin
if (ide) // extended format
if (extended_mode) // extended mode
begin
case (wr_fifo_cnt) // synopsys parallel_case synopsys full_case
4'h0 : data_for_fifo <= {1'b1, rtr2, 2'h0, data_len};
4'h1 : data_for_fifo <= id[28:21];
4'h2 : data_for_fifo <= id[20:13];
4'h3 : data_for_fifo <= id[12:5];
4'h4 : data_for_fifo <= {id[4:0], 3'h0};
4'h5 : data_for_fifo <= tmp_fifo[0];
4'h6 : data_for_fifo <= tmp_fifo[1];
4'h7 : data_for_fifo <= tmp_fifo[2];
4'h8 : data_for_fifo <= tmp_fifo[3];
4'h9 : data_for_fifo <= tmp_fifo[4];
4'hA : data_for_fifo <= tmp_fifo[5];
4'hB : data_for_fifo <= tmp_fifo[6];
4'hC : data_for_fifo <= tmp_fifo[7];
endcase
if (ide) // extended format
begin
case (header_cnt) // synopsys parallel_case synopsys full_case
4'h0 : data_for_fifo <= {1'b1, rtr2, 2'h0, data_len};
4'h1 : data_for_fifo <= id[28:21];
4'h2 : data_for_fifo <= id[20:13];
4'h3 : data_for_fifo <= id[12:5];
4'h4 : data_for_fifo <= {id[4:0], 3'h0};
endcase
end
else // standard format
begin
case (header_cnt) // synopsys parallel_case synopsys full_case
4'h0 : data_for_fifo <= {1'b0, rtr1, 2'h0, data_len};
4'h1 : data_for_fifo <= id[10:3];
4'h2 : data_for_fifo <= {id[2:0], 5'h0};
endcase
end
end
else // standard format
else // normal mode
begin
case (wr_fifo_cnt) // synopsys parallel_case synopsys full_case
4'h0 : data_for_fifo <= {1'b0, rtr1, 2'h0, data_len};
4'h1 : data_for_fifo <= id[10:3];
4'h2 : data_for_fifo <= {id[2:0], 5'h0};
4'h3 : data_for_fifo <= tmp_fifo[0];
4'h4 : data_for_fifo <= tmp_fifo[1];
4'h5 : data_for_fifo <= tmp_fifo[2];
4'h6 : data_for_fifo <= tmp_fifo[3];
4'h7 : data_for_fifo <= tmp_fifo[4];
4'h8 : data_for_fifo <= tmp_fifo[5];
4'h9 : data_for_fifo <= tmp_fifo[6];
4'hA : data_for_fifo <= tmp_fifo[7];
case (header_cnt) // synopsys parallel_case synopsys full_case
4'h0 : data_for_fifo <= id[10:3];
4'h1 : data_for_fifo <= {id[2:0], rtr1, data_len};
endcase
end
end
else // normal mode
begin
case (wr_fifo_cnt) // synopsys parallel_case synopsys full_case
4'h0 : data_for_fifo <= id[10:3];
4'h1 : data_for_fifo <= {id[2:0], rtr1, data_len};
4'h2 : data_for_fifo <= tmp_fifo[0];
4'h3 : data_for_fifo <= tmp_fifo[1];
4'h4 : data_for_fifo <= tmp_fifo[2];
4'h5 : data_for_fifo <= tmp_fifo[3];
4'h6 : data_for_fifo <= tmp_fifo[4];
4'h7 : data_for_fifo <= tmp_fifo[5];
4'h8 : data_for_fifo <= tmp_fifo[6];
4'h9 : data_for_fifo <= tmp_fifo[7];
endcase
end
else
data_for_fifo <= tmp_fifo[data_cnt];
end
 
/*
always @ (posedge clk or posedge rst)
begin
if (write_data_to_tmp_fifo)
tmp_fifo[byte_cnt] <=#Tp tmp_data;
end
 
 
 
// Instantiation of the RX fifo module
can_fifo i_can_fifo;
can_fifo i_can_fifo
(
.clk(clk),
.rst(rst),
 
.rd(rd),
.wr(wr),
.wr_length_info(wr_length_info),
.rd(1'b0), // FIX ME
.wr(wr_fifo),
 
.data_in(data_in),
.data_out(data_out),
.data_in(data_for_fifo),
.data_out(),
 
.reset_mode(reset_mode),
.release_buffer(release_buffer),
.release_buffer(1'b0) // FIX ME
 
// Clock Divider register
.extended_mode(extended_mode)
);
*/
 
 
 
824,4 → 817,5
 
 
 
 
endmodule
/trunk/rtl/verilog/can_registers.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2003/01/08 02:10:55 mohor
// Acceptance filter added.
//
// Revision 1.3 2002/12/27 00:12:52 mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
432,18 → 435,5
 
 
 
/*
module can_register
( data_in,
data_out,
we,
clk,
rst,
rst_sync
);
 
parameter WIDTH = 8; // default parameter of the register width
parameter RESET_VALUE = 0;
*/
 
endmodule
/trunk/sim/rtl_sim/run/wave.do
116,8 → 116,8
define variable nofullpathfilenames
include bookmark with filenames
include scope history without filenames
define waveform window listpane 9.97
define waveform window namepane 10.99
define waveform window listpane 9
define waveform window namepane 10
define multivalueindication
define pattern curpos dot
define pattern cursor1 dot
210,15 → 210,22
 
add group \
can_bsp \
can_testbench.i_can_top.i_can_bsp.acceptance_code_0[7:0]'h \
can_testbench.i_can_top.i_can_bsp.acceptance_code_1[7:0]'h \
can_testbench.i_can_top.i_can_bsp.acceptance_code_2[7:0]'h \
can_testbench.i_can_top.i_can_bsp.acceptance_code_3[7:0]'h \
can_testbench.i_can_top.i_can_bsp.acceptance_filter_mode \
can_testbench.i_can_top.i_can_bsp.acceptance_mask_0[7:0]'h \
can_testbench.i_can_top.i_can_bsp.acceptance_mask_1[7:0]'h \
can_testbench.i_can_top.i_can_bsp.acceptance_mask_2[7:0]'h \
can_testbench.i_can_top.i_can_bsp.acceptance_mask_3[7:0]'h \
can_testbench.i_can_top.i_can_bsp.bit_cnt[5:0]'h \
can_testbench.i_can_top.i_can_bsp.bit_de_stuff \
can_testbench.i_can_top.i_can_bsp.bit_de_stuff_reset \
can_testbench.i_can_top.i_can_bsp.bit_de_stuff_set \
can_testbench.i_can_top.i_can_bsp.bit_de_stuff_reset \
can_testbench.i_can_top.i_can_bsp.bit_stuff_cnt[2:0]'h \
can_testbench.i_can_top.i_can_bsp.bit_stuff_cnt_en \
can_testbench.i_can_top.i_can_bsp.bit_stuff_cnt[2:0]'h \
can_testbench.i_can_top.i_can_bsp.byte_cnt[2:0]'h \
can_testbench.i_can_top.i_can_bsp.tmp_data[7:0]'h \
can_testbench.i_can_top.i_can_bsp.write_data_to_tmp_fifo \
can_testbench.i_can_top.i_can_bsp.calculated_crc[14:0]'h \
can_testbench.i_can_top.i_can_bsp.clk \
can_testbench.i_can_top.i_can_bsp.crc_enable \
226,6 → 233,7
can_testbench.i_can_top.i_can_bsp.crc_in[14:0]'h \
can_testbench.i_can_top.i_can_bsp.data_len[3:0]'h \
can_testbench.i_can_top.i_can_bsp.eof_cnt[2:0]'h \
can_testbench.i_can_top.i_can_bsp.extended_mode \
can_testbench.i_can_top.i_can_bsp.go_crc_enable \
can_testbench.i_can_top.i_can_bsp.go_rx_ack \
can_testbench.i_can_top.i_can_bsp.go_rx_ack_lim \
242,13 → 250,16
can_testbench.i_can_top.i_can_bsp.go_rx_r1 \
can_testbench.i_can_top.i_can_bsp.go_rx_rtr1 \
can_testbench.i_can_top.i_can_bsp.go_rx_rtr2 \
can_testbench.i_can_top.i_can_bsp.hard_sync \
can_testbench.i_can_top.i_can_bsp.id[28:0]'h \
can_testbench.i_can_top.i_can_bsp.id_ok \
can_testbench.i_can_top.i_can_bsp.ide \
can_testbench.i_can_top.i_can_bsp.no_data \
can_testbench.i_can_top.i_can_bsp.reset_mode \
can_testbench.i_can_top.i_can_bsp.reset_mode_q \
can_testbench.i_can_top.i_can_bsp.reset_wr_fifo_normal_mode \
can_testbench.i_can_top.i_can_bsp.resync \
can_testbench.i_can_top.i_can_bsp.rst \
can_testbench.i_can_top.i_can_btl.rx \
can_testbench.i_can_top.i_can_bsp.bit_de_stuff \
can_testbench.i_can_top.i_can_bsp.rst_crc_enable \
can_testbench.i_can_top.i_can_bsp.rtr1 \
can_testbench.i_can_top.i_can_bsp.rtr2 \
271,6 → 282,18
can_testbench.i_can_top.i_can_bsp.sampled_bit \
can_testbench.i_can_top.i_can_bsp.sampled_bit_q \
can_testbench.i_can_top.i_can_bsp.stuff_error \
can_testbench.i_can_top.i_can_bsp.tmp_data[7:0]'h \
can_testbench.i_can_top.i_can_bsp.go_rx_ack_lim \
can_testbench.i_can_top.i_can_bsp.id_ok \
can_testbench.i_can_top.i_can_bsp.crc_error \
can_testbench.i_can_top.i_can_bsp.extended_mode \
can_testbench.i_can_top.i_can_bsp.header_cnt[2:0]'h \
can_testbench.i_can_top.i_can_bsp.data_cnt[3:0]'h \
can_testbench.i_can_top.i_can_bsp.data_for_fifo[7:0]'h \
can_testbench.i_can_top.i_can_bsp.wr_fifo \
can_testbench.i_can_top.i_can_bsp.storing_header \
can_testbench.i_can_top.i_can_bsp.header_len[2:0]'h \
can_testbench.i_can_top.i_can_bsp.write_data_to_tmp_fifo \
 
add group \
testbench \
283,9 → 306,6
can_testbench.send_frame.mode \
 
add group \
rx_crc \
 
add group \
can_registers \
can_testbench.i_can_top.i_can_registers.acceptance_code_0[7:0]'h \
can_testbench.i_can_top.i_can_registers.acceptance_code_1[7:0]'h \
337,5 → 357,4
 
 
deselect all
open window waveform 1 geometry 10 59 1592 1140
zoom at 58404.15(0)ns 0.00012325 0.00000000
open window designbrowser 1 geometry 56 117 855 550
/trunk/sim/rtl_sim/bin/rtl_file_list
7,4 → 7,5
can_top.v
can_bsp.v
can_crc.v
can_acf.v
can_acf.v
can_fifo.v

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