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    from Rev 12 to Rev 13
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Rev 12 → Rev 13

/trunk/imp/cfft1024X12.vhd
31,7 → 31,7
-- clk : main clk -- I have test 90M with Xilinx virtex600E
-- rst : globe reset -- '1' for reset
-- start : start fft -- one clock '1' before data input
-- inv : '0' for fft and '1' for ifft, it is sampled when start is '1'
-- invert : '0' for fft and '1' for ifft, it is sampled when start is '1'
-- Iin,Qin : data input-- following start immediately, input data
-- -- power should not be too big
-- inputbusy : if it change to '0' then next fft is enable
68,7 → 68,7
clk : in STD_LOGIC;
rst : in STD_LOGIC;
start : in STD_LOGIC;
inv : in std_logic;
invert : in std_logic;
Iin : in STD_LOGIC_VECTOR(11 downto 0);
Qin : in STD_LOGIC_VECTOR(11 downto 0);
inputbusy : out STD_LOGIC;
92,7 → 92,7
clk : in STD_LOGIC;
rst : in STD_LOGIC;
start : in STD_LOGIC;
inv : in std_logic;
invert : in std_logic;
Iin : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
Qin : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
inputbusy : out STD_LOGIC;
115,7 → 115,7
clk=>clk,
rst=>rst,
start=>start,
inv=>inv,
invert=>invert,
Iin=>Iin,
Qin=>Qin,
inputbusy=>inputbusy,
/trunk/src/rofactor.vhd
50,7 → 50,7
clk : in STD_LOGIC;
rst : in STD_LOGIC;
start : in STD_LOGIC;
inv : in std_logic;
invert : in std_logic;
-- step : in STD_LOGIC_VECTOR(2 downto 0);
angle : out STD_LOGIC_VECTOR(2*STAGE-1 downto 0)
);
75,7 → 75,7
counter<=( others=>'0' );
mask<=( others=>'0' );
-- state<="000";
if inv='1' then
if invert='1' then
inc<=CONV_STD_LOGIC_VECTOR(1,STAGE*2);
else
inc<=CONV_STD_LOGIC_VECTOR(-1,STAGE*2);
/trunk/src/cfft.vhd
30,7 → 30,7
-- clk : main clk -- I have test 90M with Xilinx virtex600E
-- rst : globe reset -- '1' for reset
-- start : start fft -- one clock '1' before data input
-- inv : '0' for fft and '1' for ifft, it is sampled when start is '1'
-- invert : '0' for fft and '1' for ifft, it is sampled when start is '1'
-- Iin,Qin : data input-- following start immediately, input data
-- -- power should not be too big
-- inputbusy : if it change to '0' then next fft is enable
86,7 → 86,7
clk : in STD_LOGIC;
rst : in STD_LOGIC;
start : in STD_LOGIC;
inv : in std_logic;
invert : in std_logic;
Iin : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
Qin : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
inputbusy : out STD_LOGIC;
151,7 → 151,7
clk : in STD_LOGIC;
rst : in STD_LOGIC;
start : in STD_LOGIC;
inv : in std_logic;
invert : in std_logic;
I : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
Q : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
Iout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0);
195,7 → 195,7
clk : in STD_LOGIC;
rst : in STD_LOGIC;
start : in STD_LOGIC;
inv : in std_logic;
invert : in std_logic;
angle : out STD_LOGIC_VECTOR(2*STAGE-1 downto 0)
);
end component;
275,7 → 275,7
clk=>clk,
rst=>rst,
start=>cfft4start,
inv=>inv_reg,
invert=>inv_reg,
I=>Iramout,
Q=>Qramout,
Iout=>Icfft4out,
328,7 → 328,7
clk=>clk,
rst=>rst,
start=>factorstart,
inv=>inv_reg,
invert=>inv_reg,
angle=>angle
);
 
338,7 → 338,7
inv_reg<='0';
elsif clk'event and clk='1' then
if start='1' then
inv_reg<=inv;
inv_reg<=invert;
end if;
end if;
end process;
/trunk/src/cfft4.vhd
39,7 → 39,7
clk : in STD_LOGIC;
rst : in STD_LOGIC;
start : in STD_LOGIC;
inv : in std_logic;
invert : in std_logic;
I : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
Q : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
Iout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0);
96,7 → 96,7
when "01" =>
RegAI(1)<=I;
RegAQ(1)<=Q;
if inv='0' then
if invert='0' then
-- for fft *(-j)
RegBI(3)<=SXT(RegAQ(1),WIDTH+1)-SXT(RegAQ(3),WIDTH+1);
RegBQ(3)<=SXT(RegAI(3),WIDTH+1)-SXT(RegAI(1),WIDTH+1);
/trunk/sim/tb_cfft1024x12_read_from_file.vhd
15,7 → 15,7
clk : in STD_LOGIC;
rst : in STD_LOGIC;
start : in STD_LOGIC;
inv : in std_logic;
invert : in std_logic;
Iin : in STD_LOGIC_VECTOR(11 downto 0);
Qin : in STD_LOGIC_VECTOR(11 downto 0);
inputbusy : out STD_LOGIC;
29,7 → 29,7
signal clk : STD_LOGIC;
signal rst : STD_LOGIC;
signal start : STD_LOGIC;
signal inv : std_logic;
signal invert : std_logic;
signal Iin : STD_LOGIC_VECTOR(11 downto 0);
signal Qin : STD_LOGIC_VECTOR(11 downto 0);
signal inputbusy : STD_LOGIC;
43,7 → 43,7
f: cfft1024x12 port map(clk=>clk,
rst =>rst,
start=> start,
inv=>inv,
invert=>invert,
Iin=>Iin,
Qin=>Qin,
inputbusy=>inputbusy,
70,7 → 70,7
wait until clk'EVENT and clk='1';
rst<='0';
wait until clk'EVENT and clk='1';
inv<='0';
invert<='0';
start<='1';
wait until clk'EVENT and clk='1';
start<='0';
/trunk/sim/tb_cfft1024x12.vhd
53,7 → 53,7
clk : IN STD_LOGIC ;
rst : IN STD_LOGIC ;
start : IN STD_LOGIC ;
inv : IN std_logic ;
invert : IN std_logic ;
Iin : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
Qin : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
inputbusy : OUT STD_LOGIC ;
77,7 → 77,7
signal clock : std_logic:='0';
signal reset : std_logic:='0';
signal start : std_logic:='0';
signal inv : std_logic ;
signal invert : std_logic ;
signal Iin : STD_LOGIC_VECTOR (11 DOWNTO 0);
signal Qin : STD_LOGIC_VECTOR (11 DOWNTO 0);
signal inputbusy : STD_LOGIC:='0' ;
95,7 → 95,7
clk => clock,
rst => reset,
start => start,
inv => inv,
invert => invert,
Iin => Iin,
Qin => Qin,
inputbusy => inputbusy,
111,7 → 111,7
clock <= not clock after Tck_half;
reset <= '1', '0' after 2*Tck_half;
start <= '0', '1' after 3*Tck_half, '0' after 5*Tck_half;-- only one FFT is done
inv <= '0';-- FFT
invert <= '0';-- FFT
 
----------------------------------------------------------------------------
--

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