OpenCores
URL https://opencores.org/ocsvn/csa/csa/trunk

Subversion Repositories csa

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /
    from Rev 12 to Rev 13
    Reverse comparison

Rev 12 → Rev 13

/trunk/bench/csa_pli.c
0,0 → 1,141
/*
* =====================================================================================
*
* Filename: read_ikey.c
*
* Description: this is a pli module to read the input key
*
* Version: 1.0
* Created: 07/10/2008 09:18:10 PM
* Revision: none
* Compiler: gcc
*
* Author: mengxipeng@gmail.com
* Company: mengxipeng
*
* =====================================================================================
*/
 
#include <string.h>
#include <vpi_user.h>
 
 
char data[120];
 
static int read_data(char *fn)
{
vpiHandle systf_handle;
vpiHandle arg_itr;
vpiHandle arg_handle;
s_vpi_value value_s;
 
FILE *fp;
FILE *fp1;
char str[120];
int i;
int n;
 
systf_handle = vpi_handle(vpiSysTfCall, NULL);
arg_itr = vpi_iterate(vpiArgument, systf_handle);
if (arg_itr == NULL)
{
vpi_printf("ERROR: $pow failed to obtain systf arg handles\n");
return(0);
}
 
/* read file name */
arg_handle = vpi_scan(arg_itr);
value_s.format = vpiStringVal;
vpi_get_value(arg_handle, &value_s);
strcpy(str,value_s.value.str);
 
fp=fopen(str,"r");
if(fp)
{
fscanf(fp,"%s",&data);
value_s.format = vpiBinStrVal;
value_s.value.str=data;
arg_handle = vpi_scan(arg_itr);
vpi_put_value(arg_handle, &value_s,NULL, vpiNoDelay);
fclose(fp);
}
else
{
vpi_printf("can't open the input file in %s \n", __FUNCTION__);
}
return 0;
}
 
static void read_data_register()
{
s_vpi_systf_data tf_data;
tf_data.type = vpiSysTask;
tf_data.tfname = "$read_data";
tf_data.calltf = read_data;
tf_data.compiletf = 0;
tf_data.sizetf = 0;
vpi_register_systf(&tf_data);
}
 
static int write_data(char *xx)
{
vpiHandle systf_handle;
vpiHandle arg_itr;
vpiHandle arg_handle;
s_vpi_value value_s;
 
FILE *fp;
char str[120];
int i;
int n;
 
systf_handle = vpi_handle(vpiSysTfCall, NULL);
arg_itr = vpi_iterate(vpiArgument, systf_handle);
if (arg_itr == NULL)
{
vpi_printf("ERROR: $pow failed to obtain systf arg handles\n");
return(0);
}
 
/* read file name */
arg_handle = vpi_scan(arg_itr);
value_s.format = vpiStringVal;
vpi_get_value(arg_handle, &value_s);
strcpy(str,value_s.value.str);
 
fp=fopen(str,"w");
if(fp)
{
value_s.format = vpiBinStrVal;
arg_handle = vpi_scan(arg_itr);
vpi_get_value(arg_handle, &value_s);
//fprintf(fp,"%s\n",data);
fprintf(fp,"%s\n",value_s.value.str);
fclose(fp);
}
else
{
vpi_printf("can't open the output file in %s \n", __FUNCTION__);
}
return 0;
}
 
static void write_data_register()
{
s_vpi_systf_data tf_data;
tf_data.type = vpiSysTask;
tf_data.tfname = "$write_data";
tf_data.calltf = write_data;
tf_data.compiletf = 0;
tf_data.sizetf = 0;
vpi_register_systf(&tf_data);
}
 
void (*vlog_startup_routines[])() = {
read_data_register,
write_data_register,
0
};
 
/trunk/bench/key_schedule_tb.v
0,0 → 1,29
// the test bench module for key_schedule
`timescale 10ns/1ns
 
module key_schedule_tb;
reg [8*8-1:0] ck;
wire [56*8-1:0] kk;
initial
begin
 
// read CK
$read_data(
"../test_dat/key_schedule.in"
,ck
);
#10;
 
// output kk
$write_data(
"../test_dat/key_schedule.out.v"
,kk
);
$finish;
end
 
key_schedule ks(
.i_ck(ck)
,.o_kk(kk)
);
endmodule
/trunk/rtl/key_schedule.v
0,0 → 1,26
// this key_schedule module
module key_schedule(i_ck,o_kk);
input [8*8-1:0] i_ck;
output [56*8-1:0] o_kk;
 
wire [64*8-1:0] kb;
 
assign kb[(8*8)*8-1:(7*8)*8] = i_ck;
 
key_perm k1( .i_key(kb[(8*8)*8-1:(7*8)*8]) ,.o_key(kb[(7*8)*8-1:(6*8)*8]));
key_perm k2( .i_key(kb[(7*8)*8-1:(6*8)*8]) ,.o_key(kb[(6*8)*8-1:(5*8)*8]));
key_perm k3( .i_key(kb[(6*8)*8-1:(5*8)*8]) ,.o_key(kb[(5*8)*8-1:(4*8)*8]));
key_perm k4( .i_key(kb[(5*8)*8-1:(4*8)*8]) ,.o_key(kb[(4*8)*8-1:(3*8)*8]));
key_perm k5( .i_key(kb[(4*8)*8-1:(3*8)*8]) ,.o_key(kb[(3*8)*8-1:(2*8)*8]));
key_perm k6( .i_key(kb[(3*8)*8-1:(2*8)*8]) ,.o_key(kb[(2*8)*8-1:(1*8)*8]));
key_perm k7( .i_key(kb[(2*8)*8-1:(1*8)*8]) ,.o_key(kb[(1*8)*8-1:(0*8)*8]));
 
assign o_kk [(1*8)*8-1:(0*8)*8] = kb[(1*8)*8-1:(0*8)*8] ^ 64'h0000000000000000;
assign o_kk [(2*8)*8-1:(1*8)*8] = kb[(2*8)*8-1:(1*8)*8] ^ 64'h0101010101010101;
assign o_kk [(3*8)*8-1:(2*8)*8] = kb[(3*8)*8-1:(2*8)*8] ^ 64'h0202020202020202;
assign o_kk [(4*8)*8-1:(3*8)*8] = kb[(4*8)*8-1:(3*8)*8] ^ 64'h0303030303030303;
assign o_kk [(5*8)*8-1:(4*8)*8] = kb[(5*8)*8-1:(4*8)*8] ^ 64'h0404040404040404;
assign o_kk [(6*8)*8-1:(5*8)*8] = kb[(6*8)*8-1:(5*8)*8] ^ 64'h0505050505050505;
assign o_kk [(7*8)*8-1:(6*8)*8] = kb[(7*8)*8-1:(6*8)*8] ^ 64'h0606060606060606;
 
endmodule
/trunk/rtl/makefile
1,7 → 1,12
all:key_perm
PROJ_NAME ?=key_perm
 
all:$(PROJ_NAME)
 
key_perm:
iverilog -S -tnull $@.v
 
key_schedule:
iverilog -S -tnull $@.v key_perm.v
 
clean:
/trunk/sw_sim/key_schedule.c
0,0 → 1,36
/* this file simulates the key_schedule funtion */
 
#include <stdio.h>
#include <string.h>
 
extern void key_schedule(unsigned char *CK, int *kk) ;
 
int main()
{
unsigned char CK[8];
int kk[57];
int i;
int c;
 
memset(CK,0,sizeof CK);
for (i=63;i>=0;i--)
{
c=getchar();
printf("%c",c);
if(c=='1')
{
CK[i/8]|=(1<<(i%8));
}
}
memset(kk,0,sizeof kk);
key_schedule(CK,kk);
for(i=56*8;i>=8;i--)
{
if(kk[i/8]&(1<<(i%8)))
printf("1");
else
printf("0");
 
}
return 0;
}
/trunk/sw_sim/csa.c
250,7 → 250,8
0x4D,0x4F,0xCD,0xCF,0x6D,0x6F,0xED,0xEF, 0x5D,0x5F,0xDD,0xDF,0x7D,0x7F,0xFD,0xFF,
};
 
void key_schedule(unsigned char *CK, int *kk) {
void key_schedule(unsigned char *CK, int *kk)
{
int i,j,k;
int bit[64];
int newbit[64];
/trunk/sw_sim/key_perm.c
26,14 → 26,14
 
int main()
{
int i;
int j;
int k;
int i;
int j;
int k;
unsigned char p;
int v;
int c;
int b;
/* first read the input key */
int v;
int c;
int b;
/* first read the input key */
memset(i_key,0,sizeof i_key);
for (i=63;i>=0;i--)
{
/trunk/sw_sim/makefile
1,5 → 1,5
 
PROJ_NAME ?= key_perm
PROJ_NAME ?= key_schedule
 
CFLAGS=-g -ansi
 
14,4 → 14,8
 
key_perm:csa.o key_perm.o
 
key_schedule:csa.o key_schedule.o
 
 
 
 
/trunk/makefile
1,49 → 1,66
MODULE=key_perm
MODULE=key_schedule
TEST_IN_FILE=test_dat/$(MODULE).in
TEST_TIMES=1
 
all:rtl bench sw_sim
all:rtlm benchm sw_simm
 
rtl:
make -C rtl
rtlm:
@make -s -C rtl PROJ_NAME=$(MODULE)
 
bench:
make -C bench
benchm:
@make -s -C bench PROJ_NAME=$(MODULE)
 
sw_sim:
make -C sw_sim
sw_simm:
@make -s -C sw_sim PROJ_NAME=$(MODULE)
 
synthesis:
make -C rtl $(MODULE)
@make -s -C rtl $(MODULE)
 
sw:
make -C sw_sim $(MODULE)
@make -s -C sw_sim $(MODULE)
 
preare_key_perm:
@str=""; \
@str=""; \
for ((i=0;i<8;i=i+1)); \
do \
n=$$(expr $$RANDOM % 256 ); \
binstr=$$(echo "ibase=10;obase=2;$$n"|bc); \
binstr=$$(echo "$$binstr" | awk ' { n=8-length($$1);for(i=0;i<n;i=i+1) printf "0"; printf $$1; }' ) ; \
str=$$(printf "%s%s" $$str $$binstr) ; \
str=$$(printf "%s%s" $$str $$binstr) ; \
done; \
echo $$str >$(TEST_IN_FILE)
 
preare_key_schedule:
@str=""; \
for ((i=0;i<8;i=i+1)); \
do \
n=$$(expr $$RANDOM % 256 ); \
binstr=$$(echo "ibase=10;obase=2;$$n"|bc); \
binstr=$$(echo "$$binstr" | awk ' { n=8-length($$1);for(i=0;i<n;i=i+1) printf "0"; printf $$1; }' ) ; \
str=$$(printf "%s%s" $$str $$binstr) ; \
done; \
echo $$str >$(TEST_IN_FILE)
 
 
check:
@(for ((i=0;i<$(TEST_TIMES);i=i+1)) \
do \
make -s preare_$(MODULE); \
make -s -C sw_sim test PROJ_NAME=$(MODULE);\
make -s -C bench test PROJ_NAME=$(MODULE);\
diff test_dat/$(MODULE).out.sw test_dat/$(MODULE).out.v ;\
@(for ((i=0;i<$(TEST_TIMES);i=i+1)) \
do \
make -s preare_$(MODULE); \
make -s -C sw_sim test PROJ_NAME=$(MODULE); \
make -s -C bench test PROJ_NAME=$(MODULE); \
diff test_dat/$(MODULE).out.sw test_dat/$(MODULE).out.v ; \
done)
 
 
clean:
make -s -C sw_sim clean
make -s -C rtl clean
make -s -C bench clean
rm -fr test_dat/*
@make -s -C sw_sim clean
@make -s -C rtl clean
@make -s -C bench clean
@rm -fr test_dat/*
 
cscope:
@find . -name "*.[ch]" >cscope.files
@cscope -b
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.