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/trunk/bench/verilog/fifo_beh.v
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/****************************************************************************** |
$Id: fifo_beh.v,v 1.1 2002-03-10 17:18:37 johnsonw10 Exp $ |
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Author(s): Johnsonw10@opencors.org |
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Revision History: |
$Log: not supported by cvs2svn $ |
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******************************************************************************/ |
`timescale 1 ns / 100 ps |
module fifo_beh ( |
clk, |
reset_n, |
wr, |
din, |
|
rd, |
dout, |
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empty, |
full |
); |
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parameter DATA_WIDTH = 32; |
parameter FIFO_SIZE = 64; |
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input reset_n; |
input clk; |
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input wr; |
input [0:DATA_WIDTH-1] din; |
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input rd; |
output [0:DATA_WIDTH-1] dout; |
reg [0:DATA_WIDTH-1] dout; |
output empty; |
output full; |
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reg [0:DATA_WIDTH-1] mem[0:FIFO_SIZE-1]; |
integer rd_ptr, wr_ptr, dcnt; |
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wire empty_o, full_o; |
wire rd_i = rd & (!empty_o); |
wire wr_i = wr & (!full_o); |
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always @ (negedge reset_n or posedge clk) begin |
if (!reset_n) begin |
rd_ptr <= 0; |
wr_ptr <= 0; |
dcnt <= 0; |
end |
else begin |
if (rd_i) begin |
dout <= mem[rd_ptr]; |
rd_ptr <= rd_ptr + 1; |
end |
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if (wr_i) begin |
mem[wr_ptr] <= din; |
wr_ptr <= wr_ptr + 1; |
end |
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if (rd_i && wr_i) |
dcnt <= dcnt; |
else if (rd_i) |
dcnt <= dcnt - 1; |
else if (wr_i) |
dcnt <= dcnt + 1; |
end |
end |
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assign empty_o = (dcnt == 0); |
assign full_o = (dcnt == FIFO_SIZE); |
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assign empty = empty_o; |
assign full = full_o; |
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endmodule |