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/trunk/CODE/TX/core/TXcont.vhd
6,7 → 6,7
-- Author : Jamil Khatib (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created :2001/01/15
-- Last update: 2001/01/26
-- Last update: 2001/10/20
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98
-- Synthesizers:
34,182 → 34,157
-- Bugs :
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
entity TxCont_ent is
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY TxCont_ent IS
 
port (
TXclk : in std_logic; -- TX clock
rst_n : in std_logic; -- System Reset
TXEN : in std_logic; -- TX enable
enable : out std_logic; -- Enable control
BackendEnable : out std_logic; -- Backend Enable
abortedTrans : in std_logic; -- No Valid data from the backend
inProgress : in std_logic; -- Data in progress
ValidFrame : in std_logic; -- Valid Frame
Frame : out std_logic; -- Frame strobe
AbortFrame : in std_logic; -- AbortFrame
AbortTrans : out std_logic); -- Abort data transmission
PORT (
TXclk : IN STD_LOGIC; -- TX clock
rst_n : IN STD_LOGIC; -- System Reset
TXEN : IN STD_LOGIC; -- TX enable
enable : OUT STD_LOGIC; -- Enable control
BackendEnable : OUT STD_LOGIC; -- Backend Enable
abortedTrans : IN STD_LOGIC; -- No Valid data from the backend
inProgress : IN STD_LOGIC; -- Data in progress
ValidFrame : IN STD_LOGIC; -- Valid Frame
Frame : OUT STD_LOGIC; -- Frame strobe
AbortFrame : IN STD_LOGIC; -- AbortFrame
AbortTrans : OUT STD_LOGIC); -- Abort data transmission
 
end TxCont_ent;
END TxCont_ent;
-------------------------------------------------------------------------------
architecture TxCont_beh of TxCont_ent is
ARCHITECTURE TxCont_beh OF TxCont_ent IS
 
begin -- TxCont_beh
BEGIN -- TxCont_beh
 
-- purpose: Abort Machine
-- type : sequential
-- inputs : Txclk, rst_n
-- outputs:
abort_proc : process (Txclk, rst_n)
abort_proc : PROCESS (Txclk, rst_n)
 
variable counter : integer range 0 to 14; -- Counter
VARIABLE counter : INTEGER RANGE 0 TO 14; -- Counter
 
variable state : std_logic; -- Internal State
VARIABLE state : STD_LOGIC; -- Internal State
-- state ==> '0' No abort signal
-- state ==> '1' Abort signal
begin -- process abort_proc
if rst_n = '0' then -- asynchronous reset (active low)
BEGIN -- process abort_proc
IF rst_n = '0' THEN -- asynchronous reset (active low)
AbortTrans <= '0';
Counter := 0;
enable <= '1';
state := '0';
elsif Txclk'event and Txclk = '1' then -- rising clock edge
if TXEN = '1' then
ELSIF Txclk'event AND Txclk = '1' THEN -- rising clock edge
IF TXEN = '1' THEN
 
case state is
CASE state IS
 
when '0' =>
if abortedTrans = '1' or AbortFrame = '1' then
WHEN '0' =>
IF abortedTrans = '1' OR AbortFrame = '1' THEN
state := '1';
Counter := 0;
end if;
END IF;
AbortTrans <= '0';
 
when '1' =>
if counter = 8 then
WHEN '1' =>
IF counter = 8 THEN
counter := 0;
if abortedTrans = '0' and AbortFrame = '0' then
IF abortedTrans = '0' AND AbortFrame = '0' THEN
 
state := '0';
AbortTrans <= '0';
else
ELSE
AbortTrans <= '1';
end if;
END IF;
 
else
ELSE
counter := counter +1;
end if; -- counter
END IF; -- counter
 
when others => null;
WHEN OTHERS => NULL;
 
end case;
end if; -- TXEN
END CASE;
END IF; -- TXEN
enable <= TXEN;
 
end if; -- TXclk
end process abort_proc;
END IF; -- TXclk
END PROCESS abort_proc;
 
-- purpose: Flag Controller
-- type : sequential
-- inputs : Txclk, rst_n
-- outputs:
Flag_proc : process (Txclk, rst_n)
Flag_proc : PROCESS (Txclk, rst_n)
 
variable state : std_logic_vector(2 downto 0); -- Internal State machine
variable counter : integer range 0 to 16; -- Internal counter
VARIABLE state : STD_LOGIC_VECTOR(2 DOWNTO 0); -- Internal State machine
VARIABLE counter : INTEGER RANGE 0 TO 16; -- Internal counter
 
begin -- process Flag_proc
if rst_n = '0' then -- asynchronous reset (active low)
Frame <= '0';
state := (others => '0');
BEGIN -- process Flag_proc
IF rst_n = '0' THEN -- asynchronous reset (active low)
Frame <= '0';
state := (OTHERS => '0');
counter := 0;
BackendEnable <= '1';
elsif Txclk'event and Txclk = '1' then -- rising clock edge
if TXEN = '1' then
BackendEnable <= '0';
ELSIF Txclk'event AND Txclk = '1' THEN -- rising clock edge
IF TXEN = '1' THEN
 
case state is
when "000" => -- Check Valid Frame
Frame <= '0';
if ValidFrame = '1' then
state := "001";
counter := 0;
end if;
BackendEnable <= '1';
CASE state IS
WHEN "000" => -- Check Valid Frame
Frame <= '0';
IF ValidFrame = '1' THEN
state := "001";
BackendEnable <= '1';
ELSE
BackendEnable <= '0';
END IF;
counter := 0;
 
when "001" => -- Wait 16 clks before set internal frame
counter := counter + 1;
WHEN "001" =>
 
if counter = 16 then
counter := 0;
IF counter > 1 AND inProgress = '0' THEN
state := "010";
Frame <= '1';
ELSE
Frame <= '0';
END IF;
 
if inProgress = '0' then
state := "010";
Frame <= '1';
else
state := "101";
Frame <= '0';
end if;
else
Frame <= '0';
end if;
BackendEnable <= '1';
IF inProgress = '0' THEN
counter := counter +1;
END IF;
 
when "101" => -- Wait for inProgress
 
if inProgress = '0' then
state := "010";
Frame <= '1';
else
Frame <= '0';
end if;
BackendEnable <= '1';
 
when "010" => -- Check ValidFrame
WHEN "010" => -- Check ValidFrame
 
Frame <= '1';
 
if ValidFrame = '0' then
IF ValidFrame = '0' THEN
state := "011";
counter := 0;
BackendEnable <= '0';
else
ELSE
BackendEnable <= '1';
end if;
END IF;
 
when "011" => -- wait 16 clk before trying to unset
-- internal frame
counter := counter + 1;
if counter = 16 then
counter := 0;
if inProgress = '0' then
state := "000";
Frame <= '0';
else
state := "100";
Frame <= '1';
end if;
else
Frame <= '1';
end if;
counter := 0;
 
BackendEnable <= '0';
 
when "100" =>
 
if inProgress = '0' then
WHEN "011" =>
IF counter > 2 AND inProgress = '0' THEN
state := "000";
Frame <= '0';
else
ELSE
Frame <= '1';
end if;
END IF;
 
IF inProgress = '0' THEN
counter := counter +1;
END IF;
 
BackendEnable <= '0';
 
when others => null;
end case;
end if; -- TXEN
end if;
end process Flag_proc;
WHEN OTHERS => NULL;
END CASE;
END IF; -- TXEN
END IF;
END PROCESS Flag_proc;
-------------------------------------------------------------------------------
end TxCont_beh;
END TxCont_beh;
/trunk/CODE/TX/core/zero_ins.vhd
6,7 → 6,7
-- Author : Jamil Khatib (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created : 2001/01/12
-- Last update: 2001/05/27
-- Last update:2001/10/20
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98
-- Synthesizers:
40,37 → 40,40
-- Zero is inserted after 5 sequence of 1's insted of 6 1's
-------------------------------------------------------------------------------
-- $Log: not supported by cvs2svn $
-- Revision 1.2 2001/05/28 19:14:22 khatib
-- TX zero insertion bug fixed
--
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
entity ZeroIns_ent is
ENTITY ZeroIns_ent IS
 
port (
TxClk : in std_logic; -- Tx clock
rst_n : in std_logic; -- system reset
enable : in std_logic; -- enable (Driven by controller)
inProgress : out std_logic; -- Data in progress
BackendEnable : in std_logic; -- Backend Enable
PORT (
TxClk : IN STD_LOGIC; -- Tx clock
rst_n : IN STD_LOGIC; -- system reset
enable : IN STD_LOGIC; -- enable (Driven by controller)
inProgress : OUT STD_LOGIC; -- Data in progress
BackendEnable : IN STD_LOGIC; -- Backend Enable
-- backend interface
abortedTrans : out std_logic; -- aborted Transmission
ValidFrame : in std_logic; -- Valid Frame signal
Writebyte : in std_logic; -- Back end write byte
rdy : out std_logic; -- data ready
TXD : out std_logic; -- TX serial data
Data : in std_logic_vector(7 downto 0)); -- TX data bus
abortedTrans : OUT STD_LOGIC; -- aborted Transmission
ValidFrame : IN STD_LOGIC; -- Valid Frame signal
Writebyte : IN STD_LOGIC; -- Back end write byte
rdy : OUT STD_LOGIC; -- data ready
TXD : OUT STD_LOGIC; -- TX serial data
Data : IN STD_LOGIC_VECTOR(7 DOWNTO 0)); -- TX data bus
 
end ZeroIns_ent;
END ZeroIns_ent;
-------------------------------------------------------------------------------
architecture zero_ins_beh of ZeroIns_ent is
ARCHITECTURE zero_ins_beh OF ZeroIns_ent IS
 
signal data_reg : std_logic_vector(7 downto 0); -- Data register (used as
SIGNAL data_reg : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Data register (used as
-- internal buffer)
signal flag : std_logic; -- control signal between processes
signal delay_TX : std_logic; -- Delayed output
SIGNAL flag : STD_LOGIC; -- control signal between processes
SIGNAL delay_TX : STD_LOGIC; -- Delayed output
 
begin -- zero_ins_beh
BEGIN -- zero_ins_beh
 
 
-- purpose: Parallel to Serial
77,15 → 80,15
-- type : sequential
-- inputs : TxClk, rst_n
-- outputs:
P2S_proc : process (TxClk, rst_n)
variable tmp_reg : std_logic_vector(15 downto 0); -- Temp Shift register
variable counter : integer range 0 to 8; -- Counter
variable OnesDetected : std_logic; -- 6 ones detected
P2S_proc : PROCESS (TxClk, rst_n)
VARIABLE tmp_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); -- Temp Shift register
VARIABLE counter : INTEGER RANGE 0 TO 8; -- Counter
VARIABLE OnesDetected : STD_LOGIC; -- 6 ones detected
 
begin -- process P2S_proc
if rst_n = '0' then -- asynchronous reset (active low)
BEGIN -- process P2S_proc
IF rst_n = '0' THEN -- asynchronous reset (active low)
 
tmp_reg := (others => '0');
tmp_reg := (OTHERS => '0');
Counter := 0;
flag <= '1';
OnesDetected := '0';
93,93 → 96,92
delay_TX <= '1';
inProgress <= '0';
 
elsif TxClk'event and TxClk = '1' then -- rising clock edge
if enable = '1' then
ELSIF TxClk'event AND TxClk = '1' THEN -- rising clock edge
IF enable = '1' THEN
 
OnesDetected := tmp_reg(0) and tmp_reg(1) and tmp_reg(2) and tmp_reg(3) and tmp_reg(4);
OnesDetected := tmp_reg(0) AND tmp_reg(1) AND tmp_reg(2) AND tmp_reg(3) AND tmp_reg(4);
 
delay_TX <= tmp_reg(0);
TXD <= delay_TX;
 
if OnesDetected = '1' then
IF OnesDetected = '1' THEN
-- Zero insertion
tmp_reg(4 downto 0) := '0' & tmp_reg(4 downto 1);
tmp_reg(4 DOWNTO 0) := '0' & tmp_reg(4 DOWNTO 1);
 
else
ELSE
-- Total Shift
tmp_reg(15 downto 0) := '0' & tmp_reg(15 downto 1);
tmp_reg(15 DOWNTO 0) := '0' & tmp_reg(15 DOWNTO 1);
 
Counter := Counter +1;
 
end if; -- ones detected
END IF; -- ones detected
 
if counter = 8 then
IF counter = 8 THEN
 
counter := 0;
flag <= '1';
inProgress <= '0';
 
tmp_reg(15 downto 8) := data_reg;
else
tmp_reg(15 DOWNTO 8) := data_reg;
ELSE
inProgress <= '1';
flag <= '0';
end if; -- counter
end if; -- enable
end if; -- clk
end process P2S_proc;
END IF; -- counter
END IF; -- enable
END IF; -- clk
END PROCESS P2S_proc;
-------------------------------------------------------------------------------
 
-- purpose: Baclend Interface
-- purpose: Backend Interface
-- type : sequential
-- inputs : TxClk, rst_n
-- outputs:
Backend_proc : process (TxClk, rst_n)
variable state : std_logic; -- Backend state
Backend_proc : PROCESS (TxClk, rst_n)
VARIABLE state : STD_LOGIC; -- Backend state
 
begin -- process Backend_proc
if rst_n = '0' then -- asynchronous reset (active low)
state := '0';
data_reg <= (others => '0');
rdy <= '0';
abortedTrans <= '0';
elsif TxClk'event and TxClk = '1' then -- rising clock edge
if enable = '1' then
if BackendEnable = '1' then
if ValidFrame = '1' then
BEGIN -- process Backend_proc
IF rst_n = '0' THEN -- asynchronous reset (active low)
state := '0';
data_reg <= (OTHERS => '0');
rdy <= '0';
abortedTrans <= '0';
ELSIF TxClk'event AND TxClk = '1' THEN -- rising clock edge
IF enable = '1' THEN
IF BackendEnable = '1' THEN
CASE state IS
WHEN '0' => -- wait for reading the register
IF flag = '1' THEN -- Register has been read
state := '1';
rdy <= '1';
data_reg <= "00000000"; -- set register to known pattern to
-- avoid invalid read (upon valid
-- read this value will be overwritten)
END IF;
 
case state is
when '0' => -- wait for reading the register
if flag = '1' then -- Register has been read
state := '1';
rdy <= '1';
data_reg <= "00000000"; -- set register to known pattern to
-- avoid invalid read (upon valid
-- read this value will be overwritten)
end if;
WHEN '1' =>
IF WriteByte = '1' THEN
state := '0';
rdy <= '0';
data_reg <= Data;
ELSIF flag = '1' THEN -- Another flag but without read
state := '0';
rdy <= '0';
data_reg <= "00000000";
abortedTrans <= '1';
END IF;
 
when '1' =>
if WriteByte = '1' then
state := '0';
rdy <= '0';
data_reg <= Data;
elsif flag = '1' then -- Another flag but without read
state := '0';
rdy <= '0';
data_reg <= "00000000";
abortedTrans <= '1';
end if;
WHEN OTHERS => NULL;
END CASE;
 
when others => null;
end case;
else
abortedTrans <= '0';
end if; -- ValidFrame
else
data_reg <= (others => '0');
end if; -- Backend enable
end if; -- enable
end if; -- Txclk
end process Backend_proc;
ELSE
rdy <= '0';
state := '0';
abortedTrans <= '0';
END IF; -- Backend enable
 
end zero_ins_beh;
END IF; -- enable
END IF; -- Txclk
END PROCESS Backend_proc;
 
 
END zero_ins_beh;

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