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Rev 12 → Rev 13

/trunk/rtl/verilog/i2c_master_byte_ctrl.v
2,7 → 2,8
// WISHBONE revB2 compiant I2C master core
//
// author: Richard Herveille
// rev. 0.1 August 24th, 2001. Initial Verilog release.
// rev. 0.1 August 24th, 2001. Initial Verilog release.
// rev. 0.2 October 25th, 2001. Fixed some synthesis warnings.
//
 
`include "timescale.v"
136,7 → 137,7
if (!nReset)
begin
core_cmd <= #1 `I2C_CMD_NOP;
core_txd <= #1 sr[7];
core_txd <= #1 1'b0;
shift <= #1 1'b0;
ld <= #1 1'b0;
156,129 → 157,129
c_state <= #1 ST_IDLE;
end
else
begin
// initially reset all signals
core_txd <= #1 sr[7];
begin
// initially reset all signals
core_txd <= #1 sr[7];
shift <= #1 1'b0;
ld <= #1 1'b0;
shift <= #1 1'b0;
ld <= #1 1'b0;
 
cmd_ack <= #1 1'b0;
cmd_ack <= #1 1'b0;
 
case (c_state) // synopsis full_case parallel_case
ST_IDLE:
if (go)
begin
if (start)
begin
c_state <= #1 ST_START;
core_cmd <= #1 `I2C_CMD_START;
end
else if (read)
begin
c_state <= #1 ST_READ;
core_cmd <= #1 `I2C_CMD_READ;
end
else if (write)
begin
c_state <= #1 ST_WRITE;
core_cmd <= #1 `I2C_CMD_WRITE;
end
else // stop
begin
c_state <= #1 ST_STOP;
core_cmd <= #1 `I2C_CMD_STOP;
case (c_state) // synopsis full_case parallel_case
ST_IDLE:
if (go)
begin
if (start)
begin
c_state <= #1 ST_START;
core_cmd <= #1 `I2C_CMD_START;
end
else if (read)
begin
c_state <= #1 ST_READ;
core_cmd <= #1 `I2C_CMD_READ;
end
else if (write)
begin
c_state <= #1 ST_WRITE;
core_cmd <= #1 `I2C_CMD_WRITE;
end
else // stop
begin
c_state <= #1 ST_STOP;
core_cmd <= #1 `I2C_CMD_STOP;
 
// generate command acknowledge signal
cmd_ack <= #1 1'b1;
end
// generate command acknowledge signal
cmd_ack <= #1 1'b1;
end
 
ld <= #1 1'b1;
end
ld <= #1 1'b1;
end
 
ST_START:
if (core_ack)
begin
if (read)
ST_START:
if (core_ack)
begin
if (read)
begin
c_state <= #1 ST_READ;
core_cmd <= #1 `I2C_CMD_READ;
end
else
begin
c_state <= #1 ST_WRITE;
core_cmd <= #1 `I2C_CMD_WRITE;
end
 
ld <= #1 1'b1;
end
 
ST_WRITE:
if (core_ack)
if (cnt_done)
begin
c_state <= #1 ST_READ;
c_state <= #1 ST_ACK;
core_cmd <= #1 `I2C_CMD_READ;
end
else
begin
c_state <= #1 ST_WRITE;
core_cmd <= #1 `I2C_CMD_WRITE;
c_state <= #1 ST_WRITE; // stay in same state
core_cmd <= #1 `I2C_CMD_WRITE; // write next bit
 
shift <= #1 1'b1;
end
 
ld <= #1 1'b1;
end
ST_READ:
if (core_ack)
begin
if (cnt_done)
begin
c_state <= #1 ST_ACK;
core_cmd <= #1 `I2C_CMD_WRITE;
end
else
begin
c_state <= #1 ST_READ; // stay in same state
core_cmd <= #1 `I2C_CMD_READ; // read next bit
end
 
ST_WRITE:
if (core_ack)
if (cnt_done)
begin
c_state <= #1 ST_ACK;
core_cmd <= #1 `I2C_CMD_READ;
end
else
begin
c_state <= #1 ST_WRITE; // stay in same state
core_cmd <= #1 `I2C_CMD_WRITE; // write next bit
shift <= #1 1'b1;
end
 
shift <= #1 1'b1;
end
 
ST_READ:
ST_ACK:
if (core_ack)
begin
if (cnt_done)
if (stop)
begin
c_state <= #1 ST_ACK;
core_cmd <= #1 `I2C_CMD_WRITE;
c_state <= #1 ST_STOP;
core_cmd <= #1 `I2C_CMD_STOP;
end
else
begin
c_state <= #1 ST_READ; // stay in same state
core_cmd <= #1 `I2C_CMD_READ; // read next bit
c_state <= #1 ST_IDLE;
core_cmd <= #1 `I2C_CMD_NOP;
end
 
shift <= #1 1'b1;
end
// assign ack_out output to bit_controller_rxd (contains last received bit)
ack_out = core_rxd;
 
ST_ACK:
if (core_ack)
begin
if (stop)
begin
c_state <= #1 ST_STOP;
core_cmd <= #1 `I2C_CMD_STOP;
end
else
begin
c_state <= #1 ST_IDLE;
core_cmd <= #1 `I2C_CMD_NOP;
end
 
// assign ack_out output to bit_controller_rxd (contains last received bit)
ack_out = core_rxd;
 
// generate command acknowledge signal
cmd_ack <= #1 1'b1;
// generate command acknowledge signal
cmd_ack <= #1 1'b1;
core_txd <= #1 1'b1;
end
else
core_txd <= #1 ack_in;
core_txd <= #1 1'b1;
end
else
core_txd <= #1 ack_in;
 
ST_STOP:
if (core_ack)
begin
c_state <= #1 ST_IDLE;
core_cmd <= #1 `I2C_CMD_NOP;
end
ST_STOP:
if (core_ack)
begin
c_state <= #1 ST_IDLE;
core_cmd <= #1 `I2C_CMD_NOP;
end
 
endcase
end
endcase
end
endmodule
 
 
/trunk/rtl/verilog/i2c_master_top.v
63,6 → 63,7
 
// core enable signal
wire core_en;
wire ien;
 
// status register signals
wire irxack;
146,6 → 147,7
 
// decode control register
assign core_en = ctr[7];
assign ien = ctr[6];
 
// hookup byte controller block
i2c_master_byte_ctrl byte_controller (
201,7 → 203,7
else if (wb_rst_i)
wb_inta_o <= #1 1'b0;
else
wb_inta_o <= #1 irq_flag && ctr[6]; // interrupt signal is only generated when IEN (interrupt enable bit is set)
wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set)
 
// assign status register bits
assign sr[7] = rxack;

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