OpenCores
URL https://opencores.org/ocsvn/sardmips/sardmips/trunk

Subversion Repositories sardmips

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    /
    from Rev 12 to Rev 13
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Rev 12 → Rev 13

/tags/arelease/PROGRAMMING_exception/link.xn
0,0 → 1,88
/*
* Linker script for the mips programs. Created for the 32bit mips
* little endian achitecture.
*/
 
OUTPUT(program.elf) /* Default output name */
OUTPUT_ARCH(mips) /* Output arch is mips... no shit :-) */
ENTRY(_start) /* Entry point for program */
 
SECTIONS
{
/**** Code and read-only data ****/
 
. = 0x00000000; /* Here the code should be loaded so we */
/* set the location counter to this */
/* address. */
.text . : {
 
_ftext = .; /* Start of code and read-only data */
 
crt0.o (.text) /* This must be the first file since */
/* this has the program entry point */
*(.text) /* The rest of the object files */
_ecode = .; /* End of code */
 
*(.rodata)
 
. = ALIGN(8);
_etext = .; /* End of code and read-only data */
} = 0
 
.reginfo : { *(.reginfo) } /* Contains masks of registers used and */
/* $gp value ($gp register is not used) */
 
/**** Initialised data ****/
 
.data :
{
_fdata = .; /* Start of initialised data */
*(.data)
. = ALIGN(8);
 
*(.lit8) /* Place 8-byte constants here */
*(.lit4) /* Place 4-byte constants here */
*(.sdata) /* Place subsequent data */
 
. = ALIGN(8);
 
_edata = .; /* End of initialised data */
}
 
.reginfo :
{
/**/
}
 
/**** Uninitialised data ****/
. = 0x00000000;
_fbss = .; /* Start of uninitialised data */
 
.sbss :
{
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.scommon) /* Place small common symbols here */
}
 
.bss :
{
*(.dynbss)
*(.bss)
*(.bss.*)
*(COMMON) /* Place common symbols here */
 
_sp_end = .;
/* Allocate room for stack */
. = ALIGN(8) ;
. = 0x4000 ;
_sp = . - 16;
}
 
_end = .; /* End of unitialised data */
 
}
 
 
/tags/arelease/PROGRAMMING_exception/My_Program.c.hold
0,0 → 1,16
#define ocpstore(address,save) { \
unsigned int *ctrlstore = (unsigned int *) address; \
*ctrlstore = save;}
 
#define ADDR_QUICK 0x00005000
 
int main(void)
{
int i,j,g;
i = 15;
j = 26;
g = j + i;
ocpstore(ADDR_QUICK, g);
asm("nop");
return 0;
}
/tags/arelease/PROGRAMMING_exception/regdef.h
0,0 → 1,45
/*
* Register definitions
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file "COPYING" in the main directory of
* this archive for more details.
*/
#ifndef _REGDEF_H
#define _REGDEF_H
 
#define zero $0 /* wired zero */
#define AT $at /* assembler temp - uppercase because of ".set at" */
#define v0 $2 /* return value - caller saved */
#define v1 $3
#define a0 $4 /* argument registers */
#define a1 $5
#define a2 $6
#define a3 $7
#define t0 $8 /* caller saved in 32 bit (arg reg 64 bit) */
#define t1 $9
#define t2 $10
#define t3 $11
#define t4 $12 /* caller saved */
#define t5 $13
#define t6 $14
#define t7 $15
#define s0 $16 /* callee saved */
#define s1 $17
#define s2 $18
#define s3 $19
#define s4 $20
#define s5 $21
#define s6 $22
#define s7 $23
#define t8 $24 /* caller saved */
#define t9 $25 /* callee address for PIC/temp */
#define k0 $26 /* kernel temporary */
#define k1 $27
#define gp $28 /* global pointer - caller saved for PIC */
#define sp $29 /* stack pointer */
#define fp $30 /* frame pointer */
#define s8 $30 /* callee saved */
#define ra $31 /* return address */
 
#endif /* _REGDEF_H */
/tags/arelease/PROGRAMMING_exception/DISASSEMBLER_ELF Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/tags/arelease/PROGRAMMING_exception/DISASSEMBLER_ELF
tags/arelease/PROGRAMMING_exception/DISASSEMBLER_ELF Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: tags/arelease/PROGRAMMING_exception/My_Program.bin =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: tags/arelease/PROGRAMMING_exception/My_Program.bin =================================================================== --- tags/arelease/PROGRAMMING_exception/My_Program.bin (nonexistent) +++ tags/arelease/PROGRAMMING_exception/My_Program.bin (revision 13)
tags/arelease/PROGRAMMING_exception/My_Program.bin Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: tags/arelease/PROGRAMMING_exception/instructions.asm =================================================================== --- tags/arelease/PROGRAMMING_exception/instructions.asm (nonexistent) +++ tags/arelease/PROGRAMMING_exception/instructions.asm (revision 13) @@ -0,0 +1,344 @@ +@00000000 MIPS (ID): j 16 +@00000004 MIPS (ID): nop +@00000008 MIPS (ID): j 64 +@0000000c MIPS (ID): nop +@00000010 MIPS (ID): lui $29, 0 +@00000014 MIPS (ID): addiu $29, $29, 16368 +@00000018 MIPS (ID): addiu $8, $0, 0 +@0000001c MIPS (ID): lui $9, 0 +@00000020 MIPS (ID): addiu $9, $9, 16384 +@00000024 MIPS (ID): MFC0 +@00000028 MIPS (ID): addi $26, $26, 3 +@0000002c MIPS (ID): MTC0 +@00000030 MIPS (ID): jal 716 +@00000034 MIPS (ID): nop +@00000038 MIPS (ID): j 124 +@0000003c MIPS (ID): nop +@00000040 MIPS (ID): nop +@00000044 MIPS (ID): MFC0 +@00000048 MIPS (ID): MFC0 +@0000004c MIPS (ID): srl $26, $26, 2 +@00000050 MIPS (ID): andi $26, $26, 0x1f +@00000054 MIPS (ID): beq $0, $26, 6 +@00000058 MIPS (ID): nop +@0000005c MIPS (ID): add $11, $0, $0 +@00000060 MIPS (ID): addiu $11, $27, 4 +@00000064 MIPS (ID): MTC0 +@00000068 MIPS (ID): ERET +@0000006c MIPS (ID): nop +@00000070 MIPS (ID): nop +@00000074 MIPS (ID): ERET +@00000078 MIPS (ID): nop +@0000007c MIPS (ID): j 124 +@00000080 MIPS (ID): addiu $29, $29, -40 +@00000084 MIPS (ID): sw $31, 36($29) (36) +@00000088 MIPS (ID): sw $30, 32($29) (32) +@0000008c MIPS (ID): or $30, $29, $0 +@00000090 MIPS (ID): sw $4, 40($30) (40) +@00000094 MIPS (ID): sw $5, 44($30) (44) +@00000098 MIPS (ID): sw $6, 48($30) (48) +@0000009c MIPS (ID): lw $2, 44($30) (44) +@000000a0 MIPS (ID): nop +@000000a4 MIPS (ID): sw $2, 16($30) (16) +@000000a8 MIPS (ID): lw $2, 48($30) (48) +@000000ac MIPS (ID): nop +@000000b0 MIPS (ID): sw $2, 20($30) (20) +@000000b4 MIPS (ID): lw $3, 44($30) (44) +@000000b8 MIPS (ID): lw $2, 48($30) (48) +@000000bc MIPS (ID): nop +@000000c0 MIPS (ID): addu $3, $3, $2 +@000000c4 MIPS (ID): sra $2, $3, 31 +@000000c8 MIPS (ID): srl $2, $2, 31 +@000000cc MIPS (ID): addu $2, $3, $2 +@000000d0 MIPS (ID): sra $2, $2, 1 +@000000d4 MIPS (ID): sll $3, $2, 2 +@000000d8 MIPS (ID): lw $2, 40($30) (40) +@000000dc MIPS (ID): nop +@000000e0 MIPS (ID): addu $2, $3, $2 +@000000e4 MIPS (ID): lw $2, 0($2) (0) +@000000e8 MIPS (ID): nop +@000000ec MIPS (ID): sw $2, 28($30) (28) +@000000f0 MIPS (ID): lw $2, 16($30) (16) +@000000f4 MIPS (ID): nop +@000000f8 MIPS (ID): sll $3, $2, 2 +@000000fc MIPS (ID): lw $2, 40($30) (40) +@00000100 MIPS (ID): nop +@00000104 MIPS (ID): addu $2, $3, $2 +@00000108 MIPS (ID): lw $3, 0($2) (0) +@0000010c MIPS (ID): lw $2, 28($30) (28) +@00000110 MIPS (ID): nop +@00000114 MIPS (ID): slt $2, $3, $2 +@00000118 MIPS (ID): bne $0, $2, 3 +@0000011c MIPS (ID): nop +@00000120 MIPS (ID): beq $0, $0, 6 +@00000124 MIPS (ID): nop +@00000128 MIPS (ID): lw $2, 16($30) (16) +@0000012c MIPS (ID): nop +@00000130 MIPS (ID): addiu $2, $2, 1 +@00000134 MIPS (ID): beq $0, $0, -18 +@00000138 MIPS (ID): sw $2, 16($30) (16) +@0000013c MIPS (ID): nop +@00000140 MIPS (ID): lw $2, 20($30) (20) +@00000144 MIPS (ID): nop +@00000148 MIPS (ID): sll $3, $2, 2 +@0000014c MIPS (ID): lw $2, 40($30) (40) +@00000150 MIPS (ID): nop +@00000154 MIPS (ID): addu $2, $3, $2 +@00000158 MIPS (ID): lw $3, 0($2) (0) +@0000015c MIPS (ID): lw $2, 28($30) (28) +@00000160 MIPS (ID): nop +@00000164 MIPS (ID): slt $2, $2, $3 +@00000168 MIPS (ID): bne $0, $2, 3 +@0000016c MIPS (ID): nop +@00000170 MIPS (ID): beq $0, $0, 6 +@00000174 MIPS (ID): nop +@00000178 MIPS (ID): lw $2, 20($30) (20) +@0000017c MIPS (ID): nop +@00000180 MIPS (ID): addiu $2, $2, -1 +@00000184 MIPS (ID): beq $0, $0, -18 +@00000188 MIPS (ID): sw $2, 20($30) (20) +@0000018c MIPS (ID): lw $2, 16($30) (16) +@00000190 MIPS (ID): lw $3, 20($30) (20) +@00000194 MIPS (ID): nop +@00000198 MIPS (ID): slt $2, $3, $2 +@0000019c MIPS (ID): bne $0, $2, 42 +@000001a0 MIPS (ID): nop +@000001a4 MIPS (ID): lw $2, 16($30) (16) +@000001a8 MIPS (ID): nop +@000001ac MIPS (ID): sll $3, $2, 2 +@000001b0 MIPS (ID): lw $2, 40($30) (40) +@000001b4 MIPS (ID): nop +@000001b8 MIPS (ID): addu $2, $3, $2 +@000001bc MIPS (ID): lw $2, 0($2) (0) +@000001c0 MIPS (ID): nop +@000001c4 MIPS (ID): sw $2, 24($30) (24) +@000001c8 MIPS (ID): lw $2, 16($30) (16) +@000001cc MIPS (ID): nop +@000001d0 MIPS (ID): sll $3, $2, 2 +@000001d4 MIPS (ID): lw $2, 40($30) (40) +@000001d8 MIPS (ID): nop +@000001dc MIPS (ID): addu $4, $3, $2 +@000001e0 MIPS (ID): lw $2, 20($30) (20) +@000001e4 MIPS (ID): nop +@000001e8 MIPS (ID): sll $3, $2, 2 +@000001ec MIPS (ID): lw $2, 40($30) (40) +@000001f0 MIPS (ID): nop +@000001f4 MIPS (ID): addu $2, $3, $2 +@000001f8 MIPS (ID): lw $2, 0($2) (0) +@000001fc MIPS (ID): nop +@00000200 MIPS (ID): sw $2, 0($4) (0) +@00000204 MIPS (ID): lw $2, 20($30) (20) +@00000208 MIPS (ID): nop +@0000020c MIPS (ID): sll $3, $2, 2 +@00000210 MIPS (ID): lw $2, 40($30) (40) +@00000214 MIPS (ID): nop +@00000218 MIPS (ID): addu $3, $3, $2 +@0000021c MIPS (ID): lw $2, 24($30) (24) +@00000220 MIPS (ID): nop +@00000224 MIPS (ID): sw $2, 0($3) (0) +@00000228 MIPS (ID): lw $2, 16($30) (16) +@0000022c MIPS (ID): nop +@00000230 MIPS (ID): addiu $2, $2, 1 +@00000234 MIPS (ID): sw $2, 16($30) (16) +@00000238 MIPS (ID): lw $2, 20($30) (20) +@0000023c MIPS (ID): nop +@00000240 MIPS (ID): addiu $2, $2, -1 +@00000244 MIPS (ID): sw $2, 20($30) (20) +@00000248 MIPS (ID): lw $2, 16($30) (16) +@0000024c MIPS (ID): lw $3, 20($30) (20) +@00000250 MIPS (ID): nop +@00000254 MIPS (ID): slt $2, $3, $2 +@00000258 MIPS (ID): beq $0, $2, -91 +@0000025c MIPS (ID): nop +@00000260 MIPS (ID): lw $2, 44($30) (44) +@00000264 MIPS (ID): lw $3, 20($30) (20) +@00000268 MIPS (ID): nop +@0000026c MIPS (ID): slt $2, $2, $3 +@00000270 MIPS (ID): beq $0, $2, 6 +@00000274 MIPS (ID): nop +@00000278 MIPS (ID): lw $4, 40($30) (40) +@0000027c MIPS (ID): lw $5, 44($30) (44) +@00000280 MIPS (ID): lw $6, 20($30) (20) +@00000284 MIPS (ID): jal 128 +@00000288 MIPS (ID): nop +@0000028c MIPS (ID): lw $2, 16($30) (16) +@00000290 MIPS (ID): lw $3, 48($30) (48) +@00000294 MIPS (ID): nop +@00000298 MIPS (ID): slt $2, $2, $3 +@0000029c MIPS (ID): beq $0, $2, 6 +@000002a0 MIPS (ID): nop +@000002a4 MIPS (ID): lw $4, 40($30) (40) +@000002a8 MIPS (ID): lw $5, 16($30) (16) +@000002ac MIPS (ID): lw $6, 48($30) (48) +@000002b0 MIPS (ID): jal 128 +@000002b4 MIPS (ID): nop +@000002b8 MIPS (ID): or $29, $30, $0 +@000002bc MIPS (ID): lw $31, 36($29) (36) +@000002c0 MIPS (ID): lw $30, 32($29) (32) +@000002c4 MIPS (ID): jr $31 + * UNKNOWN FUNCTION CODE FOR R-format +@000002c8 MIPS (ID): addiu $29, $29, 40 +@000002cc MIPS (ID): addiu $29, $29, -80 +@000002d0 MIPS (ID): sw $30, 72($29) (72) +@000002d4 MIPS (ID): or $30, $29, $0 +@000002d8 MIPS (ID): addiu $2, $0, 23 +@000002dc MIPS (ID): sw $2, 52($30) (52) +@000002e0 MIPS (ID): addiu $2, $0, 24 +@000002e4 MIPS (ID): sw $2, 56($30) (56) +@000002e8 MIPS (ID): addiu $2, $0, 13 +@000002ec MIPS (ID): sw $2, 0($30) (0) +@000002f0 MIPS (ID): addiu $2, $0, 34 +@000002f4 MIPS (ID): sw $2, 4($30) (4) +@000002f8 MIPS (ID): addiu $2, $0, 86 +@000002fc MIPS (ID): sw $2, 8($30) (8) +@00000300 MIPS (ID): addiu $2, $0, 23 +@00000304 MIPS (ID): sw $2, 12($30) (12) +@00000308 MIPS (ID): addiu $2, $0, 52 +@0000030c MIPS (ID): sw $2, 16($30) (16) +@00000310 MIPS (ID): addiu $2, $0, 43 +@00000314 MIPS (ID): sw $2, 20($30) (20) +@00000318 MIPS (ID): addiu $2, $0, 45 +@0000031c MIPS (ID): sw $2, 24($30) (24) +@00000320 MIPS (ID): addiu $2, $0, 87 +@00000324 MIPS (ID): sw $2, 28($30) (28) +@00000328 MIPS (ID): addiu $2, $0, 12 +@0000032c MIPS (ID): sw $2, 32($30) (32) +@00000330 MIPS (ID): addiu $2, $0, 24 +@00000334 MIPS (ID): sw $2, 36($30) (36) +@00000338 MIPS (ID): addiu $2, $0, 35 +@0000033c MIPS (ID): sw $2, 40($30) (40) +@00000340 MIPS (ID): addiu $2, $0, 100 +@00000344 MIPS (ID): sw $2, 44($30) (44) +@00000348 MIPS (ID): lw $3, 52($30) (52) +@0000034c MIPS (ID): lw $2, 56($30) (56) +@00000350 MIPS (ID): nop +@00000354 MIPS (ID): mult [Hi,Lo], $3, $2 + * UNKNOWN FUNCTION CODE FOR R-format +@00000358 MIPS (ID): mflo $2 [Lo] + * UNKNOWN FUNCTION CODE FOR R-format +@0000035c MIPS (ID): sw $2, 48($30) (48) +@00000360 MIPS (ID): nop +@00000364 MIPS (ID): sw $0, 60($30) (60) +@00000368 MIPS (ID): lw $2, 60($30) (60) +@0000036c MIPS (ID): nop +@00000370 MIPS (ID): slti $2, $2, 12 +@00000374 MIPS (ID): bne $0, $2, 3 +@00000378 MIPS (ID): nop +@0000037c MIPS (ID): beq $0, $0, 16 +@00000380 MIPS (ID): nop +@00000384 MIPS (ID): lw $2, 60($30) (60) +@00000388 MIPS (ID): nop +@0000038c MIPS (ID): sll $2, $2, 2 +@00000390 MIPS (ID): addu $4, $30, $2 +@00000394 MIPS (ID): lw $3, 52($30) (52) +@00000398 MIPS (ID): lw $2, 60($30) (60) +@0000039c MIPS (ID): nop +@000003a0 MIPS (ID): mult [Hi,Lo], $3, $2 + * UNKNOWN FUNCTION CODE FOR R-format +@000003a4 MIPS (ID): mflo $2 [Lo] + * UNKNOWN FUNCTION CODE FOR R-format +@000003a8 MIPS (ID): sw $2, 0($4) (0) +@000003ac MIPS (ID): lw $2, 60($30) (60) +@000003b0 MIPS (ID): nop +@000003b4 MIPS (ID): addiu $2, $2, 1 +@000003b8 MIPS (ID): beq $0, $0, -21 +@000003bc MIPS (ID): sw $2, 60($30) (60) +@000003c0 MIPS (ID): addiu $2, $0, 4096 +@000003c4 MIPS (ID): sw $2, 64($30) (64) +@000003c8 MIPS (ID): lw $3, 64($30) (64) +@000003cc MIPS (ID): lw $2, 0($30) (0) +@000003d0 MIPS (ID): nop +@000003d4 MIPS (ID): sw $2, 0($3) (0) +@000003d8 MIPS (ID): addiu $2, $0, 4100 +@000003dc MIPS (ID): sw $2, 64($30) (64) +@000003e0 MIPS (ID): lw $3, 64($30) (64) +@000003e4 MIPS (ID): lw $2, 4($30) (4) +@000003e8 MIPS (ID): nop +@000003ec MIPS (ID): sw $2, 0($3) (0) +@000003f0 MIPS (ID): addiu $2, $0, 4104 +@000003f4 MIPS (ID): sw $2, 64($30) (64) +@000003f8 MIPS (ID): lw $3, 64($30) (64) +@000003fc MIPS (ID): lw $2, 8($30) (8) +@00000400 MIPS (ID): nop +@00000404 MIPS (ID): sw $2, 0($3) (0) +@00000408 MIPS (ID): addiu $2, $0, 4108 +@0000040c MIPS (ID): sw $2, 64($30) (64) +@00000410 MIPS (ID): lw $3, 64($30) (64) +@00000414 MIPS (ID): lw $2, 12($30) (12) +@00000418 MIPS (ID): nop +@0000041c MIPS (ID): sw $2, 0($3) (0) +@00000420 MIPS (ID): addiu $2, $0, 4112 +@00000424 MIPS (ID): sw $2, 64($30) (64) +@00000428 MIPS (ID): lw $3, 64($30) (64) +@0000042c MIPS (ID): lw $2, 16($30) (16) +@00000430 MIPS (ID): nop +@00000434 MIPS (ID): sw $2, 0($3) (0) +@00000438 MIPS (ID): addiu $2, $0, 4116 +@0000043c MIPS (ID): sw $2, 64($30) (64) +@00000440 MIPS (ID): lw $3, 64($30) (64) +@00000444 MIPS (ID): lw $2, 20($30) (20) +@00000448 MIPS (ID): nop +@0000044c MIPS (ID): sw $2, 0($3) (0) +@00000450 MIPS (ID): addiu $2, $0, 4120 +@00000454 MIPS (ID): sw $2, 64($30) (64) +@00000458 MIPS (ID): lw $3, 64($30) (64) +@0000045c MIPS (ID): lw $2, 24($30) (24) +@00000460 MIPS (ID): nop +@00000464 MIPS (ID): sw $2, 0($3) (0) +@00000468 MIPS (ID): addiu $2, $0, 4124 +@0000046c MIPS (ID): sw $2, 64($30) (64) +@00000470 MIPS (ID): lw $3, 64($30) (64) +@00000474 MIPS (ID): lw $2, 28($30) (28) +@00000478 MIPS (ID): nop +@0000047c MIPS (ID): sw $2, 0($3) (0) +@00000480 MIPS (ID): addiu $2, $0, 4128 +@00000484 MIPS (ID): sw $2, 64($30) (64) +@00000488 MIPS (ID): lw $3, 64($30) (64) +@0000048c MIPS (ID): lw $2, 32($30) (32) +@00000490 MIPS (ID): nop +@00000494 MIPS (ID): sw $2, 0($3) (0) +@00000498 MIPS (ID): addiu $2, $0, 4132 +@0000049c MIPS (ID): sw $2, 64($30) (64) +@000004a0 MIPS (ID): lw $3, 64($30) (64) +@000004a4 MIPS (ID): lw $2, 36($30) (36) +@000004a8 MIPS (ID): nop +@000004ac MIPS (ID): sw $2, 0($3) (0) +@000004b0 MIPS (ID): addiu $2, $0, 4136 +@000004b4 MIPS (ID): sw $2, 64($30) (64) +@000004b8 MIPS (ID): lw $3, 64($30) (64) +@000004bc MIPS (ID): lw $2, 40($30) (40) +@000004c0 MIPS (ID): nop +@000004c4 MIPS (ID): sw $2, 0($3) (0) +@000004c8 MIPS (ID): addiu $2, $0, 4140 +@000004cc MIPS (ID): sw $2, 64($30) (64) +@000004d0 MIPS (ID): lw $3, 64($30) (64) +@000004d4 MIPS (ID): lw $2, 44($30) (44) +@000004d8 MIPS (ID): nop +@000004dc MIPS (ID): sw $2, 0($3) (0) +@000004e0 MIPS (ID): addiu $2, $0, 4144 +@000004e4 MIPS (ID): sw $2, 64($30) (64) +@000004e8 MIPS (ID): lw $3, 64($30) (64) +@000004ec MIPS (ID): lw $2, 48($30) (48) +@000004f0 MIPS (ID): nop +@000004f4 MIPS (ID): sw $2, 0($3) (0) +@000004f8 MIPS (ID): lui $2, 32767 +@000004fc MIPS (ID): ori $2, $2, 0xfffffffc +@00000500 MIPS (ID): sw $2, 64($30) (64) +@00000504 MIPS (ID): lw $2, 64($30) (64) +@00000508 MIPS (ID): nop +@0000050c MIPS (ID): sw $0, 0($2) (0) +@00000510 MIPS (ID): or $2, $0, $0 +@00000514 MIPS (ID): or $29, $30, $0 +@00000518 MIPS (ID): lw $30, 72($29) (72) +@0000051c MIPS (ID): jr $31 + * UNKNOWN FUNCTION CODE FOR R-format +@00000520 MIPS (ID): addiu $29, $29, 80 +@00000524 MIPS (ID): nop +@00000528 MIPS (ID): nop +@0000052c MIPS (ID): nop +@00000530 MIPS (ID): sw $0, 2816($0) (2816) +@00000534 MIPS (ID): nop +@00000538 MIPS (ID): nop +@0000053c MIPS (ID): nop +@00000540 MIPS (ID): nop +@00000544 MIPS (ID): nop Index: tags/arelease/PROGRAMMING_exception/mult.hex =================================================================== --- tags/arelease/PROGRAMMING_exception/mult.hex (nonexistent) +++ tags/arelease/PROGRAMMING_exception/mult.hex (revision 13) @@ -0,0 +1,218 @@ +@00000000 08 00 00 04 +@00000004 00 00 00 00 +@00000008 08 00 00 10 +@0000000c 00 00 00 00 +@00000010 3c 1d 00 00 +@00000014 27 bd 3f f0 +@00000018 24 08 00 00 +@0000001c 3c 09 00 00 +@00000020 25 29 40 00 +@00000024 40 1a 60 00 +@00000028 23 5a 00 03 +@0000002c 40 9a 60 00 +@00000030 0c 00 00 b3 +@00000034 00 00 00 00 +@00000038 08 00 00 1f +@0000003c 00 00 00 00 +@00000040 00 00 00 00 +@00000044 40 1a 68 00 +@00000048 40 1b 70 00 +@0000004c 00 1a d0 82 +@00000050 33 5a 00 1f +@00000054 13 40 00 06 +@00000058 00 00 00 00 +@0000005c 00 00 58 20 +@00000060 27 6b 00 04 +@00000064 40 8b 70 00 +@00000068 42 00 00 18 +@0000006c 00 00 00 00 +@00000070 00 00 00 00 +@00000074 42 00 00 18 +@00000078 00 00 00 00 +@0000007c 08 00 00 1f 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ac 40 00 00 +@00000510 00 00 10 25 +@00000514 03 c0 e8 25 +@00000518 8f be 00 48 +@0000051c 03 e0 00 08 +@00000520 27 bd 00 50 +@00000524 00 00 00 00 +@00000528 00 00 00 00 +@0000052c 00 00 00 00 +@00000530 ac 00 0b 00 +@00000534 00 00 00 00 +@00000538 00 00 00 00 +@0000053c 00 00 00 00 +@00000540 00 00 00 00 +@00000544 00 00 00 00 Index: tags/arelease/PROGRAMMING_exception/crt0.S =================================================================== --- tags/arelease/PROGRAMMING_exception/crt0.S (nonexistent) +++ tags/arelease/PROGRAMMING_exception/crt0.S (revision 13) @@ -0,0 +1,69 @@ +/* + * Starting point for everything (bootstrap) + * + * Initializes the stack pointer and jumps to main(). + */ + +#include "regdef.h" + + .text + .align 2 + .globl _start + .ent _start +_start: + .set noreorder + + j reset_handler + nop + + j handling_exception + nop + + +reset_handler: + /* Setup stack pointer */ + la sp, _sp + + /* Clear bss */ + la t0, 0x00000000 /* First address */ + la t1, _end /* Last address */ + + mfc0 k0, $12 + add k0, k0, 3 + mtc0 k0, $12 + + + jal main + nop + j loop + nop + +handling_exception: + nop + mfc0 k0, $13 + mfc0 k1, $14 + + srl k0, k0, 2 + andi k0, k0, 0x1F + + beq k0, $0, handling_interrupt + nop + + add $11, $0, $0 + addiu $11, k1, 4 + mtc0 $11, $14 + eret + nop + + +handling_interrupt: + nop + eret + nop + + /* Run endless loop when the program terminates */ +loop: + j loop + + .set reorder + .end _start Index: tags/arelease/PROGRAMMING_exception/My_Program =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: tags/arelease/PROGRAMMING_exception/My_Program =================================================================== --- tags/arelease/PROGRAMMING_exception/My_Program (nonexistent) +++ tags/arelease/PROGRAMMING_exception/My_Program (revision 13)
tags/arelease/PROGRAMMING_exception/My_Program Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: tags/arelease/PROGRAMMING_exception/Disassembler/DISASSEMBLER_ELF =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: tags/arelease/PROGRAMMING_exception/Disassembler/DISASSEMBLER_ELF =================================================================== --- tags/arelease/PROGRAMMING_exception/Disassembler/DISASSEMBLER_ELF (nonexistent) +++ tags/arelease/PROGRAMMING_exception/Disassembler/DISASSEMBLER_ELF (revision 13)
tags/arelease/PROGRAMMING_exception/Disassembler/DISASSEMBLER_ELF Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: tags/arelease/PROGRAMMING_exception/Disassembler/My_Program.bin =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: tags/arelease/PROGRAMMING_exception/Disassembler/My_Program.bin =================================================================== --- tags/arelease/PROGRAMMING_exception/Disassembler/My_Program.bin (nonexistent) +++ tags/arelease/PROGRAMMING_exception/Disassembler/My_Program.bin (revision 13)
tags/arelease/PROGRAMMING_exception/Disassembler/My_Program.bin Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: tags/arelease/PROGRAMMING_exception/Disassembler/instructions.dat =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: tags/arelease/PROGRAMMING_exception/Disassembler/instructions.dat =================================================================== --- tags/arelease/PROGRAMMING_exception/Disassembler/instructions.dat (nonexistent) +++ tags/arelease/PROGRAMMING_exception/Disassembler/instructions.dat (revision 13)
tags/arelease/PROGRAMMING_exception/Disassembler/instructions.dat Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: tags/arelease/PROGRAMMING_exception/Disassembler/readme.txt =================================================================== --- tags/arelease/PROGRAMMING_exception/Disassembler/readme.txt (nonexistent) +++ tags/arelease/PROGRAMMING_exception/Disassembler/readme.txt (revision 13) @@ -0,0 +1,11 @@ + +Disassembler for MipsR2000 Processor! +This program converts Bin files into HEX or ASM format! + +Usage: + + Type ./DISASSEMBLER_ELF "progran_name.bin" + where "program_name.bin" is the bin file that you want to convert + + In Run-Time Type "A" for ASM format, or "H" for HEX format, and Hit "Enter" + Index: tags/arelease/PROGRAMMING_exception/Makefile =================================================================== --- tags/arelease/PROGRAMMING_exception/Makefile (nonexistent) +++ tags/arelease/PROGRAMMING_exception/Makefile (revision 13) @@ -0,0 +1,88 @@ +# ********************************************** +# Programs to build +# ********************************************** + +PROGS = My_Program + +# ********************************************** +# Endianness EB | EL +# ********************************************** + +#ENDIAN = EB +ENDIAN = EL + +# ********************************************** +# Bootstrap object file +# ********************************************** + +BOOTSTRAP = crt0.o + +# ********************************************** +# Compiler toolchain +# ********************************************** + +ifeq ($(ENDIAN),EL) +CC = mipsel-linux-gcc +LD = mipsel-linux-ld +OBJCOPY = mipsel-linux-objcopy +OBJDUMP = mipsel-linux-objdump +endif + +ifeq ($(ENDIAN),EB) +CC = mips-linux-gcc +LD = mips-linux-ld +OBJCOPY = mips-linux-objcopy +OBJDUMP = mips-linux-objdump +endif + +# ********************************************** +# Compiler and linker options +# ********************************************** + +W_OPTS = -Wimplicit -Wformat -Wall -Wstrict-prototypes +W_OPTS_A = -Wformat -Wall -Wstrict-prototypes + + +CC_OPTS = -Wa,-32 -mips1 -mno-abicalls -fno-pic -G 0 -pipe \ + -D$(ENDIAN) -fno-strict-aliasing -c -nostdinc + +CC_OPTS_A = -Wa,-32 -mips1 -mno-abicalls -fno-pic -G 0 -pipe \ + -D$(ENDIAN) -fno-strict-aliasing -c -nostdinc + + +LD_SCRIPT = link.xn +LD_OPTS = -G 0 -static -T $(LD_SCRIPT) + +ifeq ($(ENDIAN),EB) +LD_FORMAT = elf32-tradbigmips +endif + +ifeq ($(ENDIAN),EL) +LD_FORMAT = elf32-tradlittlemips +endif + + +# ********************************************** +# Rules +# ********************************************** + +%.o : %.c + $(CC) $(W_OPTS) $(CC_OPTS) -o $@ $< + +%.o : %.S + $(CC) $(W_OPTS_A) $(CC_OPTS_A) -o $@ $< + +%.o : %.s + $(CC) $(W_OPTS_A) $(CC_OPTS_A) -o $@ $< + +all: $(PROGS) + + +My_Program : $(BOOTSTRAP) My_Program.o + $(LD) $(LD_OPTS) -o $@ $? + $(OBJCOPY) -O binary $@ $@.bin + +clean : + rm -f $(PROGS) *.bin *.o + rm -f *~ + Index: tags/arelease/PROGRAMMING_exception/My_Program.c =================================================================== --- tags/arelease/PROGRAMMING_exception/My_Program.c (nonexistent) +++ tags/arelease/PROGRAMMING_exception/My_Program.c (revision 13) @@ -0,0 +1,85 @@ +#define memstore(address,save) { \ +unsigned int *ctrlstore = (unsigned int *) address; \ +*ctrlstore = save;} + +#define ADDR_IO 0x00009000 +#define ADDR_STOP 0x7FFFFFFC +#define ADDR_QUICK 0x00003F00 + + +void quicksort (int a[], int lo, int hi) +{ + int i=lo, j=hi, h; + int x=a[(lo+hi)/2]; + + // partition + do + { + while (a[i]x) j--; + if (i<=j) + { + h=a[i]; a[i]=a[j]; a[j]=h; + i++; j--; + } + } while (i<=j); + + // recursion + if (lo + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: tags/arelease/source/top.cpp =================================================================== --- tags/arelease/source/top.cpp (nonexistent) +++ tags/arelease/source/top.cpp (revision 13) @@ -0,0 +1,3 @@ +#include "top.h" + + Index: tags/arelease/source/main.cpp =================================================================== --- tags/arelease/source/main.cpp (nonexistent) +++ tags/arelease/source/main.cpp (revision 13) @@ -0,0 +1,420 @@ +// +// $Id: main.cpp,v 1.1.1.1 2006-01-31 10:55:26 igorloi Exp $ +// +#include +#include "top_debug.h" +#include "./constants/config.h" + +int sc_main(int argc, char *argv[]) +{ + sc_clock clk("clock", 20, SC_NS); + + if (argc == 1) + { + cout << "Usage:" << endl; + cout << argv[0] << " [runlength (ns)]" << endl; + return 0; + } + + + // Istanzio il modulo top level + top_debug *debug_level; + debug_level = new top_debug("debug_level", argv[1]); + debug_level->in_clk(clk.signal()); + + + // Trace file - VCD format... + sc_trace_file * trace_file; + trace_file = sc_create_vcd_trace_file("main.trace"); + +#ifdef SIGNAL_SC_CPU + sc_trace(trace_file, debug_level->top_level->in_clk, "clk"); + sc_trace(trace_file, debug_level->top_level->reset, "reset"); + sc_trace(trace_file, debug_level->top_level->instaddr, "instaddr"); + sc_trace(trace_file, debug_level->top_level->instdataread, "instdataread"); + sc_trace(trace_file, debug_level->top_level->instreq, "instreq"); + sc_trace(trace_file, debug_level->top_level->instrw, "instrw"); + sc_trace(trace_file, debug_level->top_level->insthold, "insthold"); + sc_trace(trace_file, debug_level->top_level->dataaddr, "dataaddr"); + sc_trace(trace_file, debug_level->top_level->dataread_m_dec, "dataread_m_dec"); + sc_trace(trace_file, debug_level->top_level->dataread_dec_cpu, "dataread_dec_cpu"); + sc_trace(trace_file, debug_level->top_level->datawrite, "datawrite"); + sc_trace(trace_file, debug_level->top_level->datareq, "datareq"); + sc_trace(trace_file, debug_level->top_level->datarw, "datarw"); + sc_trace(trace_file, debug_level->top_level->databs, "databs"); + sc_trace(trace_file, debug_level->top_level->datahold, "datahold"); + + sc_trace(trace_file, debug_level->top_level->risc->cpu->enable_pc, "enable_pc"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->enable_fetch, "enable_fetch"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->enable_decode, "enable_decode"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->enable_execute, "enable_execute"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->enable_memstage, "enable_memstage"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_exception, "if_exception"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id_exception, "id_exception"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex_exception, "ex_exception"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem_exception, "mem_exception"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->wb_exception, "wb_exception"); + + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->DBUS, "DBUS"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->data_addrl, "data_addrl"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->data_addrl, "data_addrs"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->ex_m_ovf_excep, "ex_m_ovf_excep"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->ex_m_syscall_exception, "ex_m_syscall_exception"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->ex_m_illegal_instruction, "ex_m_illegal_instruction"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->ex_m_inst_addrl, "ex_m_inst_addrl"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->ex_m_IBUS, "ex_m_IBUS"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_id_instaddr, "if_id_instaddr"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id_ex_instaddr, "id_ex_instaddr"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex_m_instaddr, "ex_m_instaddr"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->m_wb_instaddr, "m_wb_instaddr"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->m_wb_dataaddr, "m_wb_dataaddr"); + sc_trace(trace_file, debug_level->top_level->risc->co0->cause, "cause"); + sc_trace(trace_file, debug_level->top_level->risc->co0->check_excep, "check_excep"); + sc_trace(trace_file, debug_level->top_level->risc->co0->cp0_r->Temp_Status_Register, "cp0_r.Temp_Status_Register"); + sc_trace(trace_file, debug_level->top_level->risc->co0->to_EPC, "to_EPC"); + sc_trace(trace_file, debug_level->top_level->risc->co0->to_BadVAddr, "to_BadVAddr"); + //CP0 REGISTERS + sc_trace(trace_file, debug_level->top_level->risc->co0->cp0_r->cp0regs[8] , "cp0_regs[8]"); + sc_trace(trace_file, debug_level->top_level->risc->co0->cp0_r->cp0regs[14], "cp0_regs[14]"); + sc_trace(trace_file, debug_level->top_level->risc->co0->cp0_r->cp0regs[13], "cp0_regs[13]"); + sc_trace(trace_file, debug_level->top_level->risc->co0->cp0_r->cp0regs[12], "cp0_regs[12]"); + sc_trace(trace_file, debug_level->top_level->risc->co0->sspc->insthold, "sspc.insthold"); + sc_trace(trace_file, debug_level->top_level->risc->co0->sspc->new_pc, "sspc.new_pc"); + sc_trace(trace_file, debug_level->top_level->risc->co0->sspc->load_epc, "sspc.load_epc"); + sc_trace(trace_file, debug_level->top_level->risc->co0->sspc->check_excep, "sspc.check_excep"); + sc_trace(trace_file, debug_level->top_level->risc->co0->sspc->currentstate, "sspc.currentstate"); + sc_trace(trace_file, debug_level->top_level->risc->co0->sspc->nextstate, "sspc.nextstate"); + sc_trace(trace_file, debug_level->top_level->risc->co0->sspc->x_insthold, "sspc.x_insthold"); + sc_trace(trace_file, debug_level->top_level->risc->co0->sspc->in_clk, "sspc.in_clk"); + sc_trace(trace_file, debug_level->top_level->risc->co0->sspc->cp0_inst, "sspc.cp0_inst"); + sc_trace(trace_file, debug_level->top_level->risc->co0->sspc->EPC_FOR_RFE, "sspc.EPC_FOR_RFE"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_mux_fw2, "id.id_mux_fw2"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_sign_extend , "id.id_sign_extend"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->interrupt_signal, "interrupt_signal"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->interrupt_signal_out, "interrupt_signal_out"); + + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->reg_mem1->datahold, "red_mem.datahold"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->reg_mem1->insthold, "reg_mem.insthold"); + + sc_trace(trace_file, debug_level->top_level->risc->cpu->m_wb_interrupt_signal, "m_wb_interrupt_signal"); + sc_trace(trace_file, debug_level->top_level->risc->co0->excp->to_SR, "excp.to_SR");; + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_reg1, "id_reg1"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_reg2, "id_reg2"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->rs, "rs"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->rt, "rt"); + + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->multiply1->stage0, "ex.stage0"); + #ifdef _MULT_PIPELINE_ + #if(DEPTH_MULT_PIPE == 1) + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->multiply1->stage1, "ex.stage1"); + #else + #if(DEPTH_MULT_PIPE == 2) + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->multiply1->stage1, "ex.stage1"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->multiply1->stage2, "ex.stage2"); + #else + #if(DEPTH_MULT_PIPE == 3) + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->multiply1->stage1, "ex.stage1"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->multiply1->stage2, "ex.stage2"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->multiply1->stage3, "ex.stage3"); + #else + #if(DEPTH_MULT_PIPE == 4) + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->multiply1->stage1, "ex.stage1"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->multiply1->stage2, "ex.stage2"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->multiply1->stage3, "ex.stage3"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->multiply1->stage4, "ex.stage4"); + #endif + #endif + #endif + #endif + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->fsm1->ready, "fsm.ready"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->fsm1->current_state, "fsm.current_state"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->fsm1->hold_pipe, "fsm.hold_pipe"); + #endif + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->multiply1->hi, "ex.hi"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->multiply1->lo, "ex.lo"); + + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_id_inst, "cpu.if_id_inst"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id_ex_inst, "cpu.id_ex_inst"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex_mem_inst, "cpu.ex_mem_inst"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem_wb_inst, "cpu.mem_wb_inst"); + + + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_alu_function, "ex.id_ex_alu_function"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_alu_opcode, "ex.id_ex_alu_opcode"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_function, "id.id_function"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_opcode, "id.id_opcode"); +#endif + +#ifdef SIGNAL_DATAMEM + // MEMORY3 + sc_trace(trace_file, debug_level->top_level->datamem->memaddr, "datamem.dataaddr"); + sc_trace(trace_file, debug_level->top_level->datamem->memdataread, "datamem.dataread"); + sc_trace(trace_file, debug_level->top_level->datamem->memdatawrite, "datamem.datawrite"); + sc_trace(trace_file, debug_level->top_level->datamem->memreq, "datamem.datareq"); + sc_trace(trace_file, debug_level->top_level->datamem->memrw, "datamem.datarw"); + + sc_trace(trace_file, debug_level->top_level->datamem->addrl, "data_addrl"); + sc_trace(trace_file, debug_level->top_level->datamem->addrs, "data_addrs"); + sc_trace(trace_file, debug_level->top_level->datamem->page_fault, "DBUS"); + +#endif + +#ifdef SIGNAL_PC_STAGE + // PC State + sc_trace(trace_file, debug_level->top_level->risc->cpu->pc->in_clk, "in_clk"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->pc->reset, "reset"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->pc->insthold, "insthold"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->pc->datahold, "datahold"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->pc->pc_in, "pc_in"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->pc->pc_out, "pc_out"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->pc->instaddr, "instaddr"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->pc->instdatawrite, "instdatawrite"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->pc->instreq, "instreq"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->pc->instrw, "instrw"); +#endif + +#ifdef SIGNAL_IF_STAGE + // IF State + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->in_clk, "in_clk"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->reset, "reset"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->insthold, "insthold"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->datahold, "datahold"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->pc_out, "pc_out"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->id_new_pc, "id_new_pc"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->id_jmp_tar, "id_jmp_tar"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->id_ctrl, "id_ctrl"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->id_branch, "id_branch"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->pc_in, "pc_in"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->instdataread, "instdataread"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->if_id_inst, "if_id_inst"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->if_id_next_pc, "if_id_next_pc"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->new_pc, "new_pc"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->load_epc, "load_epc"); +#endif + +#ifdef SIGNAL_ID_STAGE + // ID Stage + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->in_clk, "in_clk"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->reset, "reset"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->insthold, "insthold"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->datahold, "datahold"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->if_id_next_pc, "if_id_next_pc"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->if_id_inst, "if_id_inst"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_jmp_tar, "id_jmp_tar"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_new_pc, "id_new_pc"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_ctrl, "id_ctrl"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_branch, "id_branch"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_ex_alu1, "id_ex_alu1"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_ex_alu2, "id_ex_alu2"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_ex_datastore, "id_ex_datastore"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_alu_ctrl, "id_alu_ctrl"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_ex_equal, "id_ex_equal"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_ex_byteselect, "id_ex_byteselect"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_ex_bssign, "id_ex_bssign"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_ex_alu_sa, "id_ex_alu_sa"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_ex_datareq, "id_ex_datareq"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_ex_datarw, "id_ex_datarw"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_ex_memtoreg, "id_ex_memtoreg"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_ex_writeregister_out, "id_ex_writeregister_out"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_ex_regwrite_out, "id_ex_regwrite_out"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_ex_m_writeregister, "id_ex_m_writeregister"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_ex_m_wb_writeregister, "id_ex_m_wb_writeregister"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_ex_m_regwrite, "id_ex_m_regwrite"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_ex_m_wb_regwrite, "id_ex_m_wb_regwrite"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->ex_id_forward, "ex_id_forward"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->m_id_forward, "m_id_forward"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->wb_id_forward, "wb_id_forward"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->cp0_inst, "cp0_inst"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->cp0_reg_no, "cp0_reg_no"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->cp0_reg_rw, "cp0_reg_rw"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->cp0_reg_rs, "cp0_reg_rs"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->cp0_reg_out, "cp0_reg_out"); + + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[1], "$1"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[2], "$2"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[3], "$3"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[4], "$4"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[5], "$5"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[6], "$6"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[7], "$7"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[8], "$8"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[9], "$9"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[10], "$10"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[11], "$11"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[12], "$12"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[13], "$13"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[14], "$14"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[15], "$15"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[16], "$16"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[17], "$17"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[18], "$18"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[19], "$19"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[20], "$20"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[21], "$21"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[22], "$22"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[23], "$23"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[24], "$24"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[25], "$25"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[26], "$26"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[27], "$27"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[28], "$28"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[29], "$29"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[30], "$30"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->localreg->r[31], "$31"); + +#endif + +#ifdef SIGNAL_EX_STAGE + // EX Stage + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->in_clk, "in_clk"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->reset, "reset"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->insthold, "insthold"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->datahold, "datahold"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_alu1, "id_ex_alu1"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_alu2, "id_ex_alu2"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_datastore, "id_ex_datastore"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_alu_ctrl, "id_ex_alu_ctrl"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_equal, "id_ex_equal"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_byteselect, "id_ex_byteselect"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_bssign, "id_ex_bssign"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_alu_sa, "id_ex_alu_sa"); + + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_datareq, "id_ex_datareq"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_datarw, "id_ex_datarw"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_memtoreg, "id_ex_memtoreg"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_writeregister_out, "id_ex_writeregister_out"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_regwrite_out, "id_ex_regwrite_out"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_m_writeregister, "id_ex_m_writeregister"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_m_regwrite, "id_ex_m_regwrite"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_m_datareq, "id_ex_m_datareq"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_m_datarw, "id_ex_m_datarw"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_m_datastore, "id_ex_m_datastore"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->ex_m_alu, "ex_m_alu"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_m_memtoreg, "id_ex_m_memtoreg"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->ex_id_forward, "ex_id_forward"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_m_byteselect, "id_ex_m_byteselect"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->id_ex_m_bssign, "id_ex_m_bssign"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->ovf_excep, "ovf_excep"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->addr_err, "addr_err"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->multiply1->lo, "multiply.lo"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex->multiply1->hi, "multiply.hi"); + + +#endif + +#ifdef SIGNAL_MEM_STAGE + // MEM Stage + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->in_clk, "in_clk"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->reset, "reset"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->insthold, "insthold"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->datahold, "datahold"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->id_ex_m_datareq, "id_ex_m_datareq"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->id_ex_m_datarw, "id_ex_m_datarw"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->id_ex_m_datastore, "id_ex_m_datastore"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->ex_m_alu, "ex_m_alu"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->id_ex_m_memtoreg, "id_ex_m_memtoreg"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->id_ex_m_byteselect, "id_ex_m_byteselect"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->id_ex_m_bssign, "id_ex_m_bssign"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->dataread, "dataread"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->datawrite, "datawrite"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->dataaddr, "dataaddr"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->datareq, "datareq"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->datarw, "datarw"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->databs, "databs"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->id_ex_m_writeregister, "id_ex_m_writeregister"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->id_ex_m_regwrite, "id_ex_m_regwrite"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->id_ex_m_wb_writeregister, "id_ex_m_wb_writeregister"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->m_id_forward, "m_id_forward"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->wb_id_forward, "wb_id_forward"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->id_store, "id_store"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->id_ex_m_wb_regwrite, "id_ex_m_wb_regwrite"); + + +#endif + +#ifdef SIGNAL_CP0 + // cp0 + sc_trace(trace_file, debug_level->top_level->risc->co0->in_clk, "in_clk"); + sc_trace(trace_file, debug_level->top_level->risc->co0->reset, "reset"); + sc_trace(trace_file, debug_level->top_level->risc->co0->pc_out, "pc_out"); + sc_trace(trace_file, debug_level->top_level->risc->co0->pc_in, "pc_in"); + sc_trace(trace_file, debug_level->top_level->risc->co0->id_ex_datarw, "id_ex_datarw"); + sc_trace(trace_file, debug_level->top_level->risc->co0->id_ex_datareq, "id_ex_datareq"); + sc_trace(trace_file, debug_level->top_level->risc->co0->id_branch, "id_branch"); + sc_trace(trace_file, debug_level->top_level->risc->co0->id_ctrl, "id_ctrl"); + sc_trace(trace_file, debug_level->top_level->risc->co0->new_pc, "new_pc"); + sc_trace(trace_file, debug_level->top_level->risc->co0->load_epc, "load_epc"); + sc_trace(trace_file, debug_level->top_level->risc->co0->m_wb_ovf_excep, "m_wb_ovf_excep"); + sc_trace(trace_file, debug_level->top_level->risc->co0->ex_alu, "ex_alu"); + sc_trace(trace_file, debug_level->top_level->risc->co0->addr_err, "addr_err"); + sc_trace(trace_file, debug_level->top_level->risc->co0->cp0_inst, "cp0_inst"); + + sc_trace(trace_file, debug_level->top_level->risc->co0->x_insthold, "x_insthold"); + sc_trace(trace_file, debug_level->top_level->risc->co0->insthold, "insthold"); + + sc_trace(trace_file, debug_level->top_level->risc->co0->reg_no, "reg_no"); + sc_trace(trace_file, debug_level->top_level->risc->co0->reg_rw, "reg_rw"); + sc_trace(trace_file, debug_level->top_level->risc->co0->reg_rs, "reg_rs"); + sc_trace(trace_file, debug_level->top_level->risc->co0->reg_out, "reg_out"); +#endif + +#ifdef ONEHOT_DEBUG + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->inst_jalr, "onehot_debug.inst_jalr"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->inst_addiu, "onehot_debug.inst_addiu"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->inst_lw, "onehot_debug.inst_lw"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->inst_mtc0, "onehot_debug.inst_mtc0"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->inst_mfc0, "onehot_debug.inst_mfc0"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->inst_nop, "onehot_debug.inst_nop"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->inst_sw, "onehot_debug.inst_sw"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->inst_wait, "onehot_debug.inst_wait"); +#endif + +#ifdef SIGNAL_INTERRUPT + + // remaining inputs/outputs + sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->pc_out, "cp0.pc_out"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->pc_in, "cp0.pc_in"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->id_ex_datarw, "cp0.id_ex_datarw"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->id_ex_datareq, "cp0.id_ex_datareq"); + /* + sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->id_branch, "cp0.id_branch"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->id_ctrl, "cp0.id_ctrl"); + */ + sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->new_pc, "cp0.new_pc"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->load_epc, "cp0.load_epc"); + /* + sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->ovf_excep, "cp0.ovf_excep"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->addr_err, "cp0.addr_err"); + */ + sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->cp0_inst, "cp0.cp0_inst"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->x_insthold, "cp0.x_insthold"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->insthold, "cp0.insthold"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->reg_no, "cp0.reg_no"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->reg_rw, "cp0.reg_rw"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->reg_rs, "cp0.reg_rs"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->reg_out, "cp0.reg_out"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->co0->currentstate, "cp0.currentstate"); + + +#endif + + ///////////////////////////////////////////////////////////////// + // Start the simulation + ///////////////////////////////////////////////////////////////// + + cout << "--->Start<---" << endl; + sc_report::suppress_warnings(true); + + int runtime; + if (argc == 3) + runtime = atoi(argv[2]); + else + runtime = -1; + + sc_start(runtime); + + + sc_close_vcd_trace_file(trace_file); + + return 0; +} Index: tags/arelease/source/top_debug.cpp.BAK =================================================================== --- tags/arelease/source/top_debug.cpp.BAK (nonexistent) +++ tags/arelease/source/top_debug.cpp.BAK (revision 13) @@ -0,0 +1,439 @@ +#include "top_debug.h" + +void decode(sc_lv<32> if_id_inst, unsigned int i, ostream& out) +{ + + sc_lv<32> inst = if_id_inst; + sc_lv<6> func = inst.range(5,0); + sc_lv<6> op = inst.range(31,26); + + char *charinst=0; + + sc_lv<5> rs, rt ,rd ,lrs, lrt, lrd, lsa; // lv version of reg # + sc_uint<5> uirs, uirt, uird, uisa; // unsigned integer version of reg # + sc_int<32> is, it, id; // integer version of register contents... + + //! The immediate value in an instruction + sc_lv<16> imm; + sc_lv<32> imm_sign, imm_zero; + sc_int<32> iimm_sign, iimm_zero; + sc_uint<32> uiimm_sign, uiimm_zero; + sc_lv<28> instr_index; + sc_uint<28> uiinstr_index; + + // register destinations and recipients + rs = inst.range(25,21); + rt = inst.range(20,16); + rd = inst.range(15,11); + uirs = lrs = inst.range(25,21); + uirt = lrt = inst.range(20,16); + uird = lrd = inst.range(15,11); + uisa = lsa = inst.range(10,6); + + + // Immediate values + imm = inst.range(15,0); + uiimm_zero = iimm_zero = imm_zero = (HALFWORD_ZERO,imm); + if( imm[15] == '1') + uiimm_sign = iimm_sign = imm_sign = (HALFWORD_ONE,imm); + else + uiimm_sign = iimm_sign = imm_sign = (HALFWORD_ZERO,imm); + + uiinstr_index = instr_index = (inst.range(25,0), "00"); + + + + //switch stage + if(op == OP_RFORMAT) + { + if(func == FUNC_JR) + { + out << " MIPS (ID): jr $"<< dec << (unsigned int)uirs << endl; + } + else if(func == FUNC_JALR) + { + if (uird == 0) + out << " MIPS (ID): jalr $" << dec << (unsigned int)uirs << endl; + else + out << " MIPS (ID): jalr $" << dec << (unsigned int)uird << ", $" << dec << (unsigned int)uirs << endl; + } + + /* + + */ + else + if(func == FUNC_MTHI || + func == FUNC_MFLO || + func == FUNC_MULT || + func == FUNC_MULTU || + func == FUNC_DIV || + func == FUNC_DIVU) + + if (func == FUNC_MTHI) {charinst = "mthi"; out << " MIPS (ID): " << charinst << " $" << dec << (unsigned int) uirs << " [Hi]" << endl;} + + if (func == FUNC_MFLO) {charinst = "mflo"; out << " MIPS (ID): " << charinst << " $" << dec << (unsigned int) uird << " [Lo]" << endl;} + + if (func == FUNC_MULT) {charinst = "mult"; out << " MIPS (ID): " << charinst << " [Hi,Lo]," <<" $" << dec << (unsigned int)uirs << ", $" << dec << (unsigned int)uirt << endl;} + + if (func == FUNC_MULTU) {charinst = "multu"; out << " MIPS (ID): " << charinst <<" [Hi,Lo], $" << dec << (unsigned int)uirs << ", $" << dec << (unsigned int)uirt << endl;} + + if (func == FUNC_DIV) {charinst = "div"; out << " MIPS (ID): " << charinst << " [Quoz = Hi, Resto = Lo], $" << dec << (unsigned int)uirs << ", $" << dec << (unsigned int)uirt << endl;} + + if (func == FUNC_DIVU) {charinst = "divu"; out << " MIPS (ID): " << charinst << " [Quoz = Hi, Rest = Lo], $" << dec << (unsigned int)uirs << ", $" << dec << (unsigned int)uirt << endl;} + + + else if(func == FUNC_SLL || + func == FUNC_SRL || + func == FUNC_SRA) + { + if (func == FUNC_SLL) charinst = "sll"; + if (func == FUNC_SRL) charinst = "srl"; + if (func == FUNC_SRA) charinst = "sra"; + if (func == FUNC_SLL && (unsigned int)uird == 0) + out << " MIPS (ID): nop" << endl; + else + out << " MIPS (ID): " << charinst << " $" << dec << (unsigned int)uird <<", $" << dec << (unsigned int)uirt <<", " << dec << (unsigned int)uisa << endl; + } + else if(func == FUNC_SLLV || + func == FUNC_SRLV || + func == FUNC_SRAV || + func == FUNC_ADD || + func == FUNC_ADDU || + func == FUNC_SUB || + func == FUNC_SUBU || + func == FUNC_AND || + func == FUNC_OR || + func == FUNC_XOR || + func == FUNC_NOR || + func == FUNC_SLT || + func == FUNC_SLTU) + { + + // printf("MIPS (ID): R-Format - read next line!\n"); + if (func == FUNC_SLLV) charinst = "sllv"; + if (func == FUNC_SRLV) charinst = "srlv"; + if (func == FUNC_SRAV) charinst = "srav"; + if (func == FUNC_ADD) charinst = "add"; + if (func == FUNC_ADDU) charinst = "addu"; + if (func == FUNC_SUB) charinst = "sub"; + if (func == FUNC_SUBU) charinst = "subu"; + if (func == FUNC_AND) charinst = "and"; + if (func == FUNC_OR) charinst = "or"; + if (func == FUNC_XOR) charinst = "xor"; + if (func == FUNC_NOR) charinst = "nor"; + if (func == FUNC_SLT) charinst = "slt"; + if (func == FUNC_SLTU) charinst = "sltu"; + out << " MIPS (ID): " << charinst << " $" << dec << (unsigned int)uird << ", $" << dec << (unsigned int)uirs << ", $" << dec << (unsigned int)uirt << endl; + } + else if (func == FUNC_BREAK) + { + out << " MIPS (ID): BREAK" << endl; + } + + else if (func == FUNC_SYSCALL) + { + out << " MIPS (ID): SYSCALL" << endl; + } + + else if (func == FUNC_BREAK || func == FUNC_SYSCALL) + { + out << " Exception!!" << endl; + } + + else + { + out << " * UNKNOWN FUNCTION CODE FOR R-format" << endl; + } + } + else if(op == OP_BRANCH) + { + // PRINTLN("Branch format"); + if(lrt.range(1,0) == BRANCH_BLTZ) + { + out << " MIPS (ID): bltz $" << dec << (unsigned int)uirs << ", " << dec << (unsigned int)iimm_sign << endl; + } + + else if(lrt.range(1,0) == BRANCH_BGEZ) + { + out << " MIPS (ID): bgez $" << dec << (unsigned int)uirs << ", " << dec << (unsigned int)iimm_sign << endl; + } + + else if(lrt.range(1,0) == BRANCH_BLTZAL) + { + out << " MIPS (ID): bltzal $"<< dec << (unsigned int)uirs << ", " << dec << (unsigned int)iimm_sign << endl; + } + else if(lrt.range(1,0) == BRANCH_BGEZAL) + { + + out << " MIPS (ID): bgezal $" << dec << (unsigned int)uirs << ", " << dec << (unsigned int)iimm_sign << endl; + } + } + + + else if(op == OP_J) + { + + out << " MIPS (ID): j "<< dec << (unsigned int) uiinstr_index << endl; + } + + + else if(op == OP_JAL) + { + out << " MIPS (ID): jal " << dec << (unsigned int) uiinstr_index << endl; + } + + + else if(op == OP_BEQ) + { + out << " MIPS (ID): beq $" << dec << (unsigned int)uirt << ", $" << dec << (unsigned int)uirs << ", " << dec << (unsigned int)iimm_sign << endl; + } + + + else if(op == OP_BNE) + { + out << " MIPS (ID): bne $"<< dec << (unsigned int)uirt << ", $" << dec << (unsigned int)uirs << ", " << dec << (unsigned int)iimm_sign << endl; + } + + + else if(op == OP_BLEZ) + { + out << " MIPS (ID): blez $" << dec << (unsigned int) uirs << ", " << dec << (unsigned int) iimm_sign << endl; + } + + + else if(op == OP_BGTZ) + { + out << " MIPS (ID): bgtz $" << dec << (unsigned int)uirs << ", " << (unsigned int)iimm_sign << endl; + } + + + else if(op == OP_ADDI) + { + out << " MIPS (ID): addi $" << dec << (unsigned int)uirt << ", $" << dec << (unsigned int)uirs << ", " << dec << (unsigned int)iimm_sign << endl; + } + + + else if(op == OP_ADDIU) + { + out << " MIPS (ID): addiu $" << dec << (unsigned int)uirt << ", $" << dec << (unsigned int)uirs << ", " << dec << (int)uiimm_sign << endl; + } + + + else if(op == OP_SLTI) + { + out << " MIPS (ID): slti $" << dec << (unsigned int)uirt << ", $" << dec << (unsigned int)uirs << ", " << dec << (unsigned int)iimm_sign << endl; + } + + + else if(op == OP_SLTIU) + { + out << " MIPS (ID): sltiu $" << dec << (unsigned int)uirt << ", $" << dec << (unsigned int)uirs << ", " << dec << (unsigned int)iimm_sign << endl; + } + + + else if(op == OP_ANDI) + { + out << " MIPS (ID): andi $" << dec << (unsigned int)uirt << ", $" << dec << (unsigned int)uirs << ", 0x" << hex << (unsigned int)iimm_sign << endl; + } + + + else if(op == OP_ORI) + { + out << " MIPS (ID): ori $" << dec << (unsigned int)uirt << ", $" << dec << (unsigned int)uirs << ", 0x" << hex << (unsigned int)iimm_sign << endl; + } + + + else if(op == OP_XORI) + { + out << " MIPS (ID): xori $" << dec << (unsigned int)uirt << ", $" << dec << (unsigned int)uirs << ", 0x" << hex << (unsigned int)iimm_sign << endl; + } + + + else if(op == OP_LUI) + { + out << " MIPS (ID): lui $" << dec << (unsigned int)uirt << ", " << dec << (unsigned int)iimm_sign << endl; + } + + + else if(op == OP_LB || + op == OP_LH || + op == OP_LWL || + op == OP_LW || + op == OP_LBU || + op == OP_LHU || + op == OP_LWR) + { + if (op == OP_LB) charinst = "lb"; + if (op == OP_LH) charinst = "lh"; + if (op == OP_LWL) charinst = "lwl"; + if (op == OP_LW) charinst = "lw"; + if (op == OP_LBU) charinst = "lbu"; + if (op == OP_LHU) charinst = "lhu"; + if (op == OP_LWR) charinst = "lwr"; + out << " MIPS (ID): " << charinst << " $" << dec << (unsigned int)uirt << ", " << dec << (unsigned int)iimm_sign << "($" << dec << (unsigned int)uirs << ") (" << dec << (unsigned int)(is + iimm_sign) << ")" << endl; + } + + + else if(op == OP_SB || + op == OP_SH || + op == OP_SWL || + op == OP_SW || + op == OP_SWR) + { + if (op == OP_SB) charinst = "sb"; + if (op == OP_SH) charinst = "sh"; + if (op == OP_SWL) charinst = "swl"; + if (op == OP_SW) charinst = "sw"; + if (op == OP_SWR) charinst = "swr"; + out << " MIPS (ID): " << charinst <<" $" << dec << (unsigned int)uirt << ", " << dec << (unsigned int)iimm_sign << "($" << dec << (unsigned int)uirs << ") (" << dec << (unsigned int)(is + iimm_sign) << ")" << endl; + } + + + else if(op == OP_CACHE) + { + out << " MIPS (ID): CACHE $" << dec << (unsigned int)uirt << ", $" << dec << (unsigned int)iimm_sign.range(15,0) << "(" << dec << (unsigned int) uirs << ")" << endl; + } + + + else if(op == OP_COPROC0) + { + out << " MIPS (ID): CP0 instruction" << endl; + } + else + { + if(lrs == RS_MFC0) + { + out << " MIPS (ID): mfc0 $" << dec << (unsigned int)uirt << ", $" << dec << (unsigned int)uird << endl; + } + else if(lrs == RS_MTC0) + { + out << " MIPS (ID): mtc0 $" << dec << (unsigned int)uirt << ", $" << dec << (unsigned int)uird << endl; + } + } + } + + + + + + + + + +void top_debug::debug_signals() +{ + ofstream out("GIGINO.txt"); + + out << endl; + out << "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx" << endl; + out << " Simulationon after " << sc_simulation_time() << "ns Clock n°" << sc_simulation_time()/20 << " Reset =" << top_level->reset << endl; + out << "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx" << endl; + out << endl; + + //PC_STAGE + out << "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx PC_STAGE xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx" << endl; + out << " pc_in " << hex << setw(8) << setfill('0') << (unsigned int) ((sc_uint<32>) top_level->risc->cpu->pc->pc_in) << endl; + out << " pc_out " << hex << setw(8) << setfill('0') << (unsigned int) ((sc_uint<32>) top_level->risc->cpu->pc->pc_out) << endl; + out << " enable_pc " << top_level->risc->cpu->pc->enable_pc << endl; + out << "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx" << endl; + out << endl; + + //IF_STAGE + out << "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx IF_STAGE xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx" << endl; + out << " instadataread " << hex << setw(8) << setfill('0') << (unsigned int) ((sc_uint<32>) top_level->risc->cpu->if_s->instdataread) << endl; + out << " if_id_next_pc " << hex << setw(8) << setfill('0') << (unsigned int) ((sc_uint<32>) top_level->risc->cpu->if_s->if_id_next_pc) << endl; + out << " enable_if " << top_level->risc->cpu->if_s->enable_fetch << endl; + out << "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx" << endl; + out << endl; + + + + + + + + //ID_STAGE + out << "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx ID_STAGE xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx" << endl; + + decode(top_level->instdataread,((unsigned int) ((sc_uint<32>)(top_level->instaddr))), out); + + out << "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx REGISTERS xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx" << endl; + out << endl; + for (int n=0; n < 8; n++) + { + out << "$"<< dec << n <<" = 0x" << hex << setw(8) << setfill('0') <<(unsigned int) ((sc_uint<32>)(top_level->risc->cpu->id->localreg->r[n])); + + out << " $"<< dec << n+8 <<" = 0x" << hex << setw(8) << setfill('0') <<(unsigned int) ((sc_uint<32>)(top_level->risc->cpu->id->localreg->r[n+8])); + + out << " $"<< dec << n+16 <<" = 0x" << hex << setw(8) << setfill('0') <<(unsigned int) ((sc_uint<32>)(top_level->risc->cpu->id->localreg->r[n+16])); + + out << " $"<< dec << n+24 <<" = 0x" << hex << setw(8) << setfill('0') <<(unsigned int) ((sc_uint<32>)(top_level->risc->cpu->id->localreg->r[n+24]))<< endl; + + } + + out << " [HI] = " << hex << setw(8) << setfill('0') << (unsigned int) ((sc_uint<32>) top_level->risc->cpu->ex->out_hi) << endl; + + out << " [LO] = " << hex << setw(8) << setfill('0') << (unsigned int) ((sc_uint<32>) top_level->risc->cpu->ex->out_lo) << endl; + + + out << endl; + out << "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx DATA xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx" << endl; + + out << " dataaddr = 0x" << hex << setw(8) << setfill('0') << (unsigned int) ((sc_uint<32>)(top_level->dataaddr)) << endl; + out << " dataread = 0x" << hex << setw(8) << setfill('0') << (unsigned int) ((sc_uint<32>) (top_level->dataread_dec_cpu)) << " ("<< top_level->dataread_dec_cpu <<")"<< endl; + out << " datawrite = 0x" << hex << setw(8) << setfill('0') << (unsigned int) ((sc_uint<32>) (top_level->datawrite)) << " ("<< top_level->datawrite <<")"<< endl; + out << " datareq = " << top_level->datarw << endl; + out << " datarw = " << top_level->datareq << endl; + out << " databs = " << top_level->databs << endl; + + out << endl; + out << "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx INST_MEM xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx" << endl; + + + + out << " PC = 0x" << hex << setw(8) << setfill('0') << ((unsigned int)((sc_uint<32>)(top_level->instaddr))) << endl; + out << " InstDataRead = 0x" << hex << setw(8) << setfill('0') << (unsigned int) ((sc_uint<32>) (top_level->instdataread)) << " " << top_level->instdataread << endl; + + out << " instreq = " << top_level->instreq << endl; + + out << endl; + out << endl; + + + out << "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx MEMORY xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx" << endl; + + int temp, temp2, Start, Stop; + Start = Start_pos; + Stop = Finish_pos; + temp = (Start + (Stop - Start)/4); + temp2 = ((Stop - Start)/4); + + for(int n= Start; n < temp; n=n+4) + { + out << "[0x"<< hex << n << "] = "<< hex << setw(8) << setfill('0') << top_level->datamem->x[(n >> 2)] << " "; + + out << "[0x"<< hex << (n + temp2) << "] = "<< hex << setw(8) << setfill('0') << top_level->datamem->x[((n+temp2) >> 2)] << " "; + + out << "[0x"<< hex << (n + 2*temp2) << "] = "<< hex << setw(8) << setfill('0') << top_level->datamem->x[((n+2*temp2) >> 2)] << " "; + + out << "[0x"<< hex << (n + 3*temp2) << "] = "<< hex << setw(8) << setfill('0') << top_level->datamem->x[((n+3*temp2) >> 2)] << " " << endl; + + /*out << "cella [0x"<< hex << (n+8) << "] = "<< hex << setw(8) << setfill('0') << top_level->datamem->x[((n+8) >> 2)] << " "; + + out << "cella [0x"<< hex << (n+12) << "] = "<< hex << setw(8) << setfill('0') << top_level->datamem->x[((n+12) >> 2)] << endl;*/ + + } + + + + char buffer[256]; + ifstream examplefile ("GIGINO.txt"); + if (! examplefile.is_open()) + { cout << "Error opening file"; exit (1); } + + while (! examplefile.eof() ) + { + examplefile.getline (buffer,100); + fprintf (fp ,"%s\n", buffer); + } +} Index: tags/arelease/source/cpu/id_stage/reg_id.h =================================================================== --- tags/arelease/source/cpu/id_stage/reg_id.h (nonexistent) +++ tags/arelease/source/cpu/id_stage/reg_id.h (revision 13) @@ -0,0 +1,88 @@ +#include "systemc.h" +#include "../../constants/constants.h" + +SC_MODULE(reg_id) +{ + sc_in in_clk; + sc_in reset; + sc_in datahold; + sc_in insthold; + + sc_out > id_ex_alu1; + sc_in > id_alu1; + + sc_out > id_ex_alu2; + sc_in > id_alu2; + + sc_out > id_ex_datastore; + sc_in > id_mux_fw2; + + sc_out > id_ex_alu_ctrl; + sc_in > id_alu_ctrl; + + sc_out > id_ex_alu_opcode; + sc_in > id_opcode; + + sc_out > id_ex_alu_function; + sc_in > id_function; + + sc_out > id_ex_alu_sa; + sc_in > id_alu_sa; + + sc_out id_ex_equal; + sc_in id_equal; + + sc_out id_ex_datareq; + sc_in id_datareq; + + sc_out id_ex_datarw; + sc_in id_datarw; + + sc_out id_ex_memtoreg; + sc_in id_memtoreg; + + sc_out > id_ex_writeregister_out; + sc_in > id_writeregister; + + sc_out > id_ex_writeregister; + //sc_in > id_writeregister; + + sc_out id_ex_regwrite_out; + sc_in id_regwrite; + + sc_out id_ex_regwrite; + //sc_in id_regwrite; + + sc_out > id_ex_byteselect; + sc_in > id_byteselect; + + sc_out id_ex_bssign; + sc_in id_bssign; + + sc_in > if_id_inst; + sc_out > id_ex_inst; + + // EXCEPTIONS SIGNALS + sc_in illegal_instruction; + sc_in syscall_exception; + sc_in if_id_IBUS; + sc_in if_id_inst_addrl; + sc_out id_ex_IBUS; + sc_out id_ex_inst_addrl; + sc_out id_ex_syscall_exception; + sc_out id_ex_illegal_instruction; + + sc_in > if_id_instaddr; + sc_out > id_ex_instaddr; + + sc_in enable_decode; + + void do_reg_id(); + + SC_CTOR(reg_id) + { + SC_METHOD(do_reg_id); + //sensitive_pos << reset; + sensitive_pos << in_clk; + } +}; Index: tags/arelease/source/cpu/id_stage/mux_alu1.h =================================================================== --- tags/arelease/source/cpu/id_stage/mux_alu1.h (nonexistent) +++ tags/arelease/source/cpu/id_stage/mux_alu1.h (revision 13) @@ -0,0 +1,23 @@ +#include "systemc.h" +#include "../../constants/constants.h" + +SC_MODULE(mux_alu1) +{ + sc_in > if_id_inst; + sc_in id_shamt_ctrl; + sc_in id_pc_store; + sc_out > id_alu1; + sc_in > if_id_next_pc; + sc_in > cp0_reg_out; + sc_in > id_mux_fw1; + sc_in id_mfc0; + + void do_mux_alu1(); + + SC_CTOR(mux_alu1) + { + SC_METHOD(do_mux_alu1); + sensitive << id_pc_store << id_shamt_ctrl << if_id_inst << id_mux_fw1; + sensitive << if_id_next_pc << cp0_reg_out << id_mfc0; + } +}; Index: tags/arelease/source/cpu/id_stage/mux_alu2.h =================================================================== --- tags/arelease/source/cpu/id_stage/mux_alu2.h (nonexistent) +++ tags/arelease/source/cpu/id_stage/mux_alu2.h (revision 13) @@ -0,0 +1,19 @@ +#include "systemc.h" +#include "../../constants/constants.h" + +SC_MODULE(mux_alu2) +{ + sc_in > id_sign_extend; + sc_in > id_sign_ctrl; + sc_out > id_alu2; + sc_out > cp0_reg_rs; + sc_in > id_mux_fw2; + + void do_mux_alu2(); + + SC_CTOR(mux_alu2) + { + SC_METHOD(do_mux_alu2); + sensitive << id_mux_fw2 << id_sign_extend << id_sign_ctrl; + } +}; Index: tags/arelease/source/cpu/id_stage/mux_forward_select.h =================================================================== --- tags/arelease/source/cpu/id_stage/mux_forward_select.h (nonexistent) +++ tags/arelease/source/cpu/id_stage/mux_forward_select.h (revision 13) @@ -0,0 +1,21 @@ +#include "systemc.h" +#include "../../constants/constants.h" + +SC_MODULE(mux_forward_select) +{ + sc_in > id_reg; + sc_in > ex_id_forward; + sc_in > m_id_forward; + sc_in > wb_id_forward; + sc_in > id_fw_ctrl; + + sc_out > id_mux_fw; + + void do_mux_forward_select(); + + SC_CTOR(mux_forward_select) + { + SC_METHOD(do_mux_forward_select); + sensitive << id_reg << ex_id_forward << m_id_forward << wb_id_forward << id_fw_ctrl; + } +}; Index: tags/arelease/source/cpu/id_stage/forwarding_control.cpp =================================================================== --- tags/arelease/source/cpu/id_stage/forwarding_control.cpp (nonexistent) +++ tags/arelease/source/cpu/id_stage/forwarding_control.cpp (revision 13) @@ -0,0 +1,21 @@ +#include "forwarding_control.h" + +void forwarding_control::do_forwarding_control() +{ + if ((id_ex_writeregister.read() == rs.read()) && (id_ex_regwrite.read() == 1)) + { + id_fw_ctrl.write("01"); + } + else if ((id_ex_m_writeregister.read() == rs.read()) && (id_ex_m_regwrite.read() == 1)) + { + id_fw_ctrl.write("10"); + } + else if ((id_ex_m_wb_writeregister.read() == rs.read()) && (id_ex_m_wb_regwrite.read() == 1)) + { + id_fw_ctrl.write("11"); + } + else + { + id_fw_ctrl.write("00"); + } +} Index: tags/arelease/source/cpu/id_stage/mux_jump.cpp =================================================================== --- tags/arelease/source/cpu/id_stage/mux_jump.cpp (nonexistent) +++ tags/arelease/source/cpu/id_stage/mux_jump.cpp (revision 13) @@ -0,0 +1,16 @@ +#include "mux_jump.h" + +void mux_jump::do_mux_jump() +{ + sc_lv<32> iinp = if_id_next_pc.read(); + sc_lv<32> iii = if_id_inst.read(); + + if(id_select_jump == SC_LOGIC_0) + { + id_jmp_tar.write((iinp.range(31,28),iii.range(25,0),"00")); + } + else + { + id_jmp_tar.write(id_mux_fw1.read()); + } +} Index: tags/arelease/source/cpu/id_stage/sign_extend.cpp =================================================================== --- tags/arelease/source/cpu/id_stage/sign_extend.cpp (nonexistent) +++ tags/arelease/source/cpu/id_stage/sign_extend.cpp (revision 13) @@ -0,0 +1,23 @@ +#include "sign_extend.h" + +void sign_extend::do_sign_extend() +{ + sc_lv<32> inst = if_id_inst.read(); + sc_lv<2> iec = id_extend_ctrl.read(); + + if( iec == "00") + if(inst[15] == SC_LOGIC_1) + id_sign_extend = (HALFWORD_ONE,inst.range(15,0)); + else + id_sign_extend = (HALFWORD_ZERO,inst.range(15,0)); + + else + if( iec == "01") + id_sign_extend = (HALFWORD_ZERO,inst.range(15,0)); + else + if( iec == "10") + id_sign_extend = (inst.range(15,0),HALFWORD_ZERO); + else + id_sign_extend = WORD_ZERO; + +} Index: tags/arelease/source/cpu/id_stage/comparator.cpp =================================================================== --- tags/arelease/source/cpu/id_stage/comparator.cpp (nonexistent) +++ tags/arelease/source/cpu/id_stage/comparator.cpp (revision 13) @@ -0,0 +1,61 @@ +#include "comparator.h" + +void comparator::do_comparator() +{ + sc_logic result; + + sc_lv<32> ss = id_mux_fw1.read(); + sc_lv<32> tt = id_mux_fw2.read(); + + + sc_int<32> sss = ss; + sc_int<32> ttt = tt; + sc_lv<3> ibs = id_branch_select.read(); + result = SC_LOGIC_0; + + if(ibs == "000") + result = SC_LOGIC_0; + else if(ibs == "001") + { + result = SC_LOGIC_0; + PRINT("***** ERROR COMPARATOR ****** "); + } + else if(ibs == "010") // beq + if( sss == ttt ) + result = SC_LOGIC_1; + else + result = SC_LOGIC_0; + else if(ibs == "011") // bne + if( sss != ttt) + result = SC_LOGIC_1; + else + result = SC_LOGIC_0; + else if(ibs == "100") // bltz + if( sss < 0) + result = SC_LOGIC_1; + else + result = SC_LOGIC_0; + else if(ibs == "101") // blez + if( sss <= 0) + result = SC_LOGIC_1; + else + result = SC_LOGIC_0; + else if(ibs == "110") // bgtz + // Vil ikke godtage sss > 0 til verilog + // if( !(sss <= 0) ) + if ( sss > 0 ) + result = SC_LOGIC_1; + else + result = SC_LOGIC_0; + else if(ibs == "111") + if( sss >= 0) + result = SC_LOGIC_1; + else + result = SC_LOGIC_0; + else + result = SC_LOGIC_0; + + id_equal.write(result); + id_branch.write(result); +} + Index: tags/arelease/source/cpu/id_stage/decode_ctrl.cpp =================================================================== --- tags/arelease/source/cpu/id_stage/decode_ctrl.cpp (nonexistent) +++ tags/arelease/source/cpu/id_stage/decode_ctrl.cpp (revision 13) @@ -0,0 +1,13 @@ +#include "decode_ctrl.h" + +void decode_ctrl::do_decode_ctrl() +{ + if((if_id_IBUS.read() == SC_LOGIC_1) || + (if_id_inst_addrl.read() == SC_LOGIC_1) || + (syscall_exception.read() == SC_LOGIC_1) || + (illegal_instruction.read() == SC_LOGIC_1)) + id_exception.write(SC_LOGIC_1); + else + id_exception.write(SC_LOGIC_0); + +}; Index: tags/arelease/source/cpu/id_stage/forwarding_control.h =================================================================== --- tags/arelease/source/cpu/id_stage/forwarding_control.h (nonexistent) +++ tags/arelease/source/cpu/id_stage/forwarding_control.h (revision 13) @@ -0,0 +1,24 @@ +#include "systemc.h" +#include "../../constants/constants.h" + +SC_MODULE(forwarding_control) +{ + sc_in > id_ex_writeregister; + sc_in > id_ex_m_writeregister; + sc_in > id_ex_m_wb_writeregister; + sc_in id_ex_regwrite; + sc_in id_ex_m_regwrite; + sc_in id_ex_m_wb_regwrite; + sc_in > rs; + sc_out > id_fw_ctrl; + + void do_forwarding_control(); + + SC_CTOR(forwarding_control) + { + SC_METHOD(do_forwarding_control); + sensitive << id_ex_writeregister << id_ex_m_writeregister; + sensitive << id_ex_m_wb_writeregister << id_ex_regwrite; + sensitive << id_ex_m_regwrite << id_ex_m_wb_regwrite << rs; + } +}; Index: tags/arelease/source/cpu/id_stage/mux_jump.h =================================================================== --- tags/arelease/source/cpu/id_stage/mux_jump.h (nonexistent) +++ tags/arelease/source/cpu/id_stage/mux_jump.h (revision 13) @@ -0,0 +1,20 @@ +#include "systemc.h" +#include "../../constants/constants.h" +#include "../../constants/config.h" + +SC_MODULE(mux_jump) +{ + sc_in > if_id_next_pc; + sc_in > if_id_inst; + sc_in id_select_jump; + sc_in > id_mux_fw1; + sc_out > id_jmp_tar; + + void do_mux_jump(); + + SC_CTOR(mux_jump) + { + SC_METHOD(do_mux_jump); + sensitive << id_select_jump << if_id_inst << if_id_next_pc << id_mux_fw1; + } +}; Index: tags/arelease/source/cpu/id_stage/sign_extend.h =================================================================== --- tags/arelease/source/cpu/id_stage/sign_extend.h (nonexistent) +++ tags/arelease/source/cpu/id_stage/sign_extend.h (revision 13) @@ -0,0 +1,18 @@ +#include "systemc.h" +#include "../../constants/constants.h" +#include "../../constants/config.h" + +SC_MODULE(sign_extend) +{ + sc_in > if_id_inst; + sc_in > id_extend_ctrl; + sc_out > id_sign_extend; + + void do_sign_extend(); + + SC_CTOR(sign_extend) + { + SC_METHOD(do_sign_extend); + sensitive << if_id_inst << id_extend_ctrl; + } +}; Index: tags/arelease/source/cpu/id_stage/regfile_high.cpp =================================================================== --- tags/arelease/source/cpu/id_stage/regfile_high.cpp (nonexistent) +++ tags/arelease/source/cpu/id_stage/regfile_high.cpp (revision 13) @@ -0,0 +1,44 @@ +//! +/* + No description +*/ +#include "../../constants/config.h" + +// #ifdef _HIGH_LEVEL_SIM_ +#include "regfile_high.h" + +void regfile::storeregister() +{ + sc_lv<5> d = rd; + if(reset.read() == true) + { + for(int i = 0; i<32; i++) + r[i] = WORD_ZERO; + } + else + { + if(wr == SC_LOGIC_1) + r[(sc_uint<5>) d] = rd_in; + } +} + +//! Load register outputs +/*! + Sets the register file output signals according the inputs + */ +void regfile::loadregister() +{ + sc_lv<5> t = rt; + sc_lv<5> s = rs; + + if(s == "00000") + rs_out = WORD_ZERO; + else + rs_out = r[(sc_uint<5>) s]; + + if(t == "00000") + rt_out = WORD_ZERO; + else + rt_out = r[(sc_uint<5>) t]; +} +// #endif Index: tags/arelease/source/cpu/id_stage/comparator.h =================================================================== --- tags/arelease/source/cpu/id_stage/comparator.h (nonexistent) +++ tags/arelease/source/cpu/id_stage/comparator.h (revision 13) @@ -0,0 +1,20 @@ +#include "systemc.h" +#include "../../constants/constants.h" + +SC_MODULE(comparator) +{ + sc_in > id_mux_fw1; + sc_in > id_mux_fw2; + sc_in > id_branch_select; + sc_out id_equal; + sc_out id_branch; + + void do_comparator(); + + SC_CTOR(comparator) + { + SC_METHOD(do_comparator); + sensitive << id_mux_fw1 << id_mux_fw2; + sensitive << id_branch_select; + } +}; Index: tags/arelease/source/cpu/id_stage/decode_ctrl.h =================================================================== --- tags/arelease/source/cpu/id_stage/decode_ctrl.h (nonexistent) +++ tags/arelease/source/cpu/id_stage/decode_ctrl.h (revision 13) @@ -0,0 +1,20 @@ +#include "systemc.h" +#include "../../constants/constants.h" + +SC_MODULE(decode_ctrl) +{ + sc_in if_id_IBUS; + sc_in if_id_inst_addrl; + sc_in illegal_instruction; + sc_in syscall_exception; + sc_out id_exception; + + void do_decode_ctrl(); + + SC_CTOR(decode_ctrl) + { + SC_METHOD(do_decode_ctrl); + sensitive << if_id_IBUS << if_id_inst_addrl; + sensitive << syscall_exception << illegal_instruction; + } +}; Index: tags/arelease/source/cpu/id_stage/control.cpp =================================================================== --- tags/arelease/source/cpu/id_stage/control.cpp (nonexistent) +++ tags/arelease/source/cpu/id_stage/control.cpp (revision 13) @@ -0,0 +1,481 @@ +#include "control.h" + + + +void control::do_control() +{ + + sc_logic n0 = SC_LOGIC_0; + sc_logic n1 = SC_LOGIC_1; + + sc_lv<32> inst = if_id_inst; + sc_lv<6> func = inst.range(5,0); + sc_lv<6> op = inst.range(31,26); + + id_opcode.write(op); + id_function.write(func); + + sc_lv<5> lrs, lrt, lrd, lsa; // lv version of reg # + sc_uint<5> uirs, uirt, uird, uisa; // unsigned integer version of reg # + sc_int<32> is, it, id; // integer version of register contents... + + //! The immediate value in an instruction + sc_lv<16> imm; + sc_lv<32> imm_sign, imm_zero; + sc_int<32> iimm_sign, iimm_zero; + sc_uint<32> uiimm_sign, uiimm_zero; + sc_lv<28> instr_index; + sc_uint<28> uiinstr_index; + + // register destinations and recipients + rs.write(inst.range(25,21)); + rt.write(inst.range(20,16)); + rd.write(inst.range(15,11)); + + uirs = lrs = inst.range(25,21); + uirt = lrt = inst.range(20,16); + uird = lrd = inst.range(15,11); + uisa = lsa = inst.range(10,6); + + // signals for selection bytes and sign of lw/sw instructions + sc_lv<2> byteselect = "00"; + sc_logic id_bssign = SC_LOGIC_0; + +#ifdef _HIGH_LEVEL_SIM_ + is = 0; // localreg->r[uirs]; + it = 0; // localreg->r[uirt]; + id = 0; // localreg->r[uird]; +#endif + + + // Immediate values + imm = inst.range(15,0); + uiimm_zero = iimm_zero = imm_zero = (HALFWORD_ZERO,imm); + if( imm[15] == '1') + uiimm_sign = iimm_sign = imm_sign = (HALFWORD_ONE,imm); + else + uiimm_sign = iimm_sign = imm_sign = (HALFWORD_ZERO,imm); + + uiinstr_index = instr_index = (inst.range(25,0), "00"); + + id_alu_ctrl.write(func); + id_alu_sa.write(inst.range(10,6)); + id_ctrl.write(n0); + id_extend_ctrl.write("00"); + id_sign_ctrl.write("00"); + regdest.write("00"); + id_select_jump.write(n0); + id_pc_store.write(n0); + id_branch_select.write("000"); + id_regwrite.write(n0); + id_shamt_ctrl.write(n0); + id_datarw.write(n0); + id_datareq.write(n0); + id_memtoreg.write(n0); + + // Signals to cp0 + cp0_inst.write(CP0_NOTHING); // 4 bit... + // cp0_reg_rs will be set directly from forward-MUX + cp0_reg_no.write(uird); + cp0_reg_rw.write(SC_LOGIC_0); // default value...don't write! + id_mfc0.write(SC_LOGIC_0); + sc_logic cpo_co = inst[25]; + + illegal_instruction.write(SC_LOGIC_0); + syscall_exception.write(SC_LOGIC_0); + +#ifdef ONEHOT_DEBUG + inst_addiu.write(SC_LOGIC_0); + inst_jalr.write(SC_LOGIC_0); + inst_lw.write(SC_LOGIC_0); + inst_mfc0.write(SC_LOGIC_0); + inst_mtc0.write(SC_LOGIC_0); + inst_nop.write(SC_LOGIC_0); + inst_sw.write(SC_LOGIC_0); + inst_wait.write(SC_LOGIC_0); +#endif + + //switch stage + if(op == OP_RFORMAT) + { + if(func == FUNC_JR) + { + id_ctrl.write(n1); + id_select_jump.write(n1); + id_alu_ctrl.write("000000"); + } + else if(func == FUNC_JALR) + { +#ifdef ONEHOT_DEBUG + inst_jalr.write(SC_LOGIC_1); +#endif + id_ctrl.write(n1); + id_select_jump.write(n1); + id_pc_store.write(n1); + id_regwrite.write(n1); + id_alu_ctrl.write(FUNC_ADDU); + id_sign_ctrl.write("10"); + } + + else + if(func == FUNC_MULT) + { + id_alu_ctrl.write(FUNC_MULT); + id_regwrite.write(n0); + } + else if(func == FUNC_MFLO) + { + id_alu_ctrl.write(FUNC_MFLO); + id_regwrite.write(n1); + } + + else if(func == FUNC_MTHI) + { + id_alu_ctrl.write(FUNC_MTHI); + id_regwrite.write(n1); + } + + else if(func == FUNC_MULTU) + { + id_alu_ctrl.write(FUNC_MULTU); + id_regwrite.write(n0); + } + + + else if(func == FUNC_DIV) + { + id_alu_ctrl.write(FUNC_DIV); + } + + else if(func == FUNC_DIVU) + { + id_alu_ctrl.write(FUNC_DIVU); + } + + else if(func == FUNC_SLL || + func == FUNC_SRL || + func == FUNC_SRA) + { + id_shamt_ctrl.write(n1); + id_regwrite.write(n1); +#ifdef ONEHOT_DEBUG + inst_nop.write(SC_LOGIC_1); +#endif + } + else if(func == FUNC_SLLV || + func == FUNC_SRLV || + func == FUNC_SRAV || + func == FUNC_MFHI || + func == FUNC_MFLO || + func == FUNC_ADD || + func == FUNC_ADDU || + func == FUNC_SUB || + func == FUNC_SUBU || + func == FUNC_AND || + func == FUNC_OR || + func == FUNC_XOR || + func == FUNC_NOR || + func == FUNC_SLT || + func == FUNC_SLTU) + { + id_regwrite.write(n1); + } +#ifdef _INCLUDE_CP0_ + else if (func == FUNC_BREAK) + { + cp0_inst.write(CP0_BREAK); + } + else if (func == FUNC_SYSCALL) + { + cp0_inst.write(CP0_SYSCALL); + syscall_exception.write(SC_LOGIC_1); + } +#else + else if (func == FUNC_BREAK || func == FUNC_SYSCALL) + { + + //sc_stop(); + } +#endif + else + { + illegal_instruction.write(SC_LOGIC_1); + cout << " illegal instruction " << endl; + //sc_stop(); + } + } + else if(op == OP_BRANCH) + { + // PRINTLN("Branch format"); + if(lrt.range(1,0) == BRANCH_BLTZ) + { + id_branch_select.write("100"); + } + else if(lrt.range(1,0) == BRANCH_BGEZ) + { + id_branch_select.write("111"); + } + else if(lrt.range(1,0) == BRANCH_BLTZAL) + { + id_branch_select.write("100"); + id_pc_store.write(n1); + id_sign_ctrl.write("10"); + regdest.write("10"); + id_regwrite.write(n1); + id_alu_ctrl.write(FUNC_ADDU); + } + else if(lrt.range(1,0) == BRANCH_BGEZAL) + { + id_branch_select.write("111"); + id_pc_store.write(n1); + id_sign_ctrl.write("10"); + regdest.write("10"); + id_regwrite.write(n1); + id_alu_ctrl.write(FUNC_ADDU); + } + else illegal_instruction.write(SC_LOGIC_1); + } + else if(op == OP_J) + { + id_ctrl.write(n1); + } + else if(op == OP_JAL) + { + id_ctrl.write(n1); + id_pc_store.write(n1); + // add 8 in total + id_alu_ctrl.write(FUNC_ADDU); + id_sign_ctrl.write("10"); + regdest.write("10"); + id_regwrite.write(n1); + } + else if(op == OP_BEQ) + { + id_branch_select.write("010"); + } + else if(op == OP_BNE) + { + id_branch_select.write("011"); + } + else if(op == OP_BLEZ) + { + id_branch_select.write("101"); + } + else if(op == OP_BGTZ) + { + id_branch_select.write("110"); + } + else if(op == OP_ADDI) + { + id_alu_ctrl.write(FUNC_ADD); + regdest.write("01"); + id_sign_ctrl.write("01"); + id_regwrite.write(n1); + } + else if(op == OP_ADDIU) + { + id_alu_ctrl.write(FUNC_ADDU); + regdest.write("01"); + id_sign_ctrl.write("01"); + id_regwrite.write(n1); +#ifdef ONEHOT_DEBUG + inst_addiu.write(SC_LOGIC_1); +#endif + } + else if(op == OP_SLTI) + { + id_alu_ctrl.write(FUNC_SLT); + regdest.write("01"); + id_sign_ctrl.write("01"); + id_regwrite.write(n1); + } + else if(op == OP_SLTIU) + { + id_alu_ctrl.write(FUNC_SLTU); + regdest.write("01"); + id_sign_ctrl.write("01"); + id_regwrite.write(n1); + } + else if(op == OP_ANDI) + { + id_alu_ctrl.write(FUNC_AND); + regdest.write("01"); + id_sign_ctrl.write("01"); + id_extend_ctrl.write("01"); + id_regwrite.write(n1); + } + else if(op == OP_ORI) + { + id_alu_ctrl.write(FUNC_OR); + regdest.write("01"); + id_sign_ctrl.write("01"); + id_extend_ctrl.write("01"); + id_regwrite.write(n1); + } + else if(op == OP_XORI) + { + id_alu_ctrl.write(FUNC_XOR); + regdest.write("01"); + id_sign_ctrl.write("01"); + id_extend_ctrl.write("01"); + id_regwrite.write(n1); + } + else if(op == OP_LUI) + { + id_alu_ctrl.write(FUNC_ADDU); + regdest.write("01"); + id_sign_ctrl.write("01"); + id_extend_ctrl.write("10"); + id_regwrite.write(n1); + } + else if(op == OP_LB || + op == OP_LH || + op == OP_LWL || + op == OP_LW || + op == OP_LBU || + op == OP_LHU || + op == OP_LWR) + { + id_alu_ctrl.write(FUNC_ADDU); + id_regwrite.write(n1); + regdest.write("01"); + id_datareq.write(n1); + id_memtoreg.write(n1); + id_sign_ctrl.write("01"); + // Select bytes to be read! + if (op == OP_LB || op == OP_LBU) + byteselect = "01"; + else if (op == OP_LH || op == OP_LHU) + byteselect = "10"; + else + byteselect = "00"; + // select to sign_extend or not + if ((op == OP_LBU) || (op == OP_LHU)) + id_bssign = SC_LOGIC_1; +#ifdef ONEHOT_DEBUG + inst_lw = SC_LOGIC_1; +#endif + } + else if(op == OP_SB || + op == OP_SH || + op == OP_SWL || + op == OP_SW || + op == OP_SWR) + { + id_alu_ctrl.write(FUNC_ADDU); + id_datarw.write(n1); + id_datareq.write(n1); + id_memtoreg.write(n1); + id_sign_ctrl.write("01"); + // Select bytes to be written + if (op == OP_SB) + byteselect = "01"; + else if (op == OP_SH) + byteselect = "10"; + else + byteselect = "00"; +#ifdef ONEHOT_DEBUG + inst_sw = SC_LOGIC_1; +#endif + } +#ifdef _INCLUDE_CP0_ + else if(op == OP_CACHE) + { + cp0_inst.write(CP0_CACHE); + } +#endif + /*! + In order to include co-processor you need to enable it in the config file. + */ + else + if(op == OP_COPROC0) + { + if(cpo_co == SC_LOGIC_1) + { + if(func == FUNC_TLBR) + { + cp0_inst.write(CP0_TLBR); + } + else + if(func == FUNC_TLBWI) + { + cp0_inst.write(CP0_TLBWI); + } + else + if(func == FUNC_TLBWR) + { + cp0_inst.write(CP0_TLBWR); + } + else + if(func == FUNC_TLBP) + { + cp0_inst.write(CP0_TLBP); + } + else + if(func == FUNC_ERET) + { + cp0_inst.write(CP0_ERET); + + } + else + if(func == FUNC_DERET) + { + cp0_inst.write(CP0_DERET); + } + else + if(func == FUNC_WAIT) + { + cp0_inst.write(CP0_WAIT); + // Do same actions as jalr...except jump! + id_ctrl.write(n0); + id_select_jump.write(n0); + id_pc_store.write(n1); + id_regwrite.write(n1); + id_alu_ctrl.write(FUNC_ADDU); + id_sign_ctrl.write("10"); + #ifdef ONEHOT_DEBUG + inst_wait.write(SC_LOGIC_1); + #endif + } + } + else + { + if(lrs == RS_MFC0) + { + cp0_inst.write(CP0_MFC0); + cp0_reg_rw.write(SC_LOGIC_0); + id_mfc0.write(SC_LOGIC_1); + + id_alu_ctrl.write(FUNC_ADDU); + regdest.write("01"); + id_sign_ctrl.write("00"); + id_regwrite.write(n1); +#ifdef ONEHOT_DEBUG + inst_mfc0.write(SC_LOGIC_1); +#endif + } + else + if(lrs == RS_MTC0) + { + cp0_inst.write(CP0_MTC0); + cp0_reg_rw.write(SC_LOGIC_1); + id_alu_ctrl.write(FUNC_ADDU); + cp0_reg_no.write(uird); + id_mfc0.write(SC_LOGIC_0); +#ifdef ONEHOT_DEBUG + inst_mtc0.write(SC_LOGIC_1); +#endif + } + } + //cout << "illegal instruction " << endl; + //illegal_instruction.write(SC_LOGIC_1); + } + + else + { + illegal_instruction.write(SC_LOGIC_1); + cout << " illegal instruction " << endl; + //sc_stop(); + } + id_byteselect = byteselect; +} Index: tags/arelease/source/cpu/id_stage/regfile_high.h =================================================================== --- tags/arelease/source/cpu/id_stage/regfile_high.h (nonexistent) +++ tags/arelease/source/cpu/id_stage/regfile_high.h (revision 13) @@ -0,0 +1,44 @@ +// +// $Id: regfile_high.h,v 1.1.1.1 2006-01-31 10:55:29 igorloi Exp $ +// + +#ifndef _REGFILE_H +#define _REGFILE_H + +#include +#include "../../constants/config.h" +#include "../../constants/constants.h" + +SC_MODULE(regfile) +{ + // default input + sc_in in_clk; + sc_in reset; + sc_in > rs; + sc_in > rt; + sc_in wr; + sc_in > rd_in; + sc_in > rd; + sc_out > rs_out; + sc_out > rt_out; + + sc_signal > r[32]; + + void storeregister(); + void loadregister(); + + SC_CTOR(regfile) + { + SC_METHOD(storeregister); + sensitive_neg << in_clk; + + SC_METHOD(loadregister); + sensitive << rs << rt << in_clk; + } +}; + +#endif + + + + Index: tags/arelease/source/cpu/id_stage/add_new_pc.cpp =================================================================== --- tags/arelease/source/cpu/id_stage/add_new_pc.cpp (nonexistent) +++ tags/arelease/source/cpu/id_stage/add_new_pc.cpp (revision 13) @@ -0,0 +1,6 @@ +#include "add_new_pc.h" + +void add_new_pc::do_add_new_pc() +{ + id_new_pc.write(((sc_int<32>) (if_id_next_pc.read())) + (((sc_int<32>) (id_sign_extend.read()) << 2))); +} Index: tags/arelease/source/cpu/id_stage/control.h =================================================================== --- tags/arelease/source/cpu/id_stage/control.h (nonexistent) +++ tags/arelease/source/cpu/id_stage/control.h (revision 13) @@ -0,0 +1,58 @@ +#include "systemc.h" +#include "../../constants/constants.h" +#include "../../constants/config.h" + +SC_MODULE(control) +{ + sc_in > if_id_inst; + sc_out > rs; + sc_out > rt; + sc_out > rd; + sc_out > id_alu_ctrl; + + //*************************************************// + //******** segnali per il moltiplicatore **********// + sc_out > id_opcode; + sc_out > id_function; + //*************************************************// + //*************************************************// + + sc_out > id_alu_sa; + sc_out id_ctrl; + sc_out > id_extend_ctrl; + sc_out > id_sign_ctrl; + sc_out > regdest; + sc_out id_select_jump; + sc_out id_pc_store; + sc_out > id_branch_select; + sc_out id_regwrite; + sc_out id_shamt_ctrl; + sc_out id_datarw; + sc_out id_datareq; + sc_out id_memtoreg; + sc_out > id_byteselect; + + sc_out > cp0_inst; + sc_out > cp0_reg_no; + sc_out cp0_reg_rw; + sc_out id_mfc0; + sc_out illegal_instruction; + sc_out syscall_exception; +#ifdef ONEHOT_DEBUG + sc_out inst_addiu; + sc_out inst_jalr; + sc_out inst_lw; + sc_out inst_mfc0; + sc_out inst_mtc0; + sc_out inst_nop; + sc_out inst_sw; + sc_out inst_wait; +#endif + void do_control(); + + SC_CTOR(control) + { + SC_METHOD(do_control); + sensitive << if_id_inst; + } +}; Index: tags/arelease/source/cpu/id_stage/add_new_pc.h =================================================================== --- tags/arelease/source/cpu/id_stage/add_new_pc.h (nonexistent) +++ tags/arelease/source/cpu/id_stage/add_new_pc.h (revision 13) @@ -0,0 +1,18 @@ +#include "systemc.h" +#include "../../constants/constants.h" + +SC_MODULE(add_new_pc) +{ + sc_in > if_id_next_pc; + sc_in > id_sign_extend; + sc_out > id_new_pc; + + void do_add_new_pc(); + + SC_CTOR(add_new_pc) + { + SC_METHOD(do_add_new_pc); + sensitive << if_id_next_pc << id_sign_extend; + } + +}; Index: tags/arelease/source/cpu/id_stage/mux_writeregister.cpp =================================================================== --- tags/arelease/source/cpu/id_stage/mux_writeregister.cpp (nonexistent) +++ tags/arelease/source/cpu/id_stage/mux_writeregister.cpp (revision 13) @@ -0,0 +1,19 @@ +//Multiplexer per scittura registri +// Stabilisce il registro di destinazione, che puo' essere +// il registro rt, rd o il registro 31! + +#include "mux_writeregister.h" + +void mux_writeregister::do_mux_writeregister() +{ + if(regdest.read() == "00") + id_writeregister.write(rd); + else + if(regdest.read() == "01") + id_writeregister.write(rt); + else + if(regdest.read() == "10") + id_writeregister.write("11111"); + else + id_writeregister.write("00000"); +} Index: tags/arelease/source/cpu/id_stage/reg_id.cpp =================================================================== --- tags/arelease/source/cpu/id_stage/reg_id.cpp (nonexistent) +++ tags/arelease/source/cpu/id_stage/reg_id.cpp (revision 13) @@ -0,0 +1,106 @@ +#include "reg_id.h" + +void reg_id::do_reg_id() +{ + if(reset.read() == true) + { + id_ex_alu1.write(WORD_ZERO); + id_ex_alu2.write(WORD_ZERO); + id_ex_datastore.write(WORD_ZERO); + id_ex_alu_ctrl.write("000000"); + id_ex_alu_sa.write("00000"); + id_ex_equal.write(SC_LOGIC_0); + id_ex_datareq.write(SC_LOGIC_0); + id_ex_datarw.write(SC_LOGIC_0); + id_ex_memtoreg.write(SC_LOGIC_0); + id_ex_writeregister_out.write("00000"); + id_ex_regwrite_out.write(SC_LOGIC_0); + id_ex_writeregister.write("00000"); + id_ex_regwrite.write(SC_LOGIC_0); + id_ex_byteselect.write("00"); + id_ex_bssign.write(SC_LOGIC_0); + id_ex_inst.write(WORD_ZERO); + + // EXCEPTION SIGNALS + id_ex_IBUS.write(SC_LOGIC_0); + id_ex_inst_addrl.write(SC_LOGIC_0); + id_ex_syscall_exception.write(SC_LOGIC_0); + id_ex_illegal_instruction.write(SC_LOGIC_0); + id_ex_instaddr.write(0); + id_ex_alu_opcode.write("000000"); + id_ex_alu_function.write("000000"); + } + else + if((datahold.read() == false) && (insthold.read() == false) && (enable_decode.read() == SC_LOGIC_1)) + { + id_ex_alu1.write(id_alu1.read()); + id_ex_alu2.write(id_alu2.read()); + id_ex_datastore.write(id_mux_fw2.read()); + id_ex_alu_ctrl.write(id_alu_ctrl.read()); + id_ex_alu_sa.write(id_alu_sa.read()); + id_ex_equal.write(id_equal.read()); + id_ex_datareq.write(id_datareq.read()); + id_ex_datarw.write(id_datarw.read()); + id_ex_memtoreg.write(id_memtoreg.read()); + id_ex_writeregister_out.write(id_writeregister.read()); + id_ex_writeregister.write(id_writeregister.read()); + id_ex_regwrite_out.write(id_regwrite.read()); + id_ex_regwrite.write(id_regwrite.read()); + id_ex_byteselect.write(id_byteselect.read()); + id_ex_bssign.write(id_bssign.read()); + id_ex_inst.write(if_id_inst.read()); + // EXCEPTION SIGNALS + id_ex_IBUS.write(if_id_IBUS.read()); + id_ex_inst_addrl.write(if_id_inst_addrl.read()); + id_ex_syscall_exception.write(syscall_exception.read()); + id_ex_illegal_instruction.write(illegal_instruction.read()); + id_ex_instaddr.write(if_id_instaddr); + + id_ex_alu_opcode.write(id_opcode.read()); + id_ex_alu_function.write(id_function.read()); + } + else + if((datahold.read() == false) && (insthold.read() == false) && (enable_decode.read() == SC_LOGIC_0)) + { + id_ex_alu1.write(WORD_ZERO); + id_ex_alu2.write(WORD_ZERO); + id_ex_datastore.write(WORD_ZERO); + id_ex_alu_ctrl.write("000000"); + id_ex_alu_sa.write("00000"); + id_ex_equal.write(SC_LOGIC_0); + id_ex_datareq.write(SC_LOGIC_0); + id_ex_datarw.write(SC_LOGIC_0); + id_ex_memtoreg.write(SC_LOGIC_0); + id_ex_writeregister_out.write("00000"); + id_ex_regwrite_out.write(SC_LOGIC_0); + id_ex_writeregister.write("00000"); + id_ex_regwrite.write(SC_LOGIC_0); + id_ex_byteselect.write("00"); + id_ex_bssign.write(SC_LOGIC_0); + + id_ex_alu_opcode.write("000000"); + id_ex_alu_function.write("000000"); + id_ex_IBUS.write(if_id_IBUS.read()); + id_ex_inst_addrl.write(if_id_inst_addrl.read()); + id_ex_inst.write(if_id_inst.read()); + id_ex_syscall_exception.write(syscall_exception.read()); + id_ex_illegal_instruction.write(illegal_instruction.read()); + id_ex_instaddr.write(if_id_instaddr); + } + else; + + + + +} + + + + + + + + + + + Index: tags/arelease/source/cpu/id_stage/mux_alu1.cpp =================================================================== --- tags/arelease/source/cpu/id_stage/mux_alu1.cpp (nonexistent) +++ tags/arelease/source/cpu/id_stage/mux_alu1.cpp (revision 13) @@ -0,0 +1,28 @@ +#include "mux_alu1.h" + +void mux_alu1::do_mux_alu1() +{ + sc_logic isc = id_shamt_ctrl; + sc_logic ips = id_pc_store; + + sc_lv<2> select; + select[1] = isc; + select[0] = ips; + sc_lv<32> iii = if_id_inst; + sc_lv<32> v_id_alu1; + + + if (id_mfc0.read() == SC_LOGIC_1) + v_id_alu1 = cp0_reg_out; + else + if(select == "00") + v_id_alu1 = id_mux_fw1; + else + if(select == "01") + v_id_alu1 = if_id_next_pc; + else + v_id_alu1 = ("00000000000000000000000000",iii.range(11,6)); + + + id_alu1 = v_id_alu1; +} Index: tags/arelease/source/cpu/id_stage/mux_forward_select.cpp =================================================================== --- tags/arelease/source/cpu/id_stage/mux_forward_select.cpp (nonexistent) +++ tags/arelease/source/cpu/id_stage/mux_forward_select.cpp (revision 13) @@ -0,0 +1,17 @@ +#include "mux_forward_select.h" + +void mux_forward_select::do_mux_forward_select() +{ + sc_lv<2> ifc = id_fw_ctrl.read(); + + if( ifc == "00") + id_mux_fw.write(id_reg.read()); + else + if( ifc == "01") + id_mux_fw.write(ex_id_forward.read()); + else + if( ifc == "10") + id_mux_fw.write(m_id_forward.read()); + else + id_mux_fw.write(wb_id_forward.read()); +} Index: tags/arelease/source/cpu/id_stage/mux_alu2.cpp =================================================================== --- tags/arelease/source/cpu/id_stage/mux_alu2.cpp (nonexistent) +++ tags/arelease/source/cpu/id_stage/mux_alu2.cpp (revision 13) @@ -0,0 +1,18 @@ +#include "mux_alu2.h" + +void mux_alu2::do_mux_alu2() +{ + sc_lv<2> isc = id_sign_ctrl; + sc_lv<32> v_id_alu2; + if(isc == "00") + v_id_alu2 = id_mux_fw2; + else + if(isc == "01") + v_id_alu2 = id_sign_extend; + else + v_id_alu2 = (sc_int<32>) 4; + + id_alu2 = v_id_alu2; + cp0_reg_rs = v_id_alu2; + +} Index: tags/arelease/source/cpu/id_stage/mux_writeregister.h =================================================================== --- tags/arelease/source/cpu/id_stage/mux_writeregister.h (nonexistent) +++ tags/arelease/source/cpu/id_stage/mux_writeregister.h (revision 13) @@ -0,0 +1,18 @@ +#include "systemc.h" +#include "../../constants/constants.h" + +SC_MODULE(mux_writeregister) +{ + sc_in > regdest; + sc_in > rt; + sc_in > rd; + sc_out > id_writeregister; + + void do_mux_writeregister(); + + SC_CTOR(mux_writeregister) + { + SC_METHOD(do_mux_writeregister); + sensitive << rt << rd << regdest; + } +}; Index: tags/arelease/source/cpu/writeback_ctrl.cpp =================================================================== --- tags/arelease/source/cpu/writeback_ctrl.cpp (nonexistent) +++ tags/arelease/source/cpu/writeback_ctrl.cpp (revision 13) @@ -0,0 +1,25 @@ +#include "writeback_ctrl.h" + +void writeback_ctrl::do_writeback_ctrl() +{ + if((m_wb_IBUS.read() == SC_LOGIC_1) || + (m_wb_inst_addrl.read() == SC_LOGIC_1) || + (m_wb_syscall_exception.read() == SC_LOGIC_1) || + (m_wb_illegal_instruction.read() == SC_LOGIC_1) || + (m_wb_ovf_excep.read() == SC_LOGIC_1) || + (m_wb_DBUS.read() == SC_LOGIC_1) || + (m_wb_data_addrl.read() == SC_LOGIC_1) || + (m_wb_data_addrs.read() == SC_LOGIC_1) || + (m_wb_interrupt_signal.read() == SC_LOGIC_1)) + wb_exception.write(SC_LOGIC_1); + else + wb_exception.write(SC_LOGIC_0); + + + + + + + + +} Index: tags/arelease/source/cpu/ex_stage.cpp =================================================================== --- tags/arelease/source/cpu/ex_stage.cpp (nonexistent) +++ tags/arelease/source/cpu/ex_stage.cpp (revision 13) @@ -0,0 +1,6 @@ +//! EX Stage module +// +// $Id: ex_stage.cpp,v 1.00 2004/12/23 22:253:00 DIEE Cagliari +// +#include "ex_stage.h" + \ No newline at end of file Index: tags/arelease/source/cpu/if_stage/select_next_pc.cpp =================================================================== --- tags/arelease/source/cpu/if_stage/select_next_pc.cpp (nonexistent) +++ tags/arelease/source/cpu/if_stage/select_next_pc.cpp (revision 13) @@ -0,0 +1,29 @@ +#include "select_next_pc.h" + +void select_next_pc::do_select_next_pc() +{ + #ifdef _DOBRANCH_ + + //sc_lv<32> temp = new_pc; + + if (load_epc.read() == SC_LOGIC_1) + { + pc_in.write(new_pc.read()); + } + else + { + if ((id_ctrl.read() == 0) && (id_branch.read() == 0)) + pc_in.write(if_pc_add.read()); + else + if ((id_ctrl.read() == 0) && (id_branch.read() == 1)) + pc_in.write(id_new_pc.read()); + else + if ((id_ctrl.read() == 1) && (id_branch.read() == 0)) + pc_in.write(id_jmp_tar.read()); + else // 1 && 1 - should never happen! + pc_in.write(id_jmp_tar.read()); + } + #else + pc_in.write(if_pc_add.read()); + #endif +} Index: tags/arelease/source/cpu/if_stage/reg_if.h =================================================================== --- tags/arelease/source/cpu/if_stage/reg_if.h (nonexistent) +++ tags/arelease/source/cpu/if_stage/reg_if.h (revision 13) @@ -0,0 +1,33 @@ +#include "systemc.h" +#include "../../constants/constants.h" + +SC_MODULE(reg_if) +{ + sc_in in_clk; + sc_in reset; + sc_in insthold; + sc_in datahold; + + sc_in > instdataread; + sc_in > if_pc_add; + + sc_out > if_id_inst; + sc_out > if_id_next_pc; + + sc_in IBUS; + sc_in inst_addrl; + sc_out if_id_IBUS; + sc_out if_id_inst_addrl; + + sc_in > pc_if_instaddr; + sc_out > if_id_instaddr; + sc_in enable_fetch; + + void do_reg_if(); + + SC_CTOR(reg_if) + { + SC_METHOD(do_reg_if); + sensitive_pos << in_clk; + } +}; Index: tags/arelease/source/cpu/if_stage/if_ctrl.cpp =================================================================== --- tags/arelease/source/cpu/if_stage/if_ctrl.cpp (nonexistent) +++ tags/arelease/source/cpu/if_stage/if_ctrl.cpp (revision 13) @@ -0,0 +1,10 @@ +#include "if_ctrl.h" + +void if_ctrl::do_if_ctrl() +{ + if((IBUS.read() == SC_LOGIC_1) || (inst_addrl.read() == SC_LOGIC_1)) + if_exception.write(SC_LOGIC_1); + else + if_exception.write(SC_LOGIC_0); + +} Index: tags/arelease/source/cpu/if_stage/select_next_pc.h =================================================================== --- tags/arelease/source/cpu/if_stage/select_next_pc.h (nonexistent) +++ tags/arelease/source/cpu/if_stage/select_next_pc.h (revision 13) @@ -0,0 +1,27 @@ +#include "systemc.h" +#define _DOBRANCH_ 1 +#include "../../constants/constants.h" +#include "../../constants/config.h" + +SC_MODULE(select_next_pc) +{ + sc_in > new_pc; + sc_in load_epc; + sc_in id_ctrl; + sc_in id_branch; + sc_in > if_pc_add; + sc_in > id_new_pc; + sc_in > id_jmp_tar; + + sc_out > pc_in; + + + void do_select_next_pc(); + + SC_CTOR(select_next_pc) + { + SC_METHOD(do_select_next_pc); + sensitive << if_pc_add << id_jmp_tar << id_new_pc << id_branch << id_ctrl << new_pc << load_epc; + + } +}; Index: tags/arelease/source/cpu/if_stage/if_ctrl.h =================================================================== --- tags/arelease/source/cpu/if_stage/if_ctrl.h (nonexistent) +++ tags/arelease/source/cpu/if_stage/if_ctrl.h (revision 13) @@ -0,0 +1,17 @@ +#include "systemc.h" +#include "../../constants/constants.h" + +SC_MODULE(if_ctrl) +{ + sc_in IBUS; + sc_in inst_addrl; + sc_out if_exception; + + void do_if_ctrl(); + + SC_CTOR(if_ctrl) + { + SC_METHOD(do_if_ctrl); + sensitive << IBUS << inst_addrl; + } +}; Index: tags/arelease/source/cpu/if_stage/add.cpp =================================================================== --- tags/arelease/source/cpu/if_stage/add.cpp (nonexistent) +++ tags/arelease/source/cpu/if_stage/add.cpp (revision 13) @@ -0,0 +1,6 @@ +#include "add.h" + +void add::do_add() +{ + if_pc_add.write(((sc_uint<32>) pc_out.read()) + 4); +} Index: tags/arelease/source/cpu/if_stage/reg_if.cpp =================================================================== --- tags/arelease/source/cpu/if_stage/reg_if.cpp (nonexistent) +++ tags/arelease/source/cpu/if_stage/reg_if.cpp (revision 13) @@ -0,0 +1,42 @@ +#include "reg_if.h" +/* +enable_fetch: segnale posto ad 1 per il normale funzionamento della pipeline. +Se si verifica un eccezione il coprocessore setta questo segnale a zero inibendo +la scrittura sui registri di pipeline di questo stadio. +Segnale per la gestione delle eccezioni IBUS e inst_addrl +*/ + + +void reg_if::do_reg_if() +{ + if(reset.read() == true) + { + if_id_next_pc.write(0); + if_id_inst.write(0); + if_id_IBUS.write(SC_LOGIC_0); + if_id_inst_addrl.write(SC_LOGIC_0); + if_id_instaddr.write(0); + } + else + { + if((insthold.read() == false) && (datahold.read() == false) && (enable_fetch.read() == SC_LOGIC_1)) + { + if_id_next_pc.write(if_pc_add.read()); + if_id_inst.write(instdataread.read()); + if_id_IBUS.write(IBUS.read()); + if_id_inst_addrl.write(inst_addrl.read()); + if_id_instaddr.write(pc_if_instaddr.read()); + } + else + if((insthold.read() == false) && (datahold.read() == false) && (enable_fetch.read() == SC_LOGIC_0)) + { + // QUESTA PaRTE �DA RIVEDERE!!!! + if_id_next_pc.write(0); + if_id_inst.write(0); + if_id_IBUS.write(IBUS.read()); + if_id_inst_addrl.write(inst_addrl.read()); + if_id_instaddr.write(pc_if_instaddr.read()); + } + else; + } +} Index: tags/arelease/source/cpu/if_stage/add.h =================================================================== --- tags/arelease/source/cpu/if_stage/add.h (nonexistent) +++ tags/arelease/source/cpu/if_stage/add.h (revision 13) @@ -0,0 +1,15 @@ +#include "systemc.h" + +SC_MODULE(add) +{ + sc_out > if_pc_add; + sc_in > pc_out; + + void do_add(); + + SC_CTOR(add) + { + SC_METHOD(do_add); + sensitive << pc_out; + } +}; Index: tags/arelease/source/cpu/mux_instaddr.cpp =================================================================== --- tags/arelease/source/cpu/mux_instaddr.cpp (nonexistent) +++ tags/arelease/source/cpu/mux_instaddr.cpp (revision 13) @@ -0,0 +1,45 @@ +#include "mux_instaddr.h" + +void mux_instaddr::do_mux_instaddr() +{ + if(m_wb_interrupt_signal.read() == true) + { + sc_lv<16> temp_1; + sc_lv<5> temp_2; + sc_lv<6> temp_3; + + temp_1 = (ex_mem_inst.read()).range(31,16); // upper 16 bit + temp_2 = (ex_mem_inst.read()).range(10,6); // + temp_3 = (ex_mem_inst.read()).range(5,0); //opcode + + cout << " interrupt" << endl; + cout << " temp1 = " << temp_1 << endl; + cout << " temp2 = " << temp_2 << endl; + cout << " temp3 = " << temp_3 << endl; + cout << " inst = " << ex_mem_inst.read() << endl; + + //|| + + + if(((ex_m_instaddr.read() - m_wb_instaddr.read()) == 4)) + { + if(((temp_1 == HALFWORD_ZERO) && (temp_2 == "00000") && ((temp_3 == "010010") || (temp_3 == "010000") ))) + { + m_wb_instaddr_s.write(m_wb_instaddr.read() - 4 ); + cout << " Istruz MFLO o MFHI durante l'interrupt" << endl; + } + else + { + m_wb_instaddr_s.write(m_wb_instaddr.read()); + cout << " Indirizzi consecutivi delle ultime 2 istruz durante l'interrupt" << endl; + } + } + else + { + m_wb_instaddr_s.write(ex_m_instaddr.read()); + cout << " indirizzi delle ultime due istruz non consecutivi durante l'interrupt" << endl; + } + } + else + m_wb_instaddr_s.write(m_wb_instaddr.read()); +} Index: tags/arelease/source/cpu/cp0/exception.cpp =================================================================== --- tags/arelease/source/cpu/cp0/exception.cpp (nonexistent) +++ tags/arelease/source/cpu/cp0/exception.cpp (revision 13) @@ -0,0 +1,101 @@ +#include "exception.h" + +void exception::compute_cause() +{ + sc_lv<5> cause_5; + sc_lv<32> cause_32; + + if(m_wb_inst_addrl.read() == SC_LOGIC_1) + cause_5 = "00100" ; + else + if(m_wb_IBUS.read() == SC_LOGIC_1) + cause_5 = "00110" ; + else + if(m_wb_DBUS.read() == SC_LOGIC_1) + cause_5 = "00111" ; + else + if(m_wb_data_addrl.read() == SC_LOGIC_1) + cause_5 = "00100" ; + else + if(m_wb_data_addrs.read() == SC_LOGIC_1) + cause_5 = "00101" ; + else + if(m_wb_syscall_exception.read() == SC_LOGIC_1) + cause_5 = "01000" ; + else + if(m_wb_illegal_instruction.read() == SC_LOGIC_1) // RI + cause_5 = "01010"; + else + if(m_wb_ovf_excep.read() == SC_LOGIC_1) + cause_5 = "01100"; + else + if(m_wb_interrupt_signal.read() == SC_LOGIC_1) + cause_5 = "00000"; + else + cause_5 = "00000"; + + cause_32 = WORD_ZERO; + cause_32.range(6,2) = cause_5; + cause.write(cause_32); +} + +void exception::check_for_exception() +{ + if((m_wb_IBUS.read() == SC_LOGIC_1) || + (m_wb_inst_addrl.read() == SC_LOGIC_1) || + (m_wb_syscall_exception.read() == SC_LOGIC_1) || + (m_wb_illegal_instruction.read() == SC_LOGIC_1) || + (m_wb_ovf_excep.read() == SC_LOGIC_1) || + (m_wb_DBUS.read() == SC_LOGIC_1) || + (m_wb_data_addrl.read() == SC_LOGIC_1) || + (m_wb_data_addrs.read() == SC_LOGIC_1) || + (m_wb_interrupt_signal.read() == SC_LOGIC_1)) + check_excep.write(true); + else + check_excep.write(false); +} + +void exception::check_for_interrupt() +{ + /*if(interrupt_signal.read() == SC_LOGIC_1) + interrupt_exception.write(SC_LOGIC_1); + else + interrupt_exception.write(SC_LOGIC_0);*/ +} + +void exception::check_for_Page_fault() +{ + if((cause.read()).range(6,2) == "00110" ) + to_BadVAddr.write(m_wb_instaddr.read()); + else + if((cause.read()).range(6,2) == "00111" ) + to_BadVAddr.write(m_wb_dataaddr.read()); + else + to_BadVAddr.write(0); +} + +void exception::save_EPC() +{ + if(check_excep.read() == SC_LOGIC_1) + to_EPC.write(m_wb_instaddr.read()); + else + to_EPC.write(0); +} + +//sensitive << m_wb_interrupt_signal; +//sensitive << cp0_inst << reset; +void exception::handling_status_register() +{ + if(reset.read() == true ) + to_SR = SC_LOGIC_0; + else + { + if(m_wb_interrupt_signal.read() == SC_LOGIC_1) + to_SR = SC_LOGIC_1; + else + if(cp0_inst.read() == CP0_ERET) + to_SR = SC_LOGIC_0; + else; + } + +} Index: tags/arelease/source/cpu/cp0/set_stop_pc.cpp =================================================================== --- tags/arelease/source/cpu/cp0/set_stop_pc.cpp (nonexistent) +++ tags/arelease/source/cpu/cp0/set_stop_pc.cpp (revision 13) @@ -0,0 +1,96 @@ +#include "set_stop_pc.h" + +void set_stop_pc::update_state() +{ + if (reset.read() == true) + { + currentstate.write(IdLe); + } + else + { + currentstate.write(nextstate.read()); + } +} + +void set_stop_pc::do_set_stop_pc() +{ + + // FSM + switch(currentstate) + { + case IdLe: + { + + if( check_excep.read() == SC_LOGIC_1 ) + { + cout << " EXCEPTION " << endl; + nextstate.write(STATE1); + new_pc.write(WORD_ZERO); + load_epc.write(SC_LOGIC_0); + insthold.write(true); + } + else + if(cp0_inst.read() == CP0_ERET) + { + cout <<" CPO ERET" << endl; + nextstate.write(STATE3); + new_pc.write(WORD_ZERO); + load_epc.write(SC_LOGIC_0); + insthold.write(true); + } + else + { + nextstate.write(IdLe); + new_pc.write(WORD_ZERO); + load_epc.write(SC_LOGIC_0); + insthold.write(x_insthold.read()); + } + } + break; + + case STATE1: + { + insthold.write(x_insthold.read()); + new_pc.write(0x00000008); + load_epc.write(SC_LOGIC_1); + nextstate.write(STATE2); + } + break; + + case STATE2: + { + nextstate.write(IdLe); + insthold.write(x_insthold.read()); + new_pc.write(0x00000008); + load_epc.write(SC_LOGIC_1); + } + break; + + case STATE3: + { + insthold.write(x_insthold.read()); + new_pc.write(EPC_FOR_RFE.read()); + load_epc.write(SC_LOGIC_1); + nextstate.write(IdLe); + } + break; + + case STATE4: + { + nextstate.write(IdLe); + insthold.write(x_insthold.read()); + new_pc.write(EPC_FOR_RFE.read()); + load_epc.write(SC_LOGIC_1); + } + break; + + default: + { + nextstate.write(IdLe); + new_pc.write(WORD_ZERO); + load_epc.write(SC_LOGIC_0); + insthold.write(x_insthold.read()); + } + break; + } +} Index: tags/arelease/source/cpu/cp0/exception.h =================================================================== --- tags/arelease/source/cpu/cp0/exception.h (nonexistent) +++ tags/arelease/source/cpu/cp0/exception.h (revision 13) @@ -0,0 +1,74 @@ +#include "systemc.h" +#include "../../constants/constants.h" + +SC_MODULE(exception) +{ + sc_in in_clk; + sc_in reset; + + sc_in m_wb_IBUS; + sc_in m_wb_inst_addrl; + sc_in m_wb_syscall_exception; + sc_in m_wb_illegal_instruction; + sc_in m_wb_ovf_excep; + sc_in m_wb_DBUS; + sc_in m_wb_data_addrl; + sc_in m_wb_data_addrs; + sc_in > m_wb_dataaddr; + sc_in > m_wb_instaddr; + sc_in > cp0_inst; + + //**************INTERRUPT**************** + sc_in m_wb_interrupt_signal; + //sc_out interrupt_exception; + //sc_in > ex_m_instaddr; + sc_signal to_SR; + //*************************************** + + sc_out > cause; + sc_out check_excep; + sc_out > to_EPC; + sc_out > to_BadVAddr; + + + + void compute_cause(); + + void check_for_exception(); + + void check_for_interrupt(); + + void check_for_Page_fault(); + + void save_EPC(); + + void handling_status_register(); + + SC_CTOR(exception) + { + SC_METHOD(compute_cause); + sensitive << m_wb_IBUS << m_wb_inst_addrl << m_wb_syscall_exception; + sensitive << m_wb_illegal_instruction << m_wb_ovf_excep; + sensitive << m_wb_DBUS << m_wb_data_addrl << m_wb_data_addrs; + sensitive << m_wb_interrupt_signal; + + SC_METHOD(check_for_exception); + sensitive << m_wb_IBUS << m_wb_inst_addrl << m_wb_syscall_exception; + sensitive << m_wb_illegal_instruction << m_wb_ovf_excep; + sensitive << m_wb_DBUS << m_wb_data_addrl << m_wb_data_addrs << m_wb_interrupt_signal; + + SC_METHOD(check_for_interrupt); + //sensitive << interrupt_signal; + + SC_METHOD(check_for_Page_fault); + sensitive << cause << m_wb_instaddr << m_wb_dataaddr; + + SC_METHOD(save_EPC); + sensitive << check_excep; + sensitive << m_wb_instaddr; + + SC_METHOD(handling_status_register); + sensitive << m_wb_interrupt_signal; + sensitive << cp0_inst << reset; + } +}; Index: tags/arelease/source/cpu/cp0/cp0_register.cpp =================================================================== --- tags/arelease/source/cpu/cp0/cp0_register.cpp (nonexistent) +++ tags/arelease/source/cpu/cp0/cp0_register.cpp (revision 13) @@ -0,0 +1,110 @@ +#include "cp0_register.h" + + //! Read registers +/*! + sensitive << all registers, reg_wr and reg_no + */ +void cp0_register::cp0_register_read() +{ + EPC_FOR_RFE.write( (sc_uint<32>) cp0regs[14]); + reg_out = cp0regs[reg_no.read()]; + +} + +//! Write registers +/*! + sensitive_neg << in_clk + */ +void cp0_register::cp0_register_write() +{ + if (reset.read() == true) + { + cp0regs[0] = WORD_ZERO; + cp0regs[1] = WORD_ZERO; + cp0regs[2] = WORD_ZERO; + cp0regs[3] = WORD_ZERO; + cp0regs[4] = WORD_ZERO; + cp0regs[5] = WORD_ZERO; + cp0regs[6] = WORD_ZERO; + cp0regs[7] = WORD_ZERO; + cp0regs[8] = WORD_ZERO; + cp0regs[9] = WORD_ZERO; + cp0regs[0] = WORD_ZERO; + cp0regs[11] = WORD_ZERO; + cp0regs[12] = WORD_ZERO; + cp0regs[13] = WORD_ZERO; + cp0regs[14] = WORD_ZERO; + cp0regs[15] = WORD_ZERO; + cp0regs[16] = WORD_ZERO; + cp0regs[17] = WORD_ZERO; + cp0regs[18] = WORD_ZERO; + cp0regs[19] = WORD_ZERO; + cp0regs[20] = WORD_ZERO; + cp0regs[21] = WORD_ZERO; + cp0regs[22] = WORD_ZERO; + cp0regs[23] = WORD_ZERO; + cp0regs[24] = WORD_ZERO; + cp0regs[25] = WORD_ZERO; + cp0regs[26] = WORD_ZERO; + cp0regs[27] = WORD_ZERO; + cp0regs[28] = WORD_ZERO; + cp0regs[29] = WORD_ZERO; + cp0regs[30] = WORD_ZERO; + cp0regs[31] = WORD_ZERO; + } + else + if(check_excep.read() == SC_LOGIC_1) + { + cp0regs[13] = cause.read(); + cp0regs[14] = (sc_lv<32>) to_EPC.read(); + cp0regs[8] = (sc_lv<32>) to_BadVAddr.read(); + cp0regs[12] = Temp_Status_Register.read(); + } + else + if((cp0_inst.read() == CP0_ERET) && (insthold.read()==true)) + cp0regs[12] = Temp_Status_Register.read(); + else + if ((reg_rw.read() == SC_LOGIC_1)) + { + cp0regs[reg_no.read()] = reg_rs.read(); + } +} + +void cp0_register::cp0_status_register() +{ + + sc_lv<6> temp; + sc_lv<32> temp_32; + + if((check_excep.read() == SC_LOGIC_1)) + { + temp_32 = (cp0regs[12]).read(); + + temp.range(5,2) = temp_32.range(3,0); + temp.range(1,0) = "00"; + + temp_32.range(5,0) = temp; + + Temp_Status_Register.write(temp_32); + } + else + { + temp_32 = (cp0regs[12]).read(); + + temp.range(3,0) = temp_32.range(5,2); + temp.range(5,4) = temp_32.range(5,4); + + temp_32.range(5,0) = temp; + + Temp_Status_Register.write(temp_32); + } +} + +void cp0_register::enable_interrupt_and_OS() +{ + enable_interrupt.write(((cp0regs[12]).read())[0]); + enable_kernel_mode.write(((cp0regs[12]).read())[1]); + + +} + Index: tags/arelease/source/cpu/cp0/set_stop_pc.h =================================================================== --- tags/arelease/source/cpu/cp0/set_stop_pc.h (nonexistent) +++ tags/arelease/source/cpu/cp0/set_stop_pc.h (revision 13) @@ -0,0 +1,39 @@ +#include "systemc.h" +#include "../../constants/constants.h" + +enum State {IdLe, STATE1, STATE2, STATE3, STATE4}; +SC_MODULE(set_stop_pc) +{ + sc_in in_clk; // clock + sc_in reset; // reset + + sc_in x_insthold; // freeze signal from InstMemory + sc_out insthold; // output freeze signal + + sc_in > pc_in; // program counter from PC_STAGE + sc_in > cp0_inst; // coprocessor CP0 instruction + sc_out > new_pc; // next PC when exception occur! + sc_out load_epc; // signal that tell to PC STAGE to load Exception_PC + sc_in check_excep; // signal that tell if there is an exception + sc_in > EPC_FOR_RFE; // PC that must be loaded when exception routine finish! + + sc_signal currentstate , nextstate; // State from Finite State Machine + + void update_state(); + void do_set_stop_pc(); + + SC_CTOR(set_stop_pc) + { + SC_METHOD(update_state); + sensitive_pos << in_clk; + + SC_METHOD(do_set_stop_pc); + sensitive << reset; + sensitive << x_insthold; + sensitive << check_excep; + sensitive << currentstate; + sensitive << cp0_inst; + sensitive << EPC_FOR_RFE; + + } +}; Index: tags/arelease/source/cpu/cp0/cp0_register.h =================================================================== --- tags/arelease/source/cpu/cp0/cp0_register.h (nonexistent) +++ tags/arelease/source/cpu/cp0/cp0_register.h (revision 13) @@ -0,0 +1,61 @@ +#include "systemc.h" +#include "../../constants/constants.h" + +SC_MODULE(cp0_register) +{ + sc_in in_clk; + sc_in reset; + sc_in insthold; + + sc_signal > cp0regs[32]; + + sc_in > reg_no; + sc_in reg_rw; + sc_in > reg_rs; + sc_out > reg_out; + + sc_in check_excep; + //sc_in interrupt_signal; + sc_in > cause; + sc_in > to_BadVAddr; + sc_in > to_EPC; + + sc_in > cp0_inst; + + sc_out > EPC_FOR_RFE; + sc_signal > Temp_Status_Register; + + sc_out enable_interrupt; + sc_out enable_kernel_mode; + + void cp0_register_read(); + void cp0_register_write(); + void cp0_status_register(); + void enable_interrupt_and_OS(); + + SC_CTOR(cp0_register) + { + SC_METHOD(cp0_register_read); + sensitive << reg_no << cp0regs[0] << cp0regs[1] << cp0regs[2]; + sensitive << cp0regs[3] << cp0regs[4] << cp0regs[5] << cp0regs[6] << cp0regs[7]; + sensitive << cp0regs[8] << cp0regs[9] << cp0regs[10] << cp0regs[11] << cp0regs[12]; + sensitive << cp0regs[13] << cp0regs[14] << cp0regs[15] << cp0regs[16] << cp0regs[17]; + sensitive << cp0regs[18] << cp0regs[19] << cp0regs[20] << cp0regs[21] << cp0regs[22]; + sensitive << cp0regs[23] << cp0regs[24] << cp0regs[25] << cp0regs[26] << cp0regs[27]; + sensitive << cp0regs[28] << cp0regs[29] << cp0regs[30] << cp0regs[31]; + + SC_METHOD(cp0_register_write); + sensitive_neg << in_clk; + //sensitive << cause << to_EPC << to_BadVAddr; + //sensitive << check_excep; + + SC_METHOD(cp0_status_register); + sensitive << check_excep << cp0_inst << cp0regs[12]; + + SC_METHOD(enable_interrupt_and_OS); + sensitive << cp0regs[12]; + } + + + +}; Index: tags/arelease/source/cpu/mem_stage.cpp =================================================================== --- tags/arelease/source/cpu/mem_stage.cpp (nonexistent) +++ tags/arelease/source/cpu/mem_stage.cpp (revision 13) @@ -0,0 +1,5 @@ +//! MEM Stage module +// +// $Id: mem_stage.cpp,v 1.1.1.1 2006-01-31 10:55:27 igorloi Exp $ +// +#include "mem_stage.h" Index: tags/arelease/source/cpu/writeback_ctrl.h =================================================================== --- tags/arelease/source/cpu/writeback_ctrl.h (nonexistent) +++ tags/arelease/source/cpu/writeback_ctrl.h (revision 13) @@ -0,0 +1,28 @@ +#include "systemc.h" +#include "../constants/constants.h" + +SC_MODULE(writeback_ctrl) +{ + sc_in m_wb_IBUS; + sc_in m_wb_inst_addrl; + sc_in m_wb_syscall_exception; + sc_in m_wb_illegal_instruction; + sc_in m_wb_ovf_excep; + sc_in m_wb_DBUS; + sc_in m_wb_data_addrl; + sc_in m_wb_data_addrs; + sc_in m_wb_interrupt_signal; + + + sc_out wb_exception; + + void do_writeback_ctrl(); + + SC_CTOR(writeback_ctrl) + { + SC_METHOD(do_writeback_ctrl); + sensitive << m_wb_IBUS << m_wb_inst_addrl << m_wb_syscall_exception; + sensitive << m_wb_illegal_instruction << m_wb_ovf_excep; + sensitive << m_wb_DBUS << m_wb_data_addrl << m_wb_data_addrs << m_wb_interrupt_signal; + } +}; Index: tags/arelease/source/cpu/pc_stage/reg_pc.cpp =================================================================== --- tags/arelease/source/cpu/pc_stage/reg_pc.cpp (nonexistent) +++ tags/arelease/source/cpu/pc_stage/reg_pc.cpp (revision 13) @@ -0,0 +1,37 @@ +#include "reg_pc.h" + +void reg_pc::do_reg_pc() +{ + sc_lv<32> pc; + + instdatawrite = WORD_ZERO; + + if(reset.read() == true) + { + instreq.write(SC_LOGIC_1); + instrw.write(SC_LOGIC_0); + + instaddr = pc = PC_START; + pc_out = pc = PC_START; + } + else + { + if((datahold.read() == false) && (insthold.read() == false) && (enable_pc.read() == SC_LOGIC_1)) + { + instreq.write(SC_LOGIC_1); + instrw.write(SC_LOGIC_0); + pc = pc_in.read(); + instaddr.write(pc); + pc_out.write(pc_in.read()); + } + else + if((datahold.read() == false) && (insthold.read() == false) && (enable_pc.read() == SC_LOGIC_0)) + { + instreq.write(SC_LOGIC_0); + instrw.write(SC_LOGIC_0); + + instaddr = pc = PC_START; + pc_out = pc = PC_START; + } + } +} Index: tags/arelease/source/cpu/pc_stage/reg_pc.h =================================================================== --- tags/arelease/source/cpu/pc_stage/reg_pc.h (nonexistent) +++ tags/arelease/source/cpu/pc_stage/reg_pc.h (revision 13) @@ -0,0 +1,32 @@ +#include "systemc.h" +#include "../../constants/constants.h" +#include "../../constants/config.h" + +SC_MODULE(reg_pc) +{ + sc_in in_clk; + sc_in reset; + + sc_in insthold; + sc_in datahold; + + sc_in enable_pc; + + sc_in > pc_in; + sc_out > pc_out; + + sc_out > instaddr; + sc_out > instdatawrite; + + sc_out instreq; + sc_out instrw; + + + void do_reg_pc(); + + SC_CTOR(reg_pc) + { + SC_METHOD(do_reg_pc); + sensitive_pos << in_clk; + } +}; Index: tags/arelease/source/cpu/ex_stage.h =================================================================== --- tags/arelease/source/cpu/ex_stage.h (nonexistent) +++ tags/arelease/source/cpu/ex_stage.h (revision 13) @@ -0,0 +1,248 @@ +// EX_STAGE +#ifndef _EX_STAGE_H +#define _EX_STAGE_H + + #include + + #include "./ex_stage/reg_ex.h" + #include "./ex_stage/alu.h" + #include "./ex_stage/backwrite.h" + #include "./ex_stage/multiply.h" + #include "./ex_stage/mux_lo.h" + #include "./ex_stage/mux_hi.h" + #include "./ex_stage/mux_rd.h" + #include "./ex_stage/execute_ctrl.h" + #include "../constants/config.h" + +#ifdef _MULT_PIPELINE_ + #include "./ex_stage/fsm.h" +#endif + +SC_MODULE(ex_stage) +{ + sc_in in_clk; + sc_in reset; + + sc_in insthold; + sc_in datahold; + + // signals from id_stage + sc_in > id_ex_alu1; + sc_in > id_ex_alu2; + sc_in > id_ex_datastore; + sc_in > id_ex_alu_ctrl; + sc_in > id_ex_alu_opcode; + sc_in > id_ex_alu_function; + sc_in id_ex_equal; + sc_in > id_ex_byteselect; + sc_in id_ex_bssign; + sc_in > id_ex_alu_sa; + + // signals to be sent on to mem_stage + sc_in id_ex_datareq; + sc_in id_ex_datarw; + sc_in id_ex_memtoreg; + + // signal to control save in register + sc_in > id_ex_writeregister_out; + sc_in id_ex_regwrite_out; + + sc_out > id_ex_m_writeregister; + sc_out id_ex_m_regwrite; + + sc_out id_ex_m_datareq; + sc_out id_ex_m_datarw; + sc_out > id_ex_m_datastore; + sc_out > ex_m_alu; + + sc_out id_ex_m_memtoreg; + + sc_out > ex_id_forward; + + // Signals directly to mem stage + sc_out > id_ex_m_byteselect; + sc_out id_ex_m_bssign; + + sc_signal ovf_excep; + + sc_in > id_ex_inst; // instruction coming from ID_STAGE + sc_out > ex_mem_inst; // instruction to MEM_STAGE + + sc_in id_ex_IBUS; + sc_in id_ex_inst_addrl; + sc_in id_ex_syscall_exception; + sc_in id_ex_illegal_instruction; + sc_out ex_m_IBUS; + sc_out ex_m_inst_addrl; + sc_out ex_m_syscall_exception; + sc_out ex_m_illegal_instruction; + sc_out ex_m_ovf_excep; + + sc_out ex_exception; + sc_in enable_execute; + + sc_in > id_ex_instaddr; + sc_out > ex_m_instaddr; + + // Signals from cp0 + // To prevent memory access in case of Address Error Exception + sc_in addr_err; + + sc_signal > ex_alu_s; + sc_signal > ex_id_forward_s; + sc_signal > in_ex_alu_s; + sc_signal > in_ex_id_forward_s; + + // special registers + sc_signal > hi; + sc_signal > lo; + sc_signal > in_lo; + sc_signal > in_hi; + sc_signal > out_lo; + sc_signal > out_hi; + + + // Output from pipelined Multiplier + //******************************** +#ifdef _MULT_PIPELINE_ + sc_out hold_pipe; + sc_signal ready; +#endif + //********************************* + + + sc_signal carry; + + reg_ex *reg_ex1; + alu *alu1; + backwrite *backwrite1; + multiply *multiply1; + mux_lo *mux_lo1; + mux_hi *mux_hi1; + mux_rd *mux_rd1; + execute_ctrl *execute_ctrl1; +#ifdef _MULT_PIPELINE_ + fsm *fsm1; +#endif + SC_CTOR(ex_stage) + { + reg_ex1 = new reg_ex("reg_ex"); + reg_ex1->in_clk(in_clk); + reg_ex1->reset(reset); + reg_ex1->insthold(insthold); + reg_ex1->datahold(datahold); + reg_ex1->addr_err(addr_err); + reg_ex1->ex_alu_s(ex_alu_s); + reg_ex1->ex_m_alu(ex_m_alu); + reg_ex1->id_ex_datastore(id_ex_datastore); + reg_ex1->id_ex_m_datastore(id_ex_m_datastore); + reg_ex1->id_ex_datareq(id_ex_datareq); + reg_ex1->id_ex_m_datareq(id_ex_m_datareq); + reg_ex1->id_ex_datarw(id_ex_datarw); + reg_ex1->id_ex_m_datarw(id_ex_m_datarw); + reg_ex1->id_ex_memtoreg(id_ex_memtoreg); + reg_ex1->id_ex_m_memtoreg(id_ex_m_memtoreg); + reg_ex1->id_ex_writeregister_out(id_ex_writeregister_out); + reg_ex1->id_ex_m_writeregister(id_ex_m_writeregister); + reg_ex1->id_ex_regwrite_out(id_ex_regwrite_out); + reg_ex1->id_ex_m_regwrite(id_ex_m_regwrite); + reg_ex1->id_ex_byteselect(id_ex_byteselect); + reg_ex1->id_ex_m_byteselect(id_ex_m_byteselect); + reg_ex1->id_ex_bssign(id_ex_bssign); + reg_ex1->id_ex_m_bssign(id_ex_m_bssign); + reg_ex1->in_lo(in_lo); + reg_ex1->out_lo(out_lo); + reg_ex1->in_hi(in_hi); + reg_ex1->out_hi(out_hi); + //************************************************************** + reg_ex1->id_ex_IBUS(id_ex_IBUS); + reg_ex1->id_ex_inst_addrl(id_ex_inst_addrl); + reg_ex1->id_ex_syscall_exception(id_ex_syscall_exception); + reg_ex1->id_ex_illegal_instruction(id_ex_illegal_instruction); + reg_ex1->ovf_excep(ovf_excep); + reg_ex1->ex_m_IBUS(ex_m_IBUS); + reg_ex1->ex_m_inst_addrl(ex_m_inst_addrl); + reg_ex1->ex_m_syscall_exception(ex_m_syscall_exception); + reg_ex1->ex_m_illegal_instruction(ex_m_illegal_instruction); + reg_ex1->ex_m_ovf_excep(ex_m_ovf_excep); + reg_ex1->id_ex_instaddr(id_ex_instaddr); + reg_ex1->ex_m_instaddr(ex_m_instaddr); + // instruction from ID_STAGE to EX_STAGE + //****************************************************** + reg_ex1->id_ex_inst(id_ex_inst); + reg_ex1->ex_mem_inst(ex_mem_inst); + //****************************************************** + //************************************************************** + reg_ex1->enable_execute(enable_execute); + + execute_ctrl1 = new execute_ctrl("execute_ctrl"); + execute_ctrl1->id_ex_IBUS(id_ex_IBUS); + execute_ctrl1->id_ex_inst_addrl(id_ex_inst_addrl); + execute_ctrl1->id_ex_syscall_exception(id_ex_syscall_exception); + execute_ctrl1->id_ex_illegal_instruction(id_ex_illegal_instruction); + execute_ctrl1->ovf_excep(ovf_excep); + execute_ctrl1->ex_exception(ex_exception); + + alu1 = new alu("alu"); + alu1->id_ex_alu1(id_ex_alu1); + alu1->id_ex_alu2(id_ex_alu2); + alu1->id_ex_alu_ctrl(id_ex_alu_ctrl); + alu1->id_ex_equal(id_ex_equal); + alu1->id_ex_alu_sa(id_ex_alu_sa); + alu1->ovf_excep(ovf_excep); + alu1->carry(carry); + alu1->ex_alu_s(in_ex_alu_s); + alu1->ex_id_forward_s(in_ex_id_forward_s); + + backwrite1 = new backwrite("backwrite"); + backwrite1->ex_id_forward_s(ex_id_forward_s); + backwrite1->ex_id_forward(ex_id_forward); + + + multiply1 = new multiply("multiply"); + multiply1->in_clk(in_clk); + multiply1->reset(reset); + #ifdef _MULT_PIPELINE_ + multiply1->ready(ready); + #endif + multiply1->id_ex_alu1(id_ex_alu1); + multiply1->id_ex_alu2(id_ex_alu2); + multiply1->id_ex_alu_function(id_ex_alu_function); + multiply1->id_ex_alu_opcode(id_ex_alu_opcode); + multiply1->hi(hi); + multiply1->lo(lo); + +#ifdef _MULT_PIPELINE_ + fsm1 = new fsm("fsm"); + fsm1->hold_pipe(hold_pipe); + fsm1->ready(ready); + fsm1->in_clk(in_clk); + fsm1->reset(reset); + fsm1->id_ex_alu_function(id_ex_alu_function); + fsm1->id_ex_alu_opcode(id_ex_alu_opcode); +#endif + mux_lo1 = new mux_lo("mux_lo"); + mux_lo1->lo(lo); + mux_lo1->rs(id_ex_alu1); + mux_lo1->id_ex_alu_ctrl(id_ex_alu_ctrl); + mux_lo1->out(in_lo); + + mux_hi1 = new mux_hi("mux_hi"); + mux_hi1->hi(hi); + mux_hi1->rs(id_ex_alu1); + mux_hi1->id_ex_alu_ctrl(id_ex_alu_ctrl); + mux_hi1->out(in_hi); + + mux_rd1 = new mux_rd("mux_rd"); + mux_rd1->in_ex_id_forward_s(in_ex_id_forward_s); // dalla ALU + mux_rd1->in_ex_alu_s(in_ex_alu_s); // dalla ALU + mux_rd1->out_lo(out_lo); // dai registri LO + mux_rd1->out_hi(out_hi); // dai registri HI + mux_rd1->id_ex_alu_ctrl(id_ex_alu_ctrl); // selettore del MUX + mux_rd1->out_ex_id_forward_s(ex_id_forward_s); // USCITE verso i registri di pipeline + mux_rd1->out_ex_alu_s(ex_alu_s); + } +}; + +#endif + Index: tags/arelease/source/cpu/mux_instaddr.h =================================================================== --- tags/arelease/source/cpu/mux_instaddr.h (nonexistent) +++ tags/arelease/source/cpu/mux_instaddr.h (revision 13) @@ -0,0 +1,23 @@ +#include "systemc.h" +#include "../constants/constants.h" + +SC_MODULE(mux_instaddr) +{ + sc_in > m_wb_instaddr; + sc_in > ex_m_instaddr; + sc_in > ex_mem_inst; + + sc_in m_wb_interrupt_signal; + + sc_out > m_wb_instaddr_s; + + + void do_mux_instaddr(); + + SC_CTOR(mux_instaddr) + { + SC_METHOD(do_mux_instaddr); + sensitive << m_wb_instaddr << ex_m_instaddr << m_wb_instaddr; + sensitive << ex_mem_inst; + } +}; Index: tags/arelease/source/cpu/mem_stage.h =================================================================== --- tags/arelease/source/cpu/mem_stage.h (nonexistent) +++ tags/arelease/source/cpu/mem_stage.h (revision 13) @@ -0,0 +1,201 @@ +//! MEM Stage module +// +// $Id: mem_stage.h,v 1.1.1.1 2006-01-31 10:55:27 igorloi Exp $ +// +#ifndef _MEM_STAGE_H +#define _MEM_STAGE_H + +#include "systemc.h" + +#include "./mem_stage/select_mem.h" +#include "./mem_stage/reg_mem.h" +#include "./mem_stage/multiplexer_mem.h" +#include "./mem_stage/memstage_ctrl.h" +#include "./mem_stage/mux_interrupt.h" +#include "./mem_stage/flag_interr.h" + +SC_MODULE(mem_stage) +{ + sc_in in_clk; + sc_in reset; + + sc_in insthold; + sc_in datahold; + + sc_in id_ex_m_datareq; + sc_in id_ex_m_datarw; + sc_in > id_ex_m_datastore; + sc_in > ex_m_alu; + + // signal to mem_stage from ex_stage + sc_in id_ex_m_memtoreg; + sc_in > id_ex_m_byteselect; + sc_in id_ex_m_bssign; + + // signal to data memory + sc_in > dataread; + sc_out > datawrite; + sc_out > dataaddr; + sc_out datareq; + sc_out datarw; + sc_out > databs; + + // signal to control save in register + sc_in > id_ex_m_writeregister; + sc_in id_ex_m_regwrite; + + sc_out > id_ex_m_wb_writeregister; + sc_out id_ex_m_wb_regwrite; + + sc_out > m_id_forward; + sc_out > wb_id_forward; + + sc_in enable_memstage; + sc_out mem_exception; + + sc_signal > id_store; + + // EXCEPTION SIGNALS + sc_in ex_m_IBUS; + sc_in ex_m_inst_addrl; + sc_in ex_m_syscall_exception; + sc_in ex_m_illegal_instruction; + sc_in ex_m_ovf_excep; + sc_in DBUS; + sc_in data_addrl; + sc_in data_addrs; + + // INTERRUPT SIGNAL + sc_in interrupt_signal; + sc_out m_wb_interrupt_signal; + sc_in enable_interrupt; + sc_signal interrupt_signal_out; + sc_signal interrupt_out_out; + sc_signal ground; + + // exception status vector -> to CPO-Cause + sc_out m_wb_IBUS; + sc_out m_wb_inst_addrl; + sc_out m_wb_syscall_exception; + sc_out m_wb_illegal_instruction; + sc_out m_wb_ovf_excep; + sc_out m_wb_DBUS; + sc_out m_wb_data_addrl; + sc_out m_wb_data_addrs; + + sc_in > ex_mem_inst; // instruction coming from EX_STAGE + sc_out > mem_wb_inst; // instruction to WRITE_BACK Phases + + sc_in > ex_m_instaddr; + sc_out > m_wb_instaddr; + + // sc_in > ex_m_dataaddr; il segnale �dataddr! + sc_out > m_wb_dataaddr; + +#ifdef _MULT_PIPELINE_ + sc_in hold_pipe; +#endif + + select_mem *select_mem1; + multiplexer_mem *multiplexer_mem1; + reg_mem *reg_mem1; + memstage_ctrl *memstage_ctrl1; + mux_interrupt *mux_interrupt1; + flag_interr *flag_interr1; + + SC_CTOR(mem_stage) + { + select_mem1 = new select_mem("select_mem"); + select_mem1->id_ex_m_datareq(id_ex_m_datareq); + select_mem1->id_ex_m_datarw(id_ex_m_datarw); + select_mem1->id_ex_m_byteselect(id_ex_m_byteselect); + select_mem1->id_ex_m_datastore(id_ex_m_datastore); + select_mem1->datawrite(datawrite); + select_mem1->ex_m_alu(ex_m_alu); + select_mem1->dataaddr(dataaddr); + select_mem1->datareq(datareq); + select_mem1->datarw(datarw); + select_mem1->databs(databs); + select_mem1->enable_memstage(enable_memstage); + + multiplexer_mem1 = new multiplexer_mem("multiplexer_mem"); + multiplexer_mem1->id_ex_m_byteselect(id_ex_m_byteselect); + multiplexer_mem1->id_ex_m_bssign(id_ex_m_bssign); + multiplexer_mem1->id_ex_m_memtoreg(id_ex_m_memtoreg); + multiplexer_mem1->ex_m_alu(ex_m_alu); + multiplexer_mem1->dataread(dataread); + multiplexer_mem1->id_store(id_store); + multiplexer_mem1->m_id_forward(m_id_forward); + + reg_mem1 = new reg_mem("reg_mem"); + reg_mem1->in_clk(in_clk); + reg_mem1->reset(reset); + reg_mem1->insthold(insthold); + reg_mem1->datahold(datahold); + reg_mem1->wb_id_forward(wb_id_forward); + reg_mem1->id_ex_m_wb_writeregister(id_ex_m_wb_writeregister); + reg_mem1->id_ex_m_wb_regwrite(id_ex_m_wb_regwrite); + reg_mem1->id_store(id_store); + reg_mem1->id_ex_m_writeregister(id_ex_m_writeregister); + reg_mem1->id_ex_m_regwrite(id_ex_m_regwrite); + + reg_mem1->ex_m_IBUS(ex_m_IBUS); + reg_mem1->ex_m_inst_addrl(ex_m_inst_addrl); + reg_mem1->ex_m_syscall_exception(ex_m_syscall_exception); + reg_mem1->ex_m_illegal_instruction(ex_m_illegal_instruction); + reg_mem1->ex_m_ovf_excep(ex_m_ovf_excep); + reg_mem1->DBUS(DBUS); + reg_mem1->data_addrl(data_addrl); + reg_mem1->data_addrs(data_addrs); + reg_mem1->ex_m_instaddr(ex_m_instaddr); + reg_mem1->ex_m_dataaddr(dataaddr); + reg_mem1->interrupt_signal(interrupt_out_out); + reg_mem1->m_wb_interrupt_signal(m_wb_interrupt_signal); + + reg_mem1->m_wb_IBUS(m_wb_IBUS); + reg_mem1->m_wb_inst_addrl(m_wb_inst_addrl); + reg_mem1->m_wb_syscall_exception(m_wb_syscall_exception); + reg_mem1->m_wb_illegal_instruction(m_wb_illegal_instruction); + reg_mem1->m_wb_ovf_excep(m_wb_ovf_excep); + reg_mem1->m_wb_DBUS(m_wb_DBUS); + reg_mem1->m_wb_data_addrl(m_wb_data_addrl); + reg_mem1->m_wb_data_addrs(m_wb_data_addrs); + reg_mem1->m_wb_instaddr(m_wb_instaddr); + reg_mem1->m_wb_dataaddr(m_wb_dataaddr); + reg_mem1->ex_mem_inst(ex_mem_inst); + reg_mem1->mem_wb_inst(mem_wb_inst); + reg_mem1->enable_memstage(enable_memstage); + + memstage_ctrl1 = new memstage_ctrl("memstage_ctrl"); + memstage_ctrl1->ex_m_IBUS(ex_m_IBUS); + memstage_ctrl1->ex_m_inst_addrl(ex_m_inst_addrl); + memstage_ctrl1->ex_m_syscall_exception(ex_m_syscall_exception); + memstage_ctrl1->ex_m_illegal_instruction(ex_m_illegal_instruction); + memstage_ctrl1->ex_m_ovf_excep(ex_m_ovf_excep); + memstage_ctrl1->DBUS(DBUS); + memstage_ctrl1->data_addrl(data_addrl); + memstage_ctrl1->data_addrs(data_addrs); + memstage_ctrl1->mem_exception(mem_exception); + memstage_ctrl1->interrupt_signal(interrupt_out_out); + + flag_interr1 = new flag_interr("flag_interr"); + flag_interr1->in_clk(in_clk); + flag_interr1->reset(reset); + flag_interr1->interrupt_in(interrupt_signal_out); + flag_interr1->interrupt_out(interrupt_out_out); + + ground.write(false); + + mux_interrupt1 = new mux_interrupt("mux_interrupt"); + mux_interrupt1->IN_A(interrupt_signal); + mux_interrupt1->IN_B(ground); + #ifdef _MULT_PIPELINE_ + mux_interrupt1->hold_pipe(hold_pipe); + #endif + mux_interrupt1->SEL(enable_interrupt); + mux_interrupt1->OUT(interrupt_signal_out); + } +}; + + +#endif Index: tags/arelease/source/cpu/enable_stage.cpp =================================================================== --- tags/arelease/source/cpu/enable_stage.cpp (nonexistent) +++ tags/arelease/source/cpu/enable_stage.cpp (revision 13) @@ -0,0 +1,62 @@ +#include "enable_stage.h" + +void enable_stage::do_enable_stage() +{ + if(wb_exception.read() == SC_LOGIC_1) + { + enable_pc.write(SC_LOGIC_0); + enable_fetch.write(SC_LOGIC_0); + enable_decode.write(SC_LOGIC_0); + enable_execute.write(SC_LOGIC_0); + enable_memstage.write(SC_LOGIC_0); + } + else + if(mem_exception.read() == SC_LOGIC_1) + { + enable_pc.write(SC_LOGIC_0); + enable_fetch.write(SC_LOGIC_0); + enable_decode.write(SC_LOGIC_0); + enable_execute.write(SC_LOGIC_0); + enable_memstage.write(SC_LOGIC_0); + } + else + if(ex_exception.read() == SC_LOGIC_1) + { + enable_pc.write(SC_LOGIC_0); + enable_fetch.write(SC_LOGIC_0); + enable_decode.write(SC_LOGIC_0); + enable_execute.write(SC_LOGIC_0); + enable_memstage.write(SC_LOGIC_1); + } + else + if(id_exception.read() == SC_LOGIC_1) + { + enable_pc.write(SC_LOGIC_0); + enable_fetch.write(SC_LOGIC_0); + enable_decode.write(SC_LOGIC_0); + enable_execute.write(SC_LOGIC_1); + enable_memstage.write(SC_LOGIC_1); + } + else + if(if_exception.read() == SC_LOGIC_1) + { + enable_pc.write(SC_LOGIC_0); + enable_fetch.write(SC_LOGIC_0); + enable_decode.write(SC_LOGIC_1); + enable_execute.write(SC_LOGIC_1); + enable_memstage.write(SC_LOGIC_1); + } + else + { + enable_pc.write(SC_LOGIC_1); + enable_fetch.write(SC_LOGIC_1); + enable_decode.write(SC_LOGIC_1); + enable_execute.write(SC_LOGIC_1); + enable_memstage.write(SC_LOGIC_1); + } + + + + + +} Index: tags/arelease/source/cpu/sc_cpu.cpp =================================================================== --- tags/arelease/source/cpu/sc_cpu.cpp (nonexistent) +++ tags/arelease/source/cpu/sc_cpu.cpp (revision 13) @@ -0,0 +1,295 @@ +// +// $Id: sc_cpu.cpp,v 1.1.1.1 2006-01-31 10:55:28 igorloi Exp $ +// +// #define _ASM_ONLY_ +// #define _DOBRANCH_ -- should be defined in id_stage only! +#include "sc_cpu.h" +#include "../constants/config.h" + +sc_cpu::sc_cpu(const sc_module_name& name_) +{ + SC_METHOD(clocktik); + sensitive_pos << in_clk; + + pc = new pc_stage("pc_stage"); + pc->in_clk(in_clk); + pc->reset(reset); + pc->pc_in(pc_in); + pc->pc_out(pc_out); +#ifdef _MULT_PIPELINE_ + pc->insthold(insthold_W); +#endif +#ifndef _MULT_PIPELINE_ + pc->insthold(insthold); +#endif + pc->datahold(datahold); + pc->instreq(instreq); + pc->instaddr(instaddr); + pc->instdatawrite(instdatawrite); + pc->instrw(instrw); + pc->enable_pc(enable_pc); + cout << "PC STAGE ..... OK" << endl; + + if_s = new if_stage("if_stage"); + if_s->in_clk(in_clk); + if_s->reset(reset); + if_s->pc_out(pc_out); + if_s->id_new_pc(id_new_pc); + if_s->id_jmp_tar(id_jmp_tar); + if_s->id_ctrl(id_ctrl); + if_s->id_branch(id_branch); + if_s->pc_in(pc_in); + if_s->instdataread(instdataread); + if_s->if_id_inst(if_id_inst); + if_s->if_id_next_pc(if_id_next_pc); +#ifdef _MULT_PIPELINE_ + if_s->insthold(insthold_W); +#else + if_s->insthold(insthold); +#endif + if_s->datahold(datahold); + if_s->new_pc(new_pc); + if_s->load_epc(load_epc); + + + // only to mananage exceptions + //****************************************** + if_s->IBUS(IBUS); + if_s->inst_addrl(inst_addrl); + if_s->if_id_IBUS(if_id_IBUS); + if_s->if_id_inst_addrl(if_id_inst_addrl); + if_s->enable_fetch(enable_fetch); + if_s->if_exception(if_exception); + if_s->pc_if_instaddr(instaddr); + if_s->if_id_instaddr(if_id_instaddr); + //****************************************** + cout << "IF STAGE ..... OK" << endl; + + + + id = new id_stage("id_stage"); + id->in_clk(in_clk); + id->reset(reset); +#ifdef _MULT_PIPELINE_ + id->insthold(insthold_W); +#else + id->insthold(insthold); +#endif + id->datahold(datahold); + id->if_id_next_pc(if_id_next_pc); + id->if_id_inst(if_id_inst); + id->id_ex_inst(id_ex_inst); + id->id_jmp_tar(id_jmp_tar); + id->id_new_pc(id_new_pc); + id->id_branch(id_branch); + id->id_ctrl(id_ctrl); + id->id_ex_alu1(id_ex_alu1); + id->id_ex_alu2(id_ex_alu2); + id->id_ex_datastore(id_ex_datastore); + id->id_ex_alu_ctrl(id_ex_alu_ctrl); + id->id_ex_alu_opcode(id_ex_alu_opcode); + id->id_ex_alu_function(id_ex_alu_function); + id->id_ex_alu_sa(id_ex_alu_sa); + + id->id_ex_byteselect(id_ex_byteselect); + id->id_ex_bssign(id_ex_bssign); + + id->id_ex_equal(id_ex_equal); + id->id_ex_datareq(id_ex_datareq); + id->id_ex_datarw(id_ex_datarw); + id->id_ex_memtoreg(id_ex_memtoreg); + id->id_ex_writeregister_out(id_ex_writeregister_out); + id->id_ex_regwrite_out(id_ex_regwrite_out); + id->id_ex_m_writeregister(id_ex_m_writeregister); + id->id_ex_m_wb_writeregister(id_ex_m_wb_writeregister); + id->id_ex_m_regwrite(id_ex_m_regwrite); + id->id_ex_m_wb_regwrite(id_ex_m_wb_regwrite); + id->ex_id_forward(ex_id_forward); + id->m_id_forward(m_id_forward); + id->wb_id_forward(wb_id_forward); + id->cp0_inst(cp0_inst); + id->cp0_reg_no(reg_no); + id->cp0_reg_rw(reg_rw); + id->cp0_reg_rs(reg_rs); + id->cp0_reg_out(reg_out); + // only to mananage exceptions + //******************************************************* + id->if_id_IBUS(if_id_IBUS); + id->if_id_inst_addrl(if_id_inst_addrl); + id->id_ex_IBUS(id_ex_IBUS); + id->id_ex_inst_addrl(id_ex_inst_addrl); + id->id_ex_syscall_exception(id_ex_syscall_exception); + id->id_ex_illegal_instruction(id_ex_illegal_instruction); + id->if_id_instaddr(if_id_instaddr); + id->id_ex_instaddr(id_ex_instaddr); + + //******************************************************* + id->enable_decode(enable_decode); + id->id_exception(id_exception); + id->enable_kernel_mode(enable_kernel_mode); // when this bit is set to 0 the cpu are running in Kernel_mode + cout << "ID STAGE ..... OK" << endl; + + + ex = new ex_stage("ex_stage"); + ex->in_clk(in_clk); + ex->reset(reset); +#ifdef _MULT_PIPELINE_ + ex->insthold(insthold_W); +#else + ex->insthold(insthold); +#endif + ex->datahold(datahold); + ex->id_ex_alu1(id_ex_alu1); + ex->id_ex_alu2(id_ex_alu2); + ex->id_ex_datastore(id_ex_datastore); + ex->id_ex_alu_ctrl(id_ex_alu_ctrl); + ex->id_ex_alu_opcode(id_ex_alu_opcode); + ex->id_ex_alu_function(id_ex_alu_function); + ex->id_ex_alu_sa(id_ex_alu_sa); + ex->id_ex_byteselect(id_ex_byteselect); + ex->id_ex_bssign(id_ex_bssign); + + ex->id_ex_equal(id_ex_equal); + ex->id_ex_datareq(id_ex_datareq); + ex->id_ex_datarw(id_ex_datarw); + ex->id_ex_memtoreg(id_ex_memtoreg); + ex->id_ex_writeregister_out(id_ex_writeregister_out); + ex->id_ex_regwrite_out(id_ex_regwrite_out); + ex->id_ex_m_writeregister(id_ex_m_writeregister); + ex->id_ex_m_regwrite(id_ex_m_regwrite); + ex->id_ex_m_datastore(id_ex_m_datastore); + ex->ex_m_alu(ex_m_alu); + ex->id_ex_m_datareq(id_ex_m_datareq); + ex->id_ex_m_datarw(id_ex_m_datarw); + ex->id_ex_m_memtoreg(id_ex_m_memtoreg); + ex->id_ex_m_byteselect(id_ex_m_byteselect); + ex->id_ex_m_bssign(id_ex_m_bssign); + ex->ex_id_forward(ex_id_forward); + // only to mananage exceptions + //******************************************************* + ex->id_ex_IBUS(id_ex_IBUS); + ex->id_ex_inst_addrl(id_ex_inst_addrl); + ex->id_ex_inst(id_ex_inst); + ex->ex_mem_inst(ex_mem_inst); + ex->id_ex_syscall_exception(id_ex_syscall_exception); + ex->id_ex_illegal_instruction(id_ex_illegal_instruction); + ex->ex_m_IBUS(ex_m_IBUS); + ex->ex_m_inst_addrl(ex_m_inst_addrl); + ex->ex_m_syscall_exception(ex_m_syscall_exception); + ex->ex_m_illegal_instruction(ex_m_illegal_instruction); + ex->ex_m_ovf_excep(ex_m_ovf_excep); + ex->id_ex_instaddr(id_ex_instaddr); + ex->ex_m_instaddr(ex_m_instaddr); + //******************************************************* + // from cp0 + ex->addr_err(addr_err); + ex->enable_execute(enable_execute); + ex->ex_exception(ex_exception); +#ifdef _MULT_PIPELINE_ + ex->hold_pipe(hold_pipe); +#endif + cout << "EX STAGE ..... OK" << endl; + + mem = new mem_stage("mem_stage"); + mem->in_clk(in_clk); + mem->reset(reset); +#ifdef _MULT_PIPELINE_ + mem->insthold(insthold_W); +#else + mem->insthold(insthold); +#endif + mem->datahold(datahold); + mem->dataread(dataread); + mem->datawrite(datawrite); + mem->dataaddr(dataaddr); + mem->datareq(datareq); + mem->datarw(datarw); + mem->databs(databs); + mem->ex_m_alu(ex_m_alu); + mem->id_ex_m_datastore(id_ex_m_datastore); + mem->id_ex_m_datareq(id_ex_m_datareq); + mem->id_ex_m_datarw(id_ex_m_datarw); + mem->id_ex_m_memtoreg(id_ex_m_memtoreg); + + mem->id_ex_m_byteselect(id_ex_m_byteselect); + mem->id_ex_m_bssign(id_ex_m_bssign); + + mem->id_ex_m_writeregister(id_ex_m_writeregister); + mem->id_ex_m_regwrite(id_ex_m_regwrite); + mem->id_ex_m_wb_writeregister(id_ex_m_wb_writeregister); + mem->id_ex_m_wb_regwrite(id_ex_m_wb_regwrite); + mem->m_id_forward(m_id_forward); + mem->wb_id_forward(wb_id_forward); + + mem->ex_m_IBUS(ex_m_IBUS); + mem->ex_m_inst_addrl(ex_m_inst_addrl); + mem->ex_m_syscall_exception(ex_m_syscall_exception); + mem->ex_m_illegal_instruction(ex_m_illegal_instruction); + mem->ex_m_ovf_excep(ex_m_ovf_excep); + mem->DBUS(DBUS); + mem->data_addrl(data_addrl); + mem->data_addrs(data_addrs); + + mem->m_wb_IBUS(m_wb_IBUS); + mem->m_wb_inst_addrl(m_wb_inst_addrl); + mem->ex_mem_inst(ex_mem_inst); + mem->mem_wb_inst(mem_wb_inst); + mem->m_wb_syscall_exception(m_wb_syscall_exception); + mem->m_wb_illegal_instruction(m_wb_illegal_instruction); + mem->m_wb_ovf_excep(m_wb_ovf_excep); + mem->m_wb_DBUS(m_wb_DBUS); + mem->m_wb_data_addrl(m_wb_data_addrl); + mem->m_wb_data_addrs(m_wb_data_addrs); + + mem->ex_m_instaddr(ex_m_instaddr); + mem->m_wb_instaddr(m_wb_instaddr); + mem->m_wb_dataaddr(m_wb_dataaddr); //aggiunta l'uscita dell indirizzo DATAMEM in caso di page fault + mem->mem_exception(mem_exception); + mem->enable_memstage(enable_memstage); + mem->interrupt_signal(interrupt_signal); + mem->m_wb_interrupt_signal(m_wb_interrupt_signal); + mem->enable_interrupt(enable_interrupt); +#ifdef _MULT_PIPELINE_ + mem->hold_pipe(hold_pipe); +#endif + cout << "MEM STAGE ..... OK" << endl; + +#ifdef _MULT_PIPELINE_ + og1 = new or_gate("or_gate"); + og1->in_A(insthold); + og1->in_B(hold_pipe); + og1->out_gate(insthold_W); +#endif + + enable_stage1 = new enable_stage("enable_stage"); + enable_stage1->enable_pc(enable_pc); + enable_stage1->enable_fetch(enable_fetch); + enable_stage1->enable_decode(enable_decode); + enable_stage1->enable_execute(enable_execute); + enable_stage1->enable_memstage(enable_memstage); + enable_stage1->if_exception(if_exception); + enable_stage1->id_exception(id_exception); + enable_stage1->ex_exception(ex_exception); + enable_stage1->mem_exception(mem_exception); + enable_stage1->wb_exception(wb_exception); + + + writeback_ctrl1 = new writeback_ctrl("writeback_ctrl"); + writeback_ctrl1->m_wb_IBUS(m_wb_IBUS); + writeback_ctrl1->m_wb_inst_addrl(m_wb_inst_addrl); + writeback_ctrl1->m_wb_syscall_exception(m_wb_syscall_exception); + writeback_ctrl1->m_wb_illegal_instruction(m_wb_illegal_instruction); + writeback_ctrl1->m_wb_ovf_excep(m_wb_ovf_excep); + writeback_ctrl1->m_wb_DBUS(m_wb_DBUS); + writeback_ctrl1->m_wb_data_addrl(m_wb_data_addrl); + writeback_ctrl1->m_wb_data_addrs(m_wb_data_addrs); + writeback_ctrl1->wb_exception(wb_exception); + writeback_ctrl1->m_wb_interrupt_signal(m_wb_interrupt_signal); + + mux_instaddr1 = new mux_instaddr("mux_instaddr"); + mux_instaddr1->m_wb_instaddr(m_wb_instaddr); + mux_instaddr1->ex_m_instaddr(ex_m_instaddr); + mux_instaddr1->m_wb_instaddr_s(m_wb_instaddr_s); + mux_instaddr1->ex_mem_inst(mem_wb_inst); + mux_instaddr1->m_wb_interrupt_signal(m_wb_interrupt_signal); +} Index: tags/arelease/source/cpu/enable_stage.h =================================================================== --- tags/arelease/source/cpu/enable_stage.h (nonexistent) +++ tags/arelease/source/cpu/enable_stage.h (revision 13) @@ -0,0 +1,27 @@ +#include "systemc.h" +#include "../constants/constants.h" + +SC_MODULE(enable_stage) +{ + sc_in if_exception; + sc_in id_exception; + sc_in ex_exception; + sc_in mem_exception; + sc_in wb_exception; + + sc_out enable_pc; + sc_out enable_fetch; + sc_out enable_decode; + sc_out enable_execute; + sc_out enable_memstage; + + void do_enable_stage(); + + SC_CTOR(enable_stage) + { + SC_METHOD(do_enable_stage); + sensitive << if_exception << id_exception; + sensitive << ex_exception << mem_exception; + sensitive << wb_exception ; + } +}; Index: tags/arelease/source/cpu/ex_stage/mux_hi.h =================================================================== --- tags/arelease/source/cpu/ex_stage/mux_hi.h (nonexistent) +++ tags/arelease/source/cpu/ex_stage/mux_hi.h (revision 13) @@ -0,0 +1,18 @@ +#include "systemc.h" +#include "../../constants/constants.h" + +SC_MODULE(mux_hi) +{ + sc_in > hi; + sc_in > rs; + sc_in > id_ex_alu_ctrl; + sc_out > out; + + void do_mux_hi(); + + SC_CTOR(mux_hi) + { + SC_METHOD(do_mux_hi); + sensitive << hi << rs << id_ex_alu_ctrl; + } +}; Index: tags/arelease/source/cpu/ex_stage/mux_rd.cpp =================================================================== --- tags/arelease/source/cpu/ex_stage/mux_rd.cpp (nonexistent) +++ tags/arelease/source/cpu/ex_stage/mux_rd.cpp (revision 13) @@ -0,0 +1,21 @@ +#include "mux_rd.h" + +void mux_rd::do_mux_rd() +{ + if (id_ex_alu_ctrl.read() == FUNC_MFLO) + { + out_ex_alu_s.write(out_lo.read()); + out_ex_id_forward_s.write(out_lo.read()); + } + else + if (id_ex_alu_ctrl.read() == FUNC_MFHI) + { + out_ex_alu_s.write(out_hi.read()); + out_ex_id_forward_s.write(out_hi.read()); + } + else + { + out_ex_alu_s.write(in_ex_alu_s.read()); + out_ex_id_forward_s.write(in_ex_id_forward_s.read()); + } +} Index: tags/arelease/source/cpu/ex_stage/mux_lo.cpp =================================================================== --- tags/arelease/source/cpu/ex_stage/mux_lo.cpp (nonexistent) +++ tags/arelease/source/cpu/ex_stage/mux_lo.cpp (revision 13) @@ -0,0 +1,9 @@ +#include "mux_lo.h" + +void mux_lo::do_mux_lo() +{ + if (id_ex_alu_ctrl.read() == FUNC_MTLN) + out.write(rs.read()); + else + out.write(lo.read()); +} Index: tags/arelease/source/cpu/ex_stage/mux_rd.h =================================================================== --- tags/arelease/source/cpu/ex_stage/mux_rd.h (nonexistent) +++ tags/arelease/source/cpu/ex_stage/mux_rd.h (revision 13) @@ -0,0 +1,21 @@ +#include "systemc.h" +#include "../../constants/constants.h" + +SC_MODULE(mux_rd) +{ + sc_in > out_lo; + sc_in > out_hi; + sc_in > in_ex_id_forward_s; + sc_in > in_ex_alu_s; + sc_in > id_ex_alu_ctrl; + sc_out > out_ex_id_forward_s; + sc_out > out_ex_alu_s; + + void do_mux_rd(); + + SC_CTOR(mux_rd) + { + SC_METHOD(do_mux_rd); + sensitive << out_lo << out_hi << id_ex_alu_ctrl << in_ex_id_forward_s << in_ex_alu_s; + } +} ; Index: tags/arelease/source/cpu/ex_stage/mux_lo.h =================================================================== --- tags/arelease/source/cpu/ex_stage/mux_lo.h (nonexistent) +++ tags/arelease/source/cpu/ex_stage/mux_lo.h (revision 13) @@ -0,0 +1,18 @@ +#include "systemc.h" +#include "../../constants/constants.h" + +SC_MODULE(mux_lo) +{ + sc_in > lo; + sc_in > rs; + sc_in > id_ex_alu_ctrl; + sc_out > out; + + void do_mux_lo(); + + SC_CTOR(mux_lo) + { + SC_METHOD(do_mux_lo); + sensitive << lo << rs << id_ex_alu_ctrl; + } +} ; Index: tags/arelease/source/cpu/ex_stage/reg_ex.cpp =================================================================== --- tags/arelease/source/cpu/ex_stage/reg_ex.cpp (nonexistent) +++ tags/arelease/source/cpu/ex_stage/reg_ex.cpp (revision 13) @@ -0,0 +1,96 @@ +#include "reg_ex.h" + +void reg_ex::do_reg_ex() +{ + if(reset.read() == true) + { + ex_m_alu.write(WORD_ZERO); + id_ex_m_datastore.write(WORD_ZERO); + + id_ex_m_datareq.write(SC_LOGIC_0); + id_ex_m_datarw.write(SC_LOGIC_0); + + id_ex_m_memtoreg.write(SC_LOGIC_0); + id_ex_m_writeregister.write("00000"); + id_ex_m_regwrite.write(SC_LOGIC_0); + + id_ex_m_byteselect.write("00"); + id_ex_m_bssign.write(SC_LOGIC_0); + + out_lo.write(WORD_ZERO); + out_hi.write(WORD_ZERO); + + // PIPELINED EXCEPTION SIGNALS + ex_m_IBUS.write(SC_LOGIC_0); + ex_m_inst_addrl.write(SC_LOGIC_0); + ex_mem_inst.write(WORD_ZERO); + ex_m_syscall_exception.write(SC_LOGIC_0); + ex_m_illegal_instruction.write(SC_LOGIC_0); + ex_m_ovf_excep.write(SC_LOGIC_0); + ex_m_instaddr.write(0); + + } + else + if((datahold.read() == false) && (insthold.read() == false) && (enable_execute.read() == SC_LOGIC_1)) + { + ex_m_alu.write(ex_alu_s.read()); + id_ex_m_datastore.write(id_ex_datastore.read()); + id_ex_m_datarw.write(id_ex_datarw.read()); + id_ex_m_memtoreg.write(id_ex_memtoreg.read()); + id_ex_m_writeregister.write(id_ex_writeregister_out.read()); + + id_ex_m_byteselect.write(id_ex_byteselect.read()); + id_ex_m_bssign.write(id_ex_bssign.read()); + + out_lo.write(in_lo.read()); + out_hi.write(in_hi.read()); + + ex_m_IBUS.write(id_ex_IBUS.read()); + ex_m_inst_addrl.write(id_ex_inst_addrl.read()); + ex_mem_inst.write(id_ex_inst.read()); + ex_m_syscall_exception.write(id_ex_syscall_exception.read()); + ex_m_illegal_instruction.write(id_ex_illegal_instruction.read()); + ex_m_ovf_excep.write(ovf_excep.read()); + ex_m_instaddr.write(id_ex_instaddr.read()); + // Address Error Exception + if (addr_err.read() == SC_LOGIC_1) + { + #ifdef _DEBUG_ + cout << " ***************** Address Error Exception ****************** " << endl; + #endif + id_ex_m_datareq.write(SC_LOGIC_0); // NB! No read/write + id_ex_m_regwrite.write(SC_LOGIC_0); // NB! No register write + } + else + { + id_ex_m_datareq.write(id_ex_datareq.read()); + id_ex_m_regwrite.write(id_ex_regwrite_out.read()); + } + + } + else + if((datahold.read() == false) && (insthold.read() == false) && (enable_execute.read() == SC_LOGIC_0)) + { + ex_m_alu.write(WORD_ZERO); + id_ex_m_datastore.write(WORD_ZERO); + id_ex_m_datareq.write(SC_LOGIC_0); + id_ex_m_datarw.write(SC_LOGIC_0); + id_ex_m_memtoreg.write(SC_LOGIC_0); + id_ex_m_writeregister.write("00000"); + id_ex_m_regwrite.write(SC_LOGIC_0); + id_ex_m_byteselect.write("00"); + id_ex_m_bssign.write(SC_LOGIC_0); + out_lo.write(WORD_ZERO); + out_hi.write(WORD_ZERO); + + ex_m_IBUS.write(id_ex_IBUS.read()); + ex_m_inst_addrl.write(id_ex_inst_addrl.read()); + ex_mem_inst.write(id_ex_inst.read()); + ex_m_syscall_exception.write(id_ex_syscall_exception.read()); + ex_m_illegal_instruction.write(id_ex_illegal_instruction.read()); + ex_m_ovf_excep.write(ovf_excep.read()); + ex_m_instaddr.write(id_ex_instaddr.read()); + } + else; + +} Index: tags/arelease/source/cpu/ex_stage/backwrite.cpp =================================================================== --- tags/arelease/source/cpu/ex_stage/backwrite.cpp (nonexistent) +++ tags/arelease/source/cpu/ex_stage/backwrite.cpp (revision 13) @@ -0,0 +1,6 @@ +#include "backwrite.h" + +void backwrite::do_backwrite() +{ + ex_id_forward.write(ex_id_forward_s.read()); +} Index: tags/arelease/source/cpu/ex_stage/reg_ex.h =================================================================== --- tags/arelease/source/cpu/ex_stage/reg_ex.h (nonexistent) +++ tags/arelease/source/cpu/ex_stage/reg_ex.h (revision 13) @@ -0,0 +1,74 @@ +#include "systemc.h" +#include "../../constants/config.h" +#include "../../constants/constants.h" + +SC_MODULE(reg_ex) +{ + sc_in in_clk; + sc_in reset; + sc_in insthold; + sc_in datahold; + + sc_in addr_err; + + sc_in > ex_alu_s; + sc_out > ex_m_alu; + + sc_in > id_ex_datastore; + sc_out > id_ex_m_datastore; + + sc_in id_ex_datareq; + sc_out id_ex_m_datareq; + + sc_in id_ex_datarw; + sc_out id_ex_m_datarw; + + sc_in id_ex_memtoreg; + sc_out id_ex_m_memtoreg; + + sc_in > id_ex_writeregister_out; + sc_out > id_ex_m_writeregister; + + sc_in id_ex_regwrite_out; + sc_out id_ex_m_regwrite; + + sc_in > id_ex_byteselect; + sc_out > id_ex_m_byteselect; + + sc_in id_ex_bssign; + sc_out id_ex_m_bssign; + + sc_in > in_lo; + sc_out > out_lo; + + sc_in > in_hi; + sc_out > out_hi; + + sc_in id_ex_IBUS; + sc_in id_ex_inst_addrl; + + sc_in > id_ex_inst; // instruction coming from ID_STAGE + sc_out > ex_mem_inst; // instruction to MEM_STAGE + + sc_in id_ex_syscall_exception; + sc_in id_ex_illegal_instruction; + sc_in ovf_excep; + sc_out ex_m_IBUS; + sc_out ex_m_inst_addrl; + sc_out ex_m_syscall_exception; + sc_out ex_m_illegal_instruction; + sc_out ex_m_ovf_excep; + + sc_in > id_ex_instaddr; + sc_out > ex_m_instaddr; + + sc_in enable_execute; + + void do_reg_ex(); + + SC_CTOR(reg_ex) + { + SC_METHOD(do_reg_ex); + sensitive_pos << in_clk; + }; +}; Index: tags/arelease/source/cpu/ex_stage/multiply.cpp =================================================================== --- tags/arelease/source/cpu/ex_stage/multiply.cpp (nonexistent) +++ tags/arelease/source/cpu/ex_stage/multiply.cpp (revision 13) @@ -0,0 +1,116 @@ +//multiply.cpp +#include "multiply.h" + +void multiply::do_multiply() +{ + sc_lv<32> rs = id_ex_alu1.read(); + sc_lv<32> rt = id_ex_alu2.read(); + sc_lv<6> func = id_ex_alu_function.read(); + sc_lv<6> opcode = id_ex_alu_opcode.read(); + + if((func == FUNC_MULT) && (opcode == OP_RFORMAT)) + { + + sc_int<32> irs,irt; + irs = rs; + irt = rt; + stage0.write(irs*irt); + + } + else + if((func == FUNC_MULTU) && (opcode == OP_RFORMAT)) + { + sc_uint<32> irs,irt; + irs = rs; + irt = rt; + stage0.write(irs*irt); + } + else + { + stage0.write(DOUBLE_ZERO); + } +} + + +#ifdef _MULT_PIPELINE_ +void multiply::do_pipe() +{ + #if(DEPTH_MULT_PIPE == 1) + if (reset.read()== true) + stage1.write(DOUBLE_ZERO); + else + stage1.write(stage0); + #else + #if(DEPTH_MULT_PIPE == 2) + if (reset.read()== true) + { + stage1.write(DOUBLE_ZERO); + stage2.write(DOUBLE_ZERO); + } + else + { + stage1.write(stage0); + stage2.write(stage1); + } + #else + #if(DEPTH_MULT_PIPE == 3) + if (reset.read()== true) + { + stage1.write(DOUBLE_ZERO); + stage2.write(DOUBLE_ZERO); + stage3.write(DOUBLE_ZERO); + } + else + { + stage1.write(stage0); + stage2.write(stage1); + stage3.write(stage2); + } + #else + #if(DEPTH_MULT_PIPE == 4) + if (reset.read()== true) + { + stage1.write(DOUBLE_ZERO); + stage2.write(DOUBLE_ZERO); + stage3.write(DOUBLE_ZERO); + stage4.write(DOUBLE_ZERO); + } + else + { + stage1.write(stage0); + stage2.write(stage1); + stage3.write(stage2); + stage4.write(stage3); + } + #endif + #endif + #endif + #endif +} +#endif +void multiply::split() +{ + sc_lv<64> temp; + #ifndef _MULT_PIPELINE_ + temp = stage0; + #else + #if(DEPTH_MULT_PIPE == 1) + temp = stage1; + #else + #if(DEPTH_MULT_PIPE == 2) + temp = stage2; + #else + #if(DEPTH_MULT_PIPE == 3) + temp = stage3; + #else + #if(DEPTH_MULT_PIPE == 4) + temp = stage4; + #endif + #endif + #endif + #endif + #endif + + hi.write(temp.range(63,32)); + lo.write(temp.range(31,0)); +} Index: tags/arelease/source/cpu/ex_stage/backwrite.h =================================================================== --- tags/arelease/source/cpu/ex_stage/backwrite.h (nonexistent) +++ tags/arelease/source/cpu/ex_stage/backwrite.h (revision 13) @@ -0,0 +1,16 @@ +#include "systemc.h" +// modulo completamente inutile!!! + +SC_MODULE(backwrite) +{ + sc_in > ex_id_forward_s; + sc_out > ex_id_forward; + + void do_backwrite(); + + SC_CTOR(backwrite) + { + SC_METHOD(do_backwrite); + sensitive << ex_id_forward_s; + } +}; Index: tags/arelease/source/cpu/ex_stage/alu.cpp =================================================================== --- tags/arelease/source/cpu/ex_stage/alu.cpp (nonexistent) +++ tags/arelease/source/cpu/ex_stage/alu.cpp (revision 13) @@ -0,0 +1,176 @@ +// +// HO MODIFICATO la funzione SLLV e SRLV +// ed ho aggiunto i segnali temp_rs e shift_rs +// + + +#include "alu.h" + +void alu::do_alu() +{ + sc_lv<6> func = id_ex_alu_ctrl.read(); + sc_lv<32> rs = id_ex_alu1.read(); + sc_lv<32> rt = id_ex_alu2.read(); + sc_lv<32> rd = WORD_ZERO; + sc_int<32> irs = rs; + sc_int<32> irt = rt; + sc_uint<32> uirs = rs; + sc_uint<32> uirt = rt; + sc_logic equal = id_ex_equal.read(); + sc_logic ovf_excep_l; + + sc_logic sign_bit_for_sra; + + // shift amount + sc_lv<5> sa = id_ex_alu_sa.read(); + sc_uint<5> uisa = sa; + + // shift from the register rs + sc_lv<5> temp_rs = rs.range(4,0); + sc_uint<5> shift_rs = temp_rs; + + sc_logic n0, n1; + n0 = 0; + n1 = 1; + + // Defaults... + ovf_excep.write(n0); // ovf_excep_l = 0; + carry.write(n0); + + if(func == FUNC_SLL) + { + rd = rt << uisa; + } + else if(func == FUNC_SRL) + { + rd = rt >> uisa; + } + else if(func == FUNC_SRA) + { + sign_bit_for_sra = rt[31]; + rd = rt >> uisa; + } + else if(func == FUNC_SLLV) + { + rd = rt << shift_rs; + } + else if(func == FUNC_SRLV) + { + rd = rt >> shift_rs; + } + else if(func == FUNC_SRAV) + { + } + /*else if(func == FUNC_MFHI) + { + rd = hi; + } + + else if(func == FUNC_MFLO) + { + rd = lo; + }*/ + + else if(func == FUNC_ADD) + { + sc_lv<33> temp; + sc_lv<32> t = rt, s = rs; + sc_lv<33> tt, ss; + sc_int<33> ttt, sss; + // Sign extend t + if(t[31] == '1') + ttt = tt = ("1",t); + else + ttt = tt = ("0",t); + // Sign extend s + if(s[31] == '1') + sss = ss = ("1",s); + else + sss = ss = ("0",s); + temp = ttt + sss; + + // Set exception bit + if (temp[32] != temp[31]) + ovf_excep.write(SC_LOGIC_1); + else + ovf_excep.write(SC_LOGIC_0); + rd = temp.range(31,0); + } + else if(func == FUNC_ADDU) + { + rd = uirs + uirt; + } + else if(func == FUNC_SUB) + { + sc_lv<33> temp; + sc_lv<32> t = rt, s = rs; + sc_lv<33> tt, ss; + sc_int<33> ttt, sss; + // Sign extend t + if(t[31] == '1') + ttt = tt = ("1",t); + else + ttt = tt = ("0",t); + // Sign extend s + if(s[31] == '1') + sss = ss = ("1",s); + else + sss = ss = ("0",s); + temp = ttt + sss; + + // Set exception bit + if (temp[32] != temp[31]) + ovf_excep.write(SC_LOGIC_1); + else + ovf_excep.write(SC_LOGIC_0); + rd = temp.range(31,0); + } + else if(func == FUNC_SUBU) + { + rd = irs - irt; + } + else if(func == FUNC_AND) + { + rd = rs & rt; + } + else if(func == FUNC_OR) + { + rd = rs | rt; + } + else if(func == FUNC_XOR) + { + rd = rs ^ rt; + } + else if(func == FUNC_NOR) + { + rd = ~(rs|rt); + } + else if(func == FUNC_SLT) + if(irs < irt) + { + rd = WORD_CON_ONE; + } + else + { + rd = WORD_ZERO; + } + else if(func == FUNC_SLTU) + if(uirs < uirt) + { + rd = WORD_CON_ONE; + } + else + { + rd = WORD_ZERO; + } + else + { + rd = WORD_ZERO; + } + + ex_alu_s.write(rd); + ex_id_forward_s.write(rd); + + + +} Index: tags/arelease/source/cpu/ex_stage/multiply.h =================================================================== --- tags/arelease/source/cpu/ex_stage/multiply.h (nonexistent) +++ tags/arelease/source/cpu/ex_stage/multiply.h (revision 13) @@ -0,0 +1,87 @@ +#include "systemc.h" +#include "../../constants/constants.h" +#include "../../constants/config.h" + +SC_MODULE(multiply) +{ + sc_in in_clk; + sc_in reset; + +#ifdef _MULT_PIPELINE_ + sc_in ready; +#endif + + sc_signal > stage0; + +#ifdef _MULT_PIPELINE_ + #if(DEPTH_MULT_PIPE == 1) + sc_signal > stage1; + #else + #if(DEPTH_MULT_PIPE == 2) + sc_signal > stage1, stage2; + #else + #if(DEPTH_MULT_PIPE == 3) + sc_signal > stage1, stage2, stage3; + #else + #if(DEPTH_MULT_PIPE == 4) + sc_signal > stage1, stage2, stage3, stage4; + #else + cout << "Out Of Bound! Check DEPTH_MULT_PIPE in config.h!" << endl; + sc_stop(); + #endif + #endif + #endif + #endif +#endif + sc_in > id_ex_alu1; + sc_in > id_ex_alu2; + sc_in > id_ex_alu_function; + sc_in > id_ex_alu_opcode; + + sc_out > hi; + sc_out > lo; + + void do_multiply(); + + void split(); +#ifdef _MULT_PIPELINE_ + void do_pipe(); +#endif + +SC_CTOR(multiply) +{ + + SC_METHOD(do_multiply); + sensitive << id_ex_alu1; + sensitive << id_ex_alu2; + sensitive << id_ex_alu_function; + sensitive << id_ex_alu_opcode; +#ifdef _MULT_PIPELINE_ + SC_METHOD(do_pipe); + sensitive_pos << in_clk; +#endif + SC_METHOD(split); + #ifndef _MULT_PIPELINE_ + sensitive << stage0; + #endif + #ifdef _MULT_PIPELINE_ + #if(DEPTH_MULT_PIPE == 1) + sensitive << stage1; + #else + #if(DEPTH_MULT_PIPE == 2) + sensitive << stage2; + #else + #if(DEPTH_MULT_PIPE == 3) + sensitive << stage3; + #else + #if(DEPTH_MULT_PIPE == 4) + sensitive << stage4; + #else + cout << "Out Of Bound! Check DEPTH_MULT_PIPE in config.h!" << endl; + #endif + #endif + #endif + #endif + #endif + } +}; Index: tags/arelease/source/cpu/ex_stage/fsm.cpp =================================================================== --- tags/arelease/source/cpu/ex_stage/fsm.cpp (nonexistent) +++ tags/arelease/source/cpu/ex_stage/fsm.cpp (revision 13) @@ -0,0 +1,101 @@ +//fsm.cpp +#include "fsm.h" +void fsm::update_state() +{ + + if (reset.read() == true) + current_state = IDLE; + else + current_state = next_state; +} + +void fsm::do_logic() +{ + sc_lv<6> func = id_ex_alu_function.read(); + sc_lv<6> opcode = id_ex_alu_opcode.read(); + + switch(current_state) { + case IDLE: + { + if(((func == FUNC_MULT) || (func == FUNC_MULTU)) && (opcode == OP_RFORMAT)) + { + ready.write(false); + hold_pipe.write(true); + next_state = STAGE1; + cout << " STARTING MULTIPLY" << endl; + } + else + { + ready.write(false); + hold_pipe.write(false); + next_state = IDLE; + } + } + break; + + case STAGE1: + { + #if(DEPTH_MULT_PIPE == 1) + ready.write(true); + hold_pipe.write(false); + next_state = IDLE; + #else + ready.write(false); + hold_pipe.write(true); + next_state = STAGE2; + #endif + } + break; + + case STAGE2: + { + #if(DEPTH_MULT_PIPE == 2) + ready.write(true); + hold_pipe.write(false); + next_state = IDLE; + #else + ready.write(false); + hold_pipe.write(true); + next_state = STAGE3; + #endif + } + break; + + case STAGE3: + { + #if(DEPTH_MULT_PIPE == 3) + ready.write(true); + hold_pipe.write(false); + next_state = IDLE; + #else + ready.write(false); + hold_pipe.write(true); + next_state = STAGE4; + #endif + } + break; + + case STAGE4: + { + #if(DEPTH_MULT_PIPE == 4) + ready.write(true); + hold_pipe.write(false); + next_state = IDLE; + #else + ready.write(false); + hold_pipe.write(false); + cout << " ERROR: PIPELINE DEPTH OUT OF RANGE" << endl; + next_state = IDLE; + #endif + } + break; + + default: + { + ready.write(false); + hold_pipe.write(false); + next_state = IDLE; + } + break; + } +} Index: tags/arelease/source/cpu/ex_stage/alu.h =================================================================== --- tags/arelease/source/cpu/ex_stage/alu.h (nonexistent) +++ tags/arelease/source/cpu/ex_stage/alu.h (revision 13) @@ -0,0 +1,26 @@ +#include "systemc.h" +#include "../../constants/config.h" +#include "../../constants/constants.h" + +SC_MODULE(alu) +{ + sc_in > id_ex_alu1; + sc_in > id_ex_alu2; + sc_in > id_ex_alu_ctrl; + sc_in id_ex_equal; + sc_in > id_ex_alu_sa; + sc_out ovf_excep; + sc_out carry; + sc_out > ex_alu_s; + sc_out > ex_id_forward_s; + + void do_alu(); + + SC_CTOR(alu) + { + SC_METHOD(do_alu); + sensitive << id_ex_equal << id_ex_alu_ctrl; + sensitive << id_ex_alu1 << id_ex_alu2; + sensitive << id_ex_alu_sa; + } +}; Index: tags/arelease/source/cpu/ex_stage/execute_ctrl.cpp =================================================================== --- tags/arelease/source/cpu/ex_stage/execute_ctrl.cpp (nonexistent) +++ tags/arelease/source/cpu/ex_stage/execute_ctrl.cpp (revision 13) @@ -0,0 +1,14 @@ +#include "execute_ctrl.h" + +void execute_ctrl::do_execute_ctrl() +{ + if((id_ex_IBUS.read() == SC_LOGIC_1) || + (id_ex_inst_addrl.read() == SC_LOGIC_1) || + (id_ex_syscall_exception.read() == SC_LOGIC_1) || + (id_ex_illegal_instruction.read() == SC_LOGIC_1) || + (ovf_excep.read() == SC_LOGIC_1)) + ex_exception.write(SC_LOGIC_1); + else + ex_exception.write(SC_LOGIC_0); + +}; Index: tags/arelease/source/cpu/ex_stage/mux_hi.cpp =================================================================== --- tags/arelease/source/cpu/ex_stage/mux_hi.cpp (nonexistent) +++ tags/arelease/source/cpu/ex_stage/mux_hi.cpp (revision 13) @@ -0,0 +1,9 @@ +#include "mux_hi.h" + +void mux_hi::do_mux_hi() +{ + if (id_ex_alu_ctrl.read() == FUNC_MTHI) + out.write(rs.read()); + else + out.write(hi.read()); +} Index: tags/arelease/source/cpu/ex_stage/fsm.h =================================================================== --- tags/arelease/source/cpu/ex_stage/fsm.h (nonexistent) +++ tags/arelease/source/cpu/ex_stage/fsm.h (revision 13) @@ -0,0 +1,32 @@ + //fsm.h +#include "systemc.h" +#include "../../constants/constants.h" +#include "../../constants/config.h" + +enum state {IDLE, STAGE1, STAGE2, STAGE3, STAGE4}; + +SC_MODULE(fsm) +{ + sc_in in_clk; + sc_in reset; + sc_in > id_ex_alu_function; + sc_in > id_ex_alu_opcode; + sc_out ready; + sc_out hold_pipe; + + sc_signal current_state ,next_state; + + void update_state(); + void do_logic(); + + SC_CTOR(fsm) + { + SC_METHOD(update_state); + sensitive_pos << in_clk; + + SC_METHOD(do_logic); + sensitive << id_ex_alu_function; + sensitive << id_ex_alu_opcode; + sensitive << current_state; + } +}; Index: tags/arelease/source/cpu/ex_stage/execute_ctrl.h =================================================================== --- tags/arelease/source/cpu/ex_stage/execute_ctrl.h (nonexistent) +++ tags/arelease/source/cpu/ex_stage/execute_ctrl.h (revision 13) @@ -0,0 +1,22 @@ +#include "systemc.h" +#include "../../constants/constants.h" + +SC_MODULE(execute_ctrl) +{ + sc_in id_ex_IBUS; + sc_in id_ex_inst_addrl; + sc_in id_ex_illegal_instruction; + sc_in id_ex_syscall_exception; + sc_in ovf_excep; + sc_out ex_exception; + + void do_execute_ctrl(); + + SC_CTOR(execute_ctrl) + { + SC_METHOD(do_execute_ctrl); + sensitive << id_ex_IBUS << id_ex_inst_addrl; + sensitive << id_ex_illegal_instruction << id_ex_syscall_exception; + sensitive << ovf_excep; + } +}; Index: tags/arelease/source/cpu/id_stage.cpp =================================================================== --- tags/arelease/source/cpu/id_stage.cpp (nonexistent) +++ tags/arelease/source/cpu/id_stage.cpp (revision 13) @@ -0,0 +1 @@ +#include "id_stage.h" Index: tags/arelease/source/cpu/mem_stage/reg_mem.h =================================================================== --- tags/arelease/source/cpu/mem_stage/reg_mem.h (nonexistent) +++ tags/arelease/source/cpu/mem_stage/reg_mem.h (revision 13) @@ -0,0 +1,61 @@ +#include "systemc.h" +#include "../../constants/constants.h" + +SC_MODULE(reg_mem) +{ + sc_in in_clk; + sc_in reset; + + sc_in insthold; + sc_in datahold; + + sc_out > wb_id_forward; + sc_out > id_ex_m_wb_writeregister; + sc_out id_ex_m_wb_regwrite; + sc_in > id_store; + sc_in > id_ex_m_writeregister; + sc_in id_ex_m_regwrite; + + // EXCEPTION SIGNALS + sc_in ex_m_IBUS; + sc_in ex_m_inst_addrl; + sc_in ex_m_syscall_exception; + sc_in ex_m_illegal_instruction; + sc_in ex_m_ovf_excep; + sc_in DBUS; + sc_in data_addrl; + sc_in data_addrs; + + // exception status vector -> to CPO-Cause + sc_out m_wb_IBUS; + sc_out m_wb_inst_addrl; + sc_out m_wb_syscall_exception; + sc_out m_wb_illegal_instruction; + sc_out m_wb_ovf_excep; + sc_out m_wb_DBUS; + sc_out m_wb_data_addrl; + sc_out m_wb_data_addrs; + + sc_out > m_wb_instaddr; //se un bit dell ESV �pari ad 1 allora questo �l'indirizzo della vittima + sc_in > ex_m_instaddr; + sc_in > ex_m_dataaddr; + sc_out > m_wb_dataaddr; + + + sc_in > ex_mem_inst; // instruction coming from EX_STAGE + sc_out > mem_wb_inst; // instruction to WRITE_BACK Phases + + + sc_in interrupt_signal; + sc_out m_wb_interrupt_signal; + + sc_in enable_memstage; + + void do_reg_mem(); + + SC_CTOR(reg_mem) + { + SC_METHOD(do_reg_mem); + sensitive_pos << in_clk; + } +}; Index: tags/arelease/source/cpu/mem_stage/flag_interr.h =================================================================== --- tags/arelease/source/cpu/mem_stage/flag_interr.h (nonexistent) +++ tags/arelease/source/cpu/mem_stage/flag_interr.h (revision 13) @@ -0,0 +1,25 @@ +#include "systemc.h" + +enum FSM_STATE {Idle, State1}; + +SC_MODULE(flag_interr) +{ + sc_in in_clk, reset; + sc_in interrupt_in; + sc_out interrupt_out; + + sc_signal current_state, next_state; + + void do_fsm_update(); + void do_fsm_ctrl(); + + SC_CTOR(flag_interr) + { + SC_METHOD(do_fsm_update); + sensitive_pos << in_clk; + + SC_METHOD(do_fsm_ctrl); + sensitive << reset << in_clk; + sensitive << current_state; + } +}; Index: tags/arelease/source/cpu/mem_stage/select_mem.h =================================================================== --- tags/arelease/source/cpu/mem_stage/select_mem.h (nonexistent) +++ tags/arelease/source/cpu/mem_stage/select_mem.h (revision 13) @@ -0,0 +1,29 @@ +//! Selects inputs to the data memory + +#include "systemc.h" +#include "../../constants/constants.h" + +SC_MODULE(select_mem) +{ + sc_in id_ex_m_datareq; + sc_in id_ex_m_datarw; + sc_in > id_ex_m_byteselect; + sc_in > id_ex_m_datastore; + sc_out > datawrite; + sc_in > ex_m_alu; + sc_out > dataaddr; + sc_out datareq; + sc_out datarw; + sc_out > databs; + sc_in enable_memstage; + + void do_select_mem(); + + SC_CTOR(select_mem) + { + SC_METHOD(do_select_mem); + sensitive << id_ex_m_datareq << id_ex_m_datarw << id_ex_m_datastore; + sensitive << ex_m_alu << id_ex_m_byteselect << enable_memstage; + //sensitive << datawrite; + } +}; Index: tags/arelease/source/cpu/mem_stage/mux_interrupt.cpp =================================================================== --- tags/arelease/source/cpu/mem_stage/mux_interrupt.cpp (nonexistent) +++ tags/arelease/source/cpu/mem_stage/mux_interrupt.cpp (revision 13) @@ -0,0 +1,21 @@ +#include "mux_interrupt.h" + +void mux_interrupt::do_mux_interrupt() +{ + #ifdef _MULT_PIPELINE_ + if(hold_pipe.read() == 0) + { + if(SEL.read() == SC_LOGIC_1) + OUT.write(IN_A.read()); + else + OUT.write(IN_B.read()); + } + else + OUT.write(IN_B.read()); + #else + if(SEL.read() == SC_LOGIC_1) + OUT.write(IN_A.read()); + else + OUT.write(IN_B.read()); + #endif +} Index: tags/arelease/source/cpu/mem_stage/.reg_mem.h.swp =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: tags/arelease/source/cpu/mem_stage/.reg_mem.h.swp =================================================================== --- tags/arelease/source/cpu/mem_stage/.reg_mem.h.swp (nonexistent) +++ tags/arelease/source/cpu/mem_stage/.reg_mem.h.swp (revision 13)
tags/arelease/source/cpu/mem_stage/.reg_mem.h.swp Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: tags/arelease/source/cpu/mem_stage/memstage_ctrl.cpp =================================================================== --- tags/arelease/source/cpu/mem_stage/memstage_ctrl.cpp (nonexistent) +++ tags/arelease/source/cpu/mem_stage/memstage_ctrl.cpp (revision 13) @@ -0,0 +1,18 @@ +#include "memstage_ctrl.h" + +void memstage_ctrl::do_memstage_ctrl() +{ + if((ex_m_IBUS.read() == SC_LOGIC_1) || + (ex_m_inst_addrl.read() == SC_LOGIC_1) || + (ex_m_syscall_exception.read() == SC_LOGIC_1) || + (ex_m_illegal_instruction.read() == SC_LOGIC_1) || + (ex_m_ovf_excep.read() == SC_LOGIC_1) || + (DBUS.read() == SC_LOGIC_1) || + (data_addrl.read() == SC_LOGIC_1) || + (data_addrs.read() == SC_LOGIC_1) || + (interrupt_signal.read() == SC_LOGIC_1)) + mem_exception.write(SC_LOGIC_1); + else + mem_exception.write(SC_LOGIC_0); + +}; Index: tags/arelease/source/cpu/mem_stage/multiplexer_mem.cpp =================================================================== --- tags/arelease/source/cpu/mem_stage/multiplexer_mem.cpp (nonexistent) +++ tags/arelease/source/cpu/mem_stage/multiplexer_mem.cpp (revision 13) @@ -0,0 +1,38 @@ +//! Selects whether to bypass data memory or not +/*! + When reading from memory, the data signal from data memory is chosen + sensitive << id_ex_m_memtoreg << ex_m_alu << dataread; + */ + + #include "multiplexer_mem.h" + + void multiplexer_mem::do_multiplexer_mem() + { + sc_lv<32> store; + sc_lv<2> byteselect = id_ex_m_byteselect.read(); + sc_logic bssign = id_ex_m_bssign.read(); + if (id_ex_m_memtoreg.read() == SC_LOGIC_0) + { + store = ex_m_alu.read(); + } + else + { + store = dataread.read(); + if (byteselect == "01") + { + store = store & "00000000000000000000000011111111"; + if ((store.range(7,7) == "1") && (bssign == SC_LOGIC_1)) + store = store | "11111111111111111111111100000000"; + } + else if (byteselect == "10") + { + store = store & "00000000000000001111111111111111"; + if ((store.range(15,15) == "1") && (bssign == SC_LOGIC_1)) + store = store | "11111111111111110000000000000000"; + } + + } + + id_store.write(store); + m_id_forward.write(store); + } Index: tags/arelease/source/cpu/mem_stage/mux_interrupt.h =================================================================== --- tags/arelease/source/cpu/mem_stage/mux_interrupt.h (nonexistent) +++ tags/arelease/source/cpu/mem_stage/mux_interrupt.h (revision 13) @@ -0,0 +1,27 @@ +#include "systemc.h" +#include "../../constants/constants.h" + +SC_MODULE(mux_interrupt) +{ + sc_in IN_A; + sc_in IN_B; + +#ifdef _MULT_PIPELINE_ + sc_in hold_pipe; +#endif + + sc_in SEL; + sc_out OUT; + + + void do_mux_interrupt(); + + SC_CTOR(mux_interrupt) + { + SC_METHOD(do_mux_interrupt); + sensitive << IN_A << IN_B << SEL; + #ifdef _MULT_PIPELINE_ + sensitive << hold_pipe; + #endif + } +}; Index: tags/arelease/source/cpu/mem_stage/memstage_ctrl.h =================================================================== --- tags/arelease/source/cpu/mem_stage/memstage_ctrl.h (nonexistent) +++ tags/arelease/source/cpu/mem_stage/memstage_ctrl.h (revision 13) @@ -0,0 +1,27 @@ +#include "systemc.h" +#include "../../constants/constants.h" + +SC_MODULE(memstage_ctrl) +{ + sc_in ex_m_IBUS; + sc_in ex_m_inst_addrl; + sc_in ex_m_illegal_instruction; + sc_in ex_m_syscall_exception; + sc_in ex_m_ovf_excep; + sc_in DBUS; + sc_in data_addrl; + sc_in data_addrs; + sc_in interrupt_signal; + sc_out mem_exception; + + + void do_memstage_ctrl(); + + SC_CTOR(memstage_ctrl) + { + SC_METHOD(do_memstage_ctrl); + sensitive << ex_m_IBUS << ex_m_inst_addrl; + sensitive << ex_m_illegal_instruction << ex_m_syscall_exception; + sensitive << ex_m_ovf_excep << DBUS << data_addrl << data_addrs << interrupt_signal; + } +}; Index: tags/arelease/source/cpu/mem_stage/reg_mem.cpp =================================================================== --- tags/arelease/source/cpu/mem_stage/reg_mem.cpp (nonexistent) +++ tags/arelease/source/cpu/mem_stage/reg_mem.cpp (revision 13) @@ -0,0 +1,68 @@ +#include "reg_mem.h" + +void reg_mem::do_reg_mem() +{ + if(reset.read() == true) + { + wb_id_forward.write(WORD_ZERO); + id_ex_m_wb_regwrite.write(SC_LOGIC_0); + id_ex_m_wb_writeregister.write("00000"); + + m_wb_IBUS.write(SC_LOGIC_0); + m_wb_inst_addrl.write(SC_LOGIC_0); + m_wb_syscall_exception.write(SC_LOGIC_0); + m_wb_illegal_instruction.write(SC_LOGIC_0); + m_wb_ovf_excep.write(SC_LOGIC_0); + m_wb_DBUS.write(SC_LOGIC_0); + m_wb_data_addrl.write(SC_LOGIC_0); + m_wb_data_addrs.write(SC_LOGIC_0); + m_wb_instaddr.write(0); + mem_wb_inst.write(WORD_ZERO); + m_wb_dataaddr.write(0); + m_wb_interrupt_signal.write(false); + } + else + { + m_wb_interrupt_signal.write(interrupt_signal.read()); + + if((datahold.read() == false) && (insthold.read() == false) && (enable_memstage.read() == SC_LOGIC_1)) + { + wb_id_forward.write(id_store.read()); + id_ex_m_wb_regwrite.write(id_ex_m_regwrite.read()); + id_ex_m_wb_writeregister.write(id_ex_m_writeregister.read()); + + m_wb_IBUS.write(ex_m_IBUS.read()); + m_wb_inst_addrl.write(ex_m_inst_addrl.read()); + m_wb_syscall_exception.write(ex_m_syscall_exception.read()); + m_wb_illegal_instruction.write(ex_m_illegal_instruction.read()); + m_wb_ovf_excep.write(ex_m_ovf_excep.read()); + m_wb_DBUS.write(DBUS.read()); + m_wb_data_addrl.write(data_addrl.read()); + m_wb_data_addrs.write(data_addrs.read()); + m_wb_instaddr.write(ex_m_instaddr.read()); + mem_wb_inst.write(ex_mem_inst.read()); + m_wb_dataaddr.write(ex_m_dataaddr.read()); + //m_wb_interrupt_signal.write(interrupt_signal.read()); + } + else + if((datahold.read() == false) && (insthold.read() == false) && (enable_memstage.read() == SC_LOGIC_0)) + { + wb_id_forward.write(WORD_ZERO); + id_ex_m_wb_regwrite.write(SC_LOGIC_0); + id_ex_m_wb_writeregister.write("00000"); + + m_wb_IBUS.write(ex_m_IBUS); + m_wb_inst_addrl.write(ex_m_inst_addrl.read()); + m_wb_syscall_exception.write(ex_m_syscall_exception.read()); + m_wb_illegal_instruction.write(ex_m_illegal_instruction.read()); + m_wb_ovf_excep.write(ex_m_ovf_excep.read()); + m_wb_DBUS.write(DBUS.read()); + m_wb_data_addrl.write(data_addrl.read()); + m_wb_data_addrs.write(data_addrs.read()); + m_wb_instaddr.write(ex_m_instaddr.read()); + mem_wb_inst.write(ex_mem_inst.read()); + m_wb_dataaddr.write(ex_m_dataaddr.read()); + //m_wb_interrupt_signal.write(interrupt_signal.read()); + } + } +} Index: tags/arelease/source/cpu/mem_stage/flag_interr.cpp =================================================================== --- tags/arelease/source/cpu/mem_stage/flag_interr.cpp (nonexistent) +++ tags/arelease/source/cpu/mem_stage/flag_interr.cpp (revision 13) @@ -0,0 +1,51 @@ +#include "flag_interr.h" + +void flag_interr::do_fsm_ctrl() +{ + switch(current_state) { + + case Idle: + { + if(interrupt_in.read() == true) + { + next_state = State1; + interrupt_out = false; + } + else + { + next_state = Idle; + interrupt_out = false; + } + } + break; + + case State1://STAGE1 + { + next_state = Idle; + interrupt_out = true; + + } + break; + + + + + default: + { + next_state = Idle; + interrupt_out = false; + } + break; + } +} + +void flag_interr::do_fsm_update() +{ + if(reset.read() == true) + { + current_state = Idle; + next_state = Idle; + } + else + current_state = next_state; +} \ No newline at end of file Index: tags/arelease/source/cpu/mem_stage/multiplexer_mem.h =================================================================== --- tags/arelease/source/cpu/mem_stage/multiplexer_mem.h (nonexistent) +++ tags/arelease/source/cpu/mem_stage/multiplexer_mem.h (revision 13) @@ -0,0 +1,28 @@ +//! Selects whether to bypass data memory or not +/*! + When reading from memory, the data signal from data memory is chosen + sensitive << id_ex_m_memtoreg << ex_m_alu << dataread; + */ + +#include "systemc.h" +#include "../../constants/constants.h" + +SC_MODULE(multiplexer_mem) +{ + sc_in > id_ex_m_byteselect; + sc_in id_ex_m_bssign; + sc_in id_ex_m_memtoreg; + sc_in > ex_m_alu; + sc_in > dataread; + sc_out > id_store; + sc_out > m_id_forward; + + void do_multiplexer_mem(); + + SC_CTOR(multiplexer_mem) + { + SC_METHOD(do_multiplexer_mem); + sensitive << id_ex_m_memtoreg << ex_m_alu << dataread; + sensitive << id_ex_m_byteselect << id_ex_m_bssign; + } +}; Index: tags/arelease/source/cpu/mem_stage/select_mem.cpp =================================================================== --- tags/arelease/source/cpu/mem_stage/select_mem.cpp (nonexistent) +++ tags/arelease/source/cpu/mem_stage/select_mem.cpp (revision 13) @@ -0,0 +1,45 @@ +/*! + Sets the address and request signals to the data memory. + For load instructions, data is set to ZZZ... + sensitive << id_ex_m_datareq << id_ex_m_datarw << id_ex_m_datastore << ex_m_alu << datawrite; + */ + +#include "select_mem.h" +#include "../../constants/constants.h" +void select_mem::do_select_mem() +{ + sc_logic dreq = id_ex_m_datareq.read(); + sc_logic drw = id_ex_m_datarw.read(); + sc_lv<32> d; + sc_uint<32> daddr; + sc_lv<2> byteselect = id_ex_m_byteselect.read(); + + + if(enable_memstage.read() == SC_LOGIC_1) + { + if ((dreq == 1) && (drw == 1)) + { + d = id_ex_m_datastore.read(); + datawrite.write(d); + } + else + { + d = WORD_ZERO; + datawrite.write(d); + } + daddr = ex_m_alu.read(); + dataaddr.write(daddr); + datareq.write(dreq); + datarw.write(drw); + databs.write(byteselect); + } + else + { + datawrite.write(WORD_ZERO); + dataaddr.write(0); + datareq.write(SC_LOGIC_0); + datarw.write(SC_LOGIC_0); + databs.write(byteselect); + + } +} Index: tags/arelease/source/cpu/or_gate.cpp =================================================================== --- tags/arelease/source/cpu/or_gate.cpp (nonexistent) +++ tags/arelease/source/cpu/or_gate.cpp (revision 13) @@ -0,0 +1,6 @@ +#include "or_gate.h" + +void or_gate::do_or_gate() +{ + out_gate.write((in_A.read() | in_B.read())); +} Index: tags/arelease/source/cpu/if_stage.cpp =================================================================== --- tags/arelease/source/cpu/if_stage.cpp (nonexistent) +++ tags/arelease/source/cpu/if_stage.cpp (revision 13) @@ -0,0 +1 @@ +#include "if_stage.h" Index: tags/arelease/source/cpu/sc_cpu.h =================================================================== --- tags/arelease/source/cpu/sc_cpu.h (nonexistent) +++ tags/arelease/source/cpu/sc_cpu.h (revision 13) @@ -0,0 +1,234 @@ +// +// $Id: sc_cpu.h,v 1.1.1.1 2006-01-31 10:55:28 igorloi Exp $ +// + +#ifndef _SC_CPU_H +#define _SC_CPU_H + +#include +#include "../constants/config.h" +#include "../constants/constants.h" +#include "pc_stage.h" +#include "if_stage.h" +#include "id_stage.h" +#include "ex_stage.h" +#include "mem_stage.h" +#include "enable_stage.h" +#include "writeback_ctrl.h" +#include "mux_instaddr.h" + +#ifdef _MULT_PIPELINE_ +#include "or_gate.h" +#endif + +SC_MODULE(sc_cpu) +{ +// to CP0_STAGE + sc_in > new_pc; + sc_in load_epc; + sc_out > pc_in; + sc_out > pc_out; + sc_out id_branch; + sc_out id_ctrl; + sc_out id_ex_datarw; + sc_out id_ex_datareq; + sc_in addr_err; + sc_in insthold; + sc_out > cp0_inst; + sc_out > reg_rs; + sc_in > reg_out; + sc_out > reg_no; + sc_out reg_rw; + sc_out > ex_id_forward; + + + // EXCEPTION SIGNAL FROM DATAMEM AND INSTMEM + //***************************************************************************************************** + sc_in inst_addrl; // disaligned address in instmem during fetch stage + sc_in IBUS; //page fault in instmem + sc_in data_addrl; //disaligned address in datamem during load instruction + sc_in data_addrs; //disaligned address in datamem during store instruction + sc_in DBUS; //page fault in instmem + //***************************************************************************************************** + + // EXCEPTION SIGNALS TO ENABLE/DISABLE PIPELINED STAGE + //***************************************************************************************************** + sc_signal enable_pc; + sc_signal enable_fetch; + sc_signal enable_decode; + sc_signal enable_execute; + sc_signal enable_memstage; + sc_signal if_exception; + sc_signal id_exception; + sc_signal ex_exception; + sc_signal mem_exception; + sc_signal wb_exception; + sc_signal interrupt_exception; + //***************************************************************************************************** + + // INTERRUPT SIGNALS + //********************************************** + sc_in interrupt_signal; + sc_out m_wb_interrupt_signal; + sc_in enable_interrupt; + sc_in enable_kernel_mode; + //********************************************** + + + // PIPELINED EXCEPTION SIGNALS + //***************************************************************************************************** + sc_signal > id_ex_inst; // from id_stage to ex_stage + sc_signal > ex_mem_inst; // from ex_stage to mem_stage + sc_signal > mem_wb_inst; // from mem_stage to WriteBack + sc_signal if_id_inst_addrl; // from if_stage to id_stage + sc_signal if_id_IBUS; // from if_stage to id_stage + sc_signal id_ex_inst_addrl; // from id_stage to ex_stage + sc_signal id_ex_IBUS; // from id_stage to ex_stage + sc_signal id_ex_syscall_exception; // from id_stage to ex_stage + sc_signal id_ex_illegal_instruction; // from id_stage to ex_stage + sc_signal ex_m_ovf_excep; // from ex_stage to mem_stage + sc_signal ex_m_inst_addrl; // from ex_stage to mem_stage + sc_signal ex_m_IBUS; // from ex_stage to mem_stage + sc_signal ex_m_syscall_exception; // from ex_stage to mem_stage + sc_signal ex_m_illegal_instruction; // from ex_stage to mem_stage + sc_out m_wb_DBUS; // from mem_stage to cp0_cause + sc_out m_wb_data_addrl; // from mem_stage to cp0_cause + sc_out m_wb_data_addrs; // from mem_stage to cp0_cause + sc_out m_wb_ovf_excep; // from mem_stage to cp0_cause + sc_out m_wb_syscall_exception; // from mem_stage to cp0_cause + sc_out m_wb_illegal_instruction; // from mem_stage to cp0_cause + sc_out m_wb_IBUS; // from mem_stage to cp0_cause + sc_out m_wb_inst_addrl; // from mem_stage to cp0_cause + + sc_signal > if_id_instaddr; // from if_stage to id_stage (victim address instruction) + sc_signal > id_ex_instaddr; // from id_stage to ex_stage (victim address instruction) + sc_signal > ex_m_instaddr; // from ex_stage to mem_stage address for INTERRUPT EPC + sc_signal > m_wb_instaddr; // from mem_stage to mux_instaddr (victim address instruction) + sc_out > m_wb_instaddr_s; // from mux_instaddr to EPC + sc_out > m_wb_dataaddr; // from mem_stage to cpo_cause (victim address instruction) + //***************************************************************************************************** + + + + // + // Very basic signals for the CPU! + // + //! Main clock signal + sc_in in_clk; + //! Main reset signal + sc_in reset; + + // + // Instruction memory interface + // + //! Instruction memory input data + // sc_inout_rv<32> instdata; + sc_in > instdataread; + sc_out > instdatawrite; + //! Instruction memory address + sc_out > instaddr; + //! Instruction memory request + sc_out instreq; + //! Instruction memory read/write signal. 1 for write. 0 for read. + sc_out instrw; + //! Hold signal from cp0 (Was: instruction memory) + + + //sc_in x_insthold; //in sc_risc! + + // + // Data memory interface + // + //! Data memory in/out data + // sc_inout_rv<32> data; + sc_in > dataread; + sc_out > datawrite; + //! Data memory address + sc_out > dataaddr; + //! Data memory request + sc_out datareq; + //! Data memory read/write signal. 1 for write. 0 for read. + sc_out datarw; + //! Byte select signal. Select bytes to be written. 01 for byte, 10 for halfword + sc_out > databs; + //! Hold signal from data memory + sc_in datahold; + + + // Misc. signals + sc_signal > id_new_pc; + sc_signal > id_jmp_tar; + sc_signal > if_id_inst; + sc_signal > if_id_next_pc; + + // signal from id_stage to ex_stage + sc_signal > id_ex_alu1; + sc_signal > id_ex_alu2; + sc_signal > id_ex_datastore; + sc_signal > id_ex_alu_ctrl; + sc_signal > id_ex_alu_opcode; + sc_signal > id_ex_alu_function; + sc_signal id_ex_equal; + sc_signal > id_ex_byteselect; + sc_signal id_ex_bssign; + sc_signal > id_ex_alu_sa; + + // signal to mem_stage through ex_stage + sc_signal id_ex_memtoreg; + sc_signal > id_ex_m_byteselect; + sc_signal id_ex_m_bssign; + + // signal to mem_stage + sc_signal id_ex_m_datareq; + sc_signal id_ex_m_datarw; + sc_signal > id_ex_m_datastore; + sc_signal > ex_m_alu; + sc_signal id_ex_m_memtoreg; + sc_signal m_ocp_cmd; + + // signal to control save in register + sc_signal > id_ex_writeregister_out; + sc_signal id_ex_regwrite_out; + + // forwarding control signal + sc_signal > id_ex_m_writeregister; + sc_signal > id_ex_m_wb_writeregister; + sc_signal id_ex_m_regwrite; + sc_signal id_ex_m_wb_regwrite; + //sc_signal > ex_id_forward; + sc_signal > m_id_forward; + sc_signal > wb_id_forward; + + + // signals between ID stage and cp0 + + sc_signal inst_break; + sc_signal inst_syscall; + +#ifdef _MULT_PIPELINE_ + sc_signal hold_pipe; + sc_signal insthold_W; +#endif + + pc_stage *pc; + if_stage *if_s; + id_stage *id; + ex_stage *ex; + mem_stage *mem; + enable_stage *enable_stage1; + writeback_ctrl *writeback_ctrl1; + mux_instaddr *mux_instaddr1; +#ifdef _MULT_PIPELINE_ + or_gate *og1; +#endif + + void clocktik() + { + }; + + SC_HAS_PROCESS(sc_cpu); + sc_cpu(const sc_module_name& name_); + +}; + +#endif Index: tags/arelease/source/cpu/cp0.cpp =================================================================== --- tags/arelease/source/cpu/cp0.cpp (nonexistent) +++ tags/arelease/source/cpu/cp0.cpp (revision 13) @@ -0,0 +1,4 @@ +// +// $Id: cp0.cpp,v 1.1.1.1 2006-01-31 10:55:27 igorloi Exp $ +// +#include "cp0.h" Index: tags/arelease/source/cpu/id_stage.h =================================================================== --- tags/arelease/source/cpu/id_stage.h (nonexistent) +++ tags/arelease/source/cpu/id_stage.h (revision 13) @@ -0,0 +1,375 @@ +#include "systemc.h" +#include "./id_stage/control.h" +#include "./id_stage/mux_writeregister.h" +#include "./id_stage/sign_extend.h" +#include "./id_stage/add_new_pc.h" +#include "./id_stage/mux_jump.h" +#include "./id_stage/mux_forward_select.h" +#include "./id_stage/mux_alu1.h" +#include "./id_stage/mux_alu2.h" +#include "./id_stage/comparator.h" +#include "./id_stage/forwarding_control.h" +#include "./id_stage/reg_id.h" +#include "./id_stage/decode_ctrl.h" + +#include "./id_stage/regfile_high.h" + +#include "../constants/config.h" +#include "../constants/constants.h" + +SC_MODULE(id_stage) +{ + sc_in in_clk; + sc_in reset; + + sc_in insthold; + sc_in datahold; + + sc_in > if_id_next_pc; + + sc_in > if_id_inst; // instruction coming from IF_STAGE + sc_out > id_ex_inst; // instruction to EX_STAGE + + // signal to if_stage NOT clk + sc_out > id_jmp_tar; + sc_out > id_new_pc; + sc_out id_branch; + sc_out id_ctrl; + + // signal to ex_stage + sc_out > id_ex_alu1; + sc_out > id_ex_alu2; + sc_out > id_ex_datastore; + sc_out > id_ex_alu_ctrl; + + sc_out > id_ex_alu_opcode; + sc_out > id_ex_alu_function; + + sc_signal > id_function; + sc_signal > id_opcode; + + sc_out id_ex_equal; + sc_out > id_ex_byteselect; + sc_out id_ex_bssign; + sc_out > id_ex_alu_sa; + + // signal to mem_stage throught ex_stage + sc_out id_ex_datareq; + sc_out id_ex_datarw; + sc_out id_ex_memtoreg; + + sc_signal > id_byteselect; + sc_signal id_bssign; + sc_signal > id_alu_sa; + + // signal to control save in register + sc_out > id_ex_writeregister_out; + sc_out id_ex_regwrite_out; + + // forwarding control signal + sc_signal > id_ex_writeregister; + sc_in > id_ex_m_writeregister; + sc_in > id_ex_m_wb_writeregister; + sc_signal id_ex_regwrite; + sc_in id_ex_m_regwrite; + sc_in id_ex_m_wb_regwrite; + sc_in > ex_id_forward; + sc_in > m_id_forward; + sc_in > wb_id_forward; + + // signals to cp0 + sc_out > cp0_inst; // Current instruction + sc_out > cp0_reg_no; // Register to read/write in cp0 + sc_out cp0_reg_rw; // Read/Write signal, 1 for write + sc_out > cp0_reg_rs; // Contents of register rd in instruction for mtc0 + sc_in > cp0_reg_out; // For reading out from cp0 - for mfc0 + + // EXCEPTIONS SIGNALS + sc_signal illegal_instruction; + sc_signal syscall_exception; + sc_in if_id_IBUS; + sc_in if_id_inst_addrl; + sc_out id_ex_IBUS; + sc_out id_ex_inst_addrl; + sc_out id_ex_syscall_exception; + sc_out id_ex_illegal_instruction; + sc_out id_exception; + sc_in enable_decode; + sc_in > if_id_instaddr; + sc_out > id_ex_instaddr; + + sc_in enable_kernel_mode; + + // signals used in control + sc_signal > rt, rs, rd, sa; + + /* sc_lv<5> lrs, lrt, lrd, lsa; // lv version of reg # */ + /* sc_uint<5> uirs, uirt, uird, uisa; // unsigned integer version of reg # */ + /* sc_int<32> is, it, id; // integer version of register contents... */ + + // sign/zero extend and lui control + sc_signal > id_sign_extend; + sc_signal > id_extend_ctrl; + + sc_signal > id_mux_fw1; + sc_signal > id_mux_fw2; + + sc_signal > id_reg1; + sc_signal > id_reg2; + + sc_signal > id_alu1; + sc_signal > id_alu2; + + sc_signal id_equal; + + // signal from control unit + sc_signal > id_writeregister; + sc_signal id_regwrite; + sc_signal > regdest; + sc_signal id_select_jump; + sc_signal id_pc_store; + sc_signal > id_sign_ctrl; + sc_signal > id_branch_select; + sc_signal > id_alu_ctrl; + sc_signal id_datareq; + sc_signal id_datarw; + sc_signal id_memtoreg; + sc_signal id_shamt_ctrl; + sc_signal id_mfc0; + + // forwarding ctrl unit + sc_signal > id_fw_ctrl1; + sc_signal > id_fw_ctrl2; + +#ifdef ONEHOT_DEBUG + sc_signal inst_addiu; + sc_signal inst_jalr; + sc_signal inst_lw; + sc_signal inst_mfc0; + sc_signal inst_mtc0; + sc_signal inst_nop; + sc_signal inst_sw; + sc_signal inst_wait; +#endif + + + control *control1; + mux_writeregister *mux_writeregister1; + sign_extend *sign_extend1; + add_new_pc *add_new_pc1; + mux_jump *mux_jump1; + mux_forward_select *mux_forward_select1; + mux_forward_select *mux_forward_select2; + mux_alu1 *mux_alu_1; + mux_alu2 *mux_alu_2; + comparator *comparator1; + forwarding_control *forwarding_control1; + forwarding_control *forwarding_control2; + reg_id *reg_id1; + regfile *localreg; + decode_ctrl *decode_ctrl1; + + + SC_CTOR(id_stage) + { + control1 = new control("control"); + control1->if_id_inst(if_id_inst); + control1->rs(rs); + control1->rt(rt); + control1->rd(rd); + control1->id_alu_ctrl(id_alu_ctrl); + control1->id_opcode(id_opcode); + control1->id_function(id_function); + control1->id_alu_sa(id_alu_sa); + control1->id_ctrl(id_ctrl); + control1->id_extend_ctrl(id_extend_ctrl); + control1->id_sign_ctrl(id_sign_ctrl); + control1->regdest(regdest); + control1->id_select_jump(id_select_jump); + control1->id_pc_store(id_pc_store); + control1->id_branch_select(id_branch_select); + control1->id_regwrite(id_regwrite); + control1->id_shamt_ctrl(id_shamt_ctrl); + control1->id_datarw(id_datarw); + control1->id_datareq(id_datareq); + control1->id_memtoreg(id_memtoreg); + control1->id_byteselect(id_byteselect); + control1->cp0_inst(cp0_inst); + control1->cp0_reg_no(cp0_reg_no); + control1->cp0_reg_rw(cp0_reg_rw); + control1->id_mfc0(id_mfc0); + control1->illegal_instruction(illegal_instruction); //instruzione non definita!! + control1->syscall_exception(syscall_exception); //instruzione non definita!! + + #ifdef ONEHOT_DEBUG + control1->inst_addiu(inst_addiu); + control1->inst_jalr(inst_jalr); + control1->inst_lw(inst_lw); + control1->inst_mfc0(inst_mfc0); + control1->inst_mtc0(inst_mtc0); + control1->inst_nop(inst_nop); + control1->inst_sw(inst_sw); + control1->inst_wait(inst_wait); + #endif + + mux_writeregister1 = new mux_writeregister("mux_writeregister"); + mux_writeregister1->regdest(regdest); + mux_writeregister1->rt(rt); + mux_writeregister1->rd(rd); + mux_writeregister1->id_writeregister(id_writeregister); + + sign_extend1 = new sign_extend("sign_extend"); + sign_extend1->if_id_inst(if_id_inst); + sign_extend1->id_extend_ctrl(id_extend_ctrl); + sign_extend1->id_sign_extend(id_sign_extend); + + add_new_pc1 = new add_new_pc("add_new_pc"); + add_new_pc1->if_id_next_pc(if_id_next_pc); + add_new_pc1->id_sign_extend(id_sign_extend); + add_new_pc1->id_new_pc(id_new_pc); + + mux_jump1 = new mux_jump("mux_jump"); + mux_jump1->if_id_next_pc(if_id_next_pc); + mux_jump1->if_id_inst(if_id_inst); + mux_jump1->id_select_jump(id_select_jump); + mux_jump1->id_mux_fw1(id_mux_fw1); + mux_jump1->id_jmp_tar(id_jmp_tar); + + mux_forward_select1 = new mux_forward_select("mux_forward_select1"); + mux_forward_select1->id_reg(id_reg1); + mux_forward_select1->ex_id_forward(ex_id_forward); + mux_forward_select1->m_id_forward(m_id_forward); + mux_forward_select1->wb_id_forward(wb_id_forward); + mux_forward_select1->id_fw_ctrl(id_fw_ctrl1); + mux_forward_select1->id_mux_fw(id_mux_fw1); + + mux_forward_select2 = new mux_forward_select("mux_forward_select2"); + mux_forward_select2->id_reg(id_reg2); + mux_forward_select2->ex_id_forward(ex_id_forward); + mux_forward_select2->m_id_forward(m_id_forward); + mux_forward_select2->wb_id_forward(wb_id_forward); + mux_forward_select2->id_fw_ctrl(id_fw_ctrl2); + mux_forward_select2->id_mux_fw(id_mux_fw2); + + mux_alu_1 = new mux_alu1("mux_alu1"); + mux_alu_1->if_id_inst(if_id_inst); + mux_alu_1->id_shamt_ctrl(id_shamt_ctrl); + mux_alu_1->id_pc_store(id_pc_store); + mux_alu_1->id_alu1(id_alu1); + mux_alu_1->if_id_next_pc(if_id_next_pc); + mux_alu_1->cp0_reg_out(cp0_reg_out); + mux_alu_1->id_mux_fw1(id_mux_fw1); + mux_alu_1->id_mfc0(id_mfc0); + + mux_alu_2 = new mux_alu2("mux_alu2"); + mux_alu_2->id_sign_extend(id_sign_extend); + mux_alu_2->id_sign_ctrl(id_sign_ctrl); + mux_alu_2->id_alu2(id_alu2); + mux_alu_2->cp0_reg_rs(cp0_reg_rs); + mux_alu_2->id_mux_fw2(id_mux_fw2); + + comparator1 = new comparator("comparator"); + comparator1->id_mux_fw1(id_mux_fw1); + comparator1->id_mux_fw2(id_mux_fw2); + comparator1->id_branch_select(id_branch_select); + comparator1->id_equal(id_equal); + comparator1->id_branch(id_branch); + + forwarding_control1 = new forwarding_control("forwarding_control1"); + forwarding_control1->id_ex_writeregister(id_ex_writeregister); + forwarding_control1->id_ex_m_writeregister(id_ex_m_writeregister); + forwarding_control1->id_ex_m_wb_writeregister(id_ex_m_wb_writeregister); + forwarding_control1->id_ex_regwrite(id_ex_regwrite); + forwarding_control1->id_ex_m_regwrite(id_ex_m_regwrite); + forwarding_control1->id_ex_m_wb_regwrite(id_ex_m_wb_regwrite); + forwarding_control1->rs(rs); + forwarding_control1->id_fw_ctrl(id_fw_ctrl1); + + forwarding_control2 = new forwarding_control("forwarding_control2"); + forwarding_control2->id_ex_writeregister(id_ex_writeregister); + forwarding_control2->id_ex_m_writeregister(id_ex_m_writeregister); + forwarding_control2->id_ex_m_wb_writeregister(id_ex_m_wb_writeregister); + forwarding_control2->id_ex_regwrite(id_ex_regwrite); + forwarding_control2->id_ex_m_regwrite(id_ex_m_regwrite); + forwarding_control2->id_ex_m_wb_regwrite(id_ex_m_wb_regwrite); + forwarding_control2->rs(rt); + forwarding_control2->id_fw_ctrl(id_fw_ctrl2); + + reg_id1 = new reg_id("reg_id"); + reg_id1->in_clk(in_clk); + reg_id1->reset(reset); + reg_id1->datahold(datahold); + reg_id1->insthold(insthold); + reg_id1->id_ex_alu1(id_ex_alu1); + reg_id1->id_alu1(id_alu1); + reg_id1->id_ex_alu2(id_ex_alu2); + reg_id1->id_alu2(id_alu2); + reg_id1->id_ex_datastore(id_ex_datastore); + reg_id1->id_mux_fw2(id_mux_fw2); + reg_id1->id_ex_alu_ctrl(id_ex_alu_ctrl); + reg_id1->id_alu_ctrl(id_alu_ctrl); + + reg_id1->id_opcode(id_opcode); + reg_id1->id_function(id_function); + + reg_id1->id_ex_alu_opcode(id_ex_alu_opcode); + reg_id1->id_ex_alu_function(id_ex_alu_function); + + reg_id1->id_ex_alu_sa(id_ex_alu_sa); + reg_id1->id_alu_sa(id_alu_sa); + reg_id1->id_ex_equal(id_ex_equal); + reg_id1->id_equal(id_equal); + reg_id1->id_ex_datareq(id_ex_datareq); + reg_id1->id_datareq(id_datareq); + reg_id1->id_ex_datarw(id_ex_datarw); + reg_id1->id_datarw(id_datarw); + reg_id1->id_ex_memtoreg(id_ex_memtoreg); + reg_id1->id_memtoreg(id_memtoreg); + reg_id1->id_ex_writeregister_out(id_ex_writeregister_out); + reg_id1->id_writeregister(id_writeregister); + reg_id1->id_ex_writeregister(id_ex_writeregister); + reg_id1->id_ex_regwrite_out(id_ex_regwrite_out); + reg_id1->id_regwrite(id_regwrite); + reg_id1->id_ex_regwrite(id_ex_regwrite); + reg_id1->id_ex_byteselect(id_ex_byteselect); + reg_id1->id_byteselect(id_byteselect); + reg_id1->id_ex_bssign(id_ex_bssign); + reg_id1->id_bssign(id_bssign); + // pipelined exception signals + reg_id1->if_id_IBUS(if_id_IBUS); + reg_id1->if_id_inst_addrl(if_id_inst_addrl); + reg_id1->syscall_exception(syscall_exception); + reg_id1->illegal_instruction(illegal_instruction); + reg_id1->id_ex_IBUS(id_ex_IBUS); + reg_id1->id_ex_inst_addrl(id_ex_inst_addrl); + reg_id1->id_ex_syscall_exception(id_ex_syscall_exception); + reg_id1->id_ex_illegal_instruction(id_ex_illegal_instruction); + reg_id1->enable_decode(enable_decode); + reg_id1->if_id_instaddr(if_id_instaddr); + reg_id1->id_ex_instaddr(id_ex_instaddr); + + // instruction from ID_STAGE to EX_STAGE + //****************************************************** + reg_id1->if_id_inst(if_id_inst); + reg_id1->id_ex_inst(id_ex_inst); + //****************************************************** + + decode_ctrl1 = new decode_ctrl("decode_ctrl"); + decode_ctrl1->if_id_IBUS(if_id_IBUS); + decode_ctrl1->if_id_inst_addrl(if_id_inst_addrl); + decode_ctrl1->syscall_exception(syscall_exception); + decode_ctrl1->illegal_instruction(illegal_instruction); + decode_ctrl1->id_exception(id_exception); + + localreg = new regfile("regfiles"); + localreg->in_clk(in_clk); + localreg->reset(reset); + localreg->rs(rs); + localreg->rt(rt); + localreg->wr(id_ex_m_wb_regwrite); + localreg->rd_in(wb_id_forward); + localreg->rd(id_ex_m_wb_writeregister); + localreg->rs_out(id_reg1); + localreg->rt_out(id_reg2); + } +}; Index: tags/arelease/source/cpu/or_gate.h =================================================================== --- tags/arelease/source/cpu/or_gate.h (nonexistent) +++ tags/arelease/source/cpu/or_gate.h (revision 13) @@ -0,0 +1,18 @@ +#include "systemc.h" + +SC_MODULE(or_gate) +{ + sc_in in_A; + sc_in in_B; + + sc_out out_gate; + + void do_or_gate(); + + SC_CTOR(or_gate) + { + SC_METHOD(do_or_gate); + sensitive << in_A << in_B; + + } +}; Index: tags/arelease/source/cpu/pc_stage.cpp =================================================================== --- tags/arelease/source/cpu/pc_stage.cpp (nonexistent) +++ tags/arelease/source/cpu/pc_stage.cpp (revision 13) @@ -0,0 +1 @@ +#include "pc_stage.h" Index: tags/arelease/source/cpu/sc_risc.cpp =================================================================== --- tags/arelease/source/cpu/sc_risc.cpp (nonexistent) +++ tags/arelease/source/cpu/sc_risc.cpp (revision 13) @@ -0,0 +1,111 @@ +// +// $Id: sc_risc.cpp,v 1.1.1.1 2006-01-31 10:55:28 igorloi Exp $ +// +#include "sc_risc.h" + +sc_risc::sc_risc(const sc_module_name& name_) +{ + cpu = new sc_cpu("cpu-processor"); + + cpu->in_clk(in_clk); + cpu->reset(reset); + cpu->instdataread(instdataread); + cpu->instdatawrite(instdatawrite); + cpu->instaddr(instaddr); + cpu->instreq(instreq); + cpu->instrw(instrw); + cpu->insthold(x_insthold); + cpu->dataread(dataread); + cpu->datawrite(datawrite); + cpu->dataaddr(dataaddr); + cpu->datareq(datareq); + cpu->datarw(datarw); + cpu->databs(databs); + cpu->datahold(datahold); + cpu->new_pc(new_pc); + cpu->load_epc(load_epc); + cpu->pc_in(pc_in); + cpu->pc_out(pc_out); + cpu->id_branch(id_branch); + cpu->id_ctrl(id_ctrl); + cpu->id_ex_datarw(id_ex_datarw); + cpu->id_ex_datareq(id_ex_datareq); + cpu->addr_err(addr_err); + cpu->cp0_inst(cp0_inst); + cpu->reg_rs(reg_rs); + cpu->reg_out(reg_out); + cpu->reg_no(reg_no); + cpu->reg_rw(reg_rw); + cpu->ex_id_forward(ex_id_forward); + + // EXCEPTION SIGNALS FROM DATAMEM AND INSTMEM + cpu->IBUS(IBUS); + cpu->inst_addrl(inst_addrl); + cpu->DBUS(DBUS); + cpu->data_addrl(data_addrl); + cpu->data_addrs(data_addrs); + + // EXCEPTION STATUS VECTOR FROM CPU TO CP0 + cpu->m_wb_ovf_excep(m_wb_ovf_excep); + cpu->m_wb_syscall_exception(m_wb_syscall_exception); + cpu->m_wb_illegal_instruction(m_wb_illegal_instruction); + cpu->m_wb_inst_addrl(m_wb_inst_addrl); // disaligned address in instmem during fetch stage + cpu->m_wb_IBUS(m_wb_IBUS); //page fault in instmem + cpu->m_wb_data_addrl(m_wb_data_addrl); //disaligned address in datamem during load instruction + cpu->m_wb_data_addrs(m_wb_data_addrs); //disaligned address in datamem during store instruction + cpu->m_wb_DBUS(m_wb_DBUS); //page fault in instmem + cpu->m_wb_dataaddr(m_wb_dataaddr); + cpu->m_wb_instaddr_s(m_wb_instaddr); + cpu->interrupt_signal(interrupt_signal); + cpu->m_wb_interrupt_signal(m_wb_interrupt_signal); + cpu->enable_interrupt(enable_interrupt); + cpu->enable_kernel_mode(enable_kernel_mode); + + co0 = new cp0("cp0_module"); + co0->in_clk(in_clk); + co0->reset(reset); + // to IF stage + co0->new_pc(new_pc); + co0->load_epc(load_epc); + // to/from ID stage + co0->pc_out(pc_out); + co0->pc_in(pc_in); + co0->id_ex_datarw(id_ex_datarw); + co0->id_ex_datareq(id_ex_datareq); + co0->id_branch(id_branch); + co0->id_ctrl(id_ctrl); + // co0->inst_break(inst_break); + // co0->inst_syscall(inst_syscall); + // to ID stage + co0->cp0_inst(cp0_inst); + co0->reg_no(reg_no); + co0->reg_rw(reg_rw); + co0->reg_out(reg_out); + // from ID stage + co0->reg_rs(reg_rs); + // from EX stage + co0->ex_alu(ex_id_forward); + + // to EX stage + co0->addr_err(addr_err); + // to all stages + co0->x_insthold(insthold); // input to cp0 + co0->insthold(x_insthold); // output from cp0*/ + + // EXCEPTION STATUS VECTOR FROM CPU TO CP0 + co0->m_wb_inst_addrl(m_wb_inst_addrl); // disaligned address in instmem during fetch stage + co0->m_wb_IBUS(m_wb_IBUS); //page fault in instmem + co0->m_wb_data_addrl(m_wb_data_addrl); //disaligned address in datamem during load instruction + co0->m_wb_data_addrs(m_wb_data_addrs); //disaligned address in datamem during store instruction + co0->m_wb_DBUS(m_wb_DBUS); //page fault in instmem + co0->m_wb_syscall_exception(m_wb_syscall_exception); + co0->m_wb_illegal_instruction(m_wb_illegal_instruction); + co0->m_wb_ovf_excep(m_wb_ovf_excep); + co0->m_wb_dataaddr(m_wb_dataaddr); + co0->m_wb_instaddr(m_wb_instaddr); + co0->m_wb_interrupt_signal(m_wb_interrupt_signal); + co0->enable_interrupt(enable_interrupt); + co0->enable_kernel_mode(enable_kernel_mode); + +} + Index: tags/arelease/source/cpu/if_stage.h =================================================================== --- tags/arelease/source/cpu/if_stage.h (nonexistent) +++ tags/arelease/source/cpu/if_stage.h (revision 13) @@ -0,0 +1,104 @@ +// Instruction Fetch Stage + + +#ifndef _IF_STAGE_H +#define _IF_STAGE_H + +#include +#include "./if_stage/add.h" +#include "./if_stage/reg_if.h" +#include "./if_stage/select_next_pc.h" +#include "./if_stage/if_ctrl.h" + +SC_MODULE(if_stage) +{ + sc_in in_clk; + sc_in reset; + + sc_in insthold; + sc_in datahold; + + sc_in > pc_out; + sc_in > id_new_pc; + sc_in > id_jmp_tar; + sc_in id_ctrl; + sc_in id_branch; + + sc_out > pc_in; + + sc_in > instdataread; + + //Used when interupt occur during MFLO, MFHI istruction + //****************************************************** + //sc_out > if_id_instdataread; + //****************************************************** + + sc_out > if_id_inst; + sc_out > if_id_next_pc; + + // cp0 connections + sc_in > new_pc; + sc_in load_epc; + + // exception signals + sc_in IBUS; + sc_in inst_addrl; + sc_out if_id_IBUS; + sc_out if_id_inst_addrl; + sc_in > pc_if_instaddr; + sc_out > if_id_instaddr; + + sc_out if_exception; + sc_in enable_fetch; + + // Signals + sc_signal > if_pc_add; + + reg_if *reg_if1; + add *add1; + select_next_pc *select_next_pc1; + if_ctrl *if_ctrl1; + + + SC_CTOR(if_stage) + { + reg_if1 = new reg_if("reg_if"); + reg_if1->in_clk(in_clk); + reg_if1->reset(reset); + reg_if1->insthold(insthold); + reg_if1->datahold(datahold); + reg_if1->instdataread(instdataread); + reg_if1->if_pc_add(if_pc_add); + reg_if1->if_id_inst(if_id_inst); + reg_if1->if_id_next_pc(if_id_next_pc); + //exception signals + reg_if1->IBUS(IBUS); + reg_if1->inst_addrl(inst_addrl); + reg_if1->if_id_IBUS(if_id_IBUS); + reg_if1->if_id_inst_addrl(if_id_inst_addrl); + reg_if1->pc_if_instaddr(pc_if_instaddr); + reg_if1->if_id_instaddr(if_id_instaddr); + reg_if1->enable_fetch(enable_fetch); + + add1 = new add("add"); + add1->if_pc_add(if_pc_add); + add1->pc_out(pc_out); + + select_next_pc1 = new select_next_pc("select_next_pc"); + select_next_pc1->new_pc(new_pc); + select_next_pc1->load_epc(load_epc); + select_next_pc1->id_ctrl(id_ctrl); + select_next_pc1->id_branch(id_branch); + select_next_pc1->if_pc_add(if_pc_add); + select_next_pc1->id_new_pc(id_new_pc); + select_next_pc1->id_jmp_tar(id_jmp_tar); + select_next_pc1->pc_in(pc_in); + + if_ctrl1 = new if_ctrl("if_ctrl"); + if_ctrl1->IBUS(IBUS); + if_ctrl1->inst_addrl(inst_addrl); + if_ctrl1->if_exception(if_exception); + } +}; + +#endif Index: tags/arelease/source/cpu/cp0.h =================================================================== --- tags/arelease/source/cpu/cp0.h (nonexistent) +++ tags/arelease/source/cpu/cp0.h (revision 13) @@ -0,0 +1,219 @@ + +// +// $Id: cp0.h,v 1.1.1.1 2006-01-31 10:55:27 igorloi Exp $ +// + +#ifndef _CP0_H +#define _CP0_H + +#include + +#include "./cp0/cp0_register.h" +#include "./cp0/exception.h" + +#include "./cp0/set_stop_pc.h" + +#include "../constants/config.h" +#include "../constants/constants.h" +#include "../constants/cp0constants.h" +#include "../constants/avrconstants.h" +#include "../constants/mipsconstants.h" + +SC_MODULE(cp0) +{ + sc_in in_clk; + sc_in reset; + + //! Current instruction address + /*! + The current instruction address. + */ + sc_in > pc_out; + + //! Next instrition address + /*! + The next instruction address. + This address can bee the new address after af jump. + */ + sc_in > pc_in; + + //! Data read/write signal, 1 is write + sc_in id_ex_datarw; + + //! Data req + /*! + Data req signal + */ + sc_in id_ex_datareq; + + //! Branch signal + /*! + Indicate that the instruction is a branch if signal bit is set. + */ + sc_in id_branch; + + //! Jump signal + /*! + Indicate that the instruction is a jump if signal bit is set. + */ + sc_in id_ctrl; + + //! Break signal + /*! + This signal indicate that a break instruction has occured. + */ + // sc_in inst_break; + + //! Syscall signal + /*! + This signal indicate a syscall instruction has occured. + */ + // sc_in inst_syscall; + + //! New pc signal + /*! + When an exception occurs, the program counter is loaded with at new value. + */ + sc_out > new_pc; + + //! Load EPC in stead of PC? + /*! + This signal tells the mux to select new_pc from cp0 + */ + sc_out load_epc; + + + + //! The data addres - from EX stage + /*! + The data addres, which is use to load or store a word. + */ + sc_in > ex_alu; + + //! Address error indicator to MEM stage + /*! + addr_err is raised to prevent a memory action to take place when an + Address Error Exception occurs + */ + sc_out addr_err; + + //! The current cp0 instruction in id_stage (if any) + /* + Tells cp0 if the instruction in id_stage is relevant + */ + sc_in > cp0_inst; + + //! To all stages. Stops the cpu by halting cpu + sc_in x_insthold; + sc_out insthold; + + //! Output register no. defined by address in reg_no + sc_in > reg_no; + sc_in reg_rw; + sc_in > reg_rs; + sc_out > reg_out; + + + // EXCEPTIONS SIGNAL FROM DATAMEM aND INSTMEM + sc_in m_wb_inst_addrl; // disaligned address in instmem during fetch stage + sc_in m_wb_IBUS; //page fault in instmem + sc_in m_wb_data_addrl; //disaligned address in datamem during load instruction + sc_in m_wb_data_addrs; //disaligned address in datamem during store instruction + sc_in m_wb_DBUS; //page fault in datamem + + // EXCEPTION SIGNAL FROM INSTRUCTION FETCH STAGE + sc_in m_wb_illegal_instruction; + sc_in m_wb_syscall_exception; + + // This signal is set to 1 by the ALU when an overflow occurs. + sc_in m_wb_ovf_excep; + + // INTERRUPT SIGNAL + sc_in m_wb_interrupt_signal; + + sc_in > m_wb_dataaddr; + sc_in > m_wb_instaddr; + + + sc_signal > cause; + sc_signal check_excep; + sc_signal > to_EPC; + sc_signal > to_BadVAddr; + sc_signal > EPC_FOR_RFE; + + //! Old Branch indication + /*! + This register is used to store informationen of previous branchs or jumps. + */ + sc_signal id_ex_branch_or_jump; + + // 32 registers 32 bit CP0 + sc_signal > cp0regs[32]; + + sc_out enable_interrupt; + sc_out enable_kernel_mode; + + + + cp0_register *cp0_r; + exception *excp; + set_stop_pc *sspc; + + + + SC_CTOR(cp0) + { + + cp0_r = new cp0_register("cp0_register"); + cp0_r->in_clk(in_clk); + cp0_r->reset(reset); + cp0_r->reg_no(reg_no); + cp0_r->reg_rw(reg_rw); + cp0_r->reg_rs(reg_rs); + cp0_r->reg_out(reg_out); + cp0_r->cause(cause); + cp0_r->check_excep(check_excep); + cp0_r->to_EPC(to_EPC); + cp0_r->to_BadVAddr(to_BadVAddr); + cp0_r->EPC_FOR_RFE(EPC_FOR_RFE); + cp0_r->cp0_inst(cp0_inst); + cp0_r->enable_interrupt(enable_interrupt); + cp0_r->enable_kernel_mode(enable_kernel_mode); + cp0_r->insthold(insthold); + + excp = new exception("exception"); + excp->in_clk(in_clk); + excp->reset(reset); + excp->m_wb_IBUS(m_wb_IBUS); + excp->m_wb_inst_addrl(m_wb_inst_addrl); + excp->m_wb_syscall_exception(m_wb_syscall_exception); + excp->m_wb_illegal_instruction(m_wb_illegal_instruction); + excp->m_wb_ovf_excep(m_wb_ovf_excep); + excp->m_wb_DBUS(m_wb_DBUS); + excp->m_wb_data_addrl(m_wb_data_addrl); + excp->m_wb_data_addrs(m_wb_data_addrs); + excp->m_wb_dataaddr(m_wb_dataaddr); + excp->m_wb_instaddr(m_wb_instaddr); + excp->cause(cause); + excp->check_excep(check_excep); + excp->to_EPC(to_EPC); + excp->to_BadVAddr(to_BadVAddr); + excp->m_wb_interrupt_signal(m_wb_interrupt_signal); + excp->cp0_inst(cp0_inst); + + + sspc = new set_stop_pc("set_stop_pc"); + sspc->in_clk(in_clk); + sspc->reset(reset); + sspc->x_insthold(x_insthold); + sspc->insthold(insthold); + sspc->pc_in(pc_in); + sspc->cp0_inst(cp0_inst); + sspc->new_pc(new_pc); + sspc->load_epc(load_epc); + sspc->check_excep(check_excep); + sspc->EPC_FOR_RFE(EPC_FOR_RFE); + } +}; + +#endif Index: tags/arelease/source/cpu/pc_stage.h =================================================================== --- tags/arelease/source/cpu/pc_stage.h (nonexistent) +++ tags/arelease/source/cpu/pc_stage.h (revision 13) @@ -0,0 +1,58 @@ +// +// $Id: pc_stage.h,v 1.1.1.1 2006-01-31 10:55:28 igorloi Exp $ +// +#ifndef _PC_STAGE_H +#define _PC_STAGE_H + +#include +#include "./pc_stage/reg_pc.h" +#include "../constants/constants.h" +#include "../constants/config.h" + +SC_MODULE(pc_stage) +{ + + sc_in in_clk; + sc_in reset; + + sc_in insthold; + sc_in datahold; + + sc_in enable_pc; + + sc_in > pc_in; + sc_out > pc_out; + + sc_out > instaddr; + sc_out > instdatawrite; + + sc_out instreq; + sc_out instrw; + + reg_pc *reg_pc1; + + SC_CTOR(pc_stage) + { + reg_pc1 = new reg_pc("reg_pc"); + + reg_pc1->in_clk(in_clk); + reg_pc1->reset(reset); + + reg_pc1->insthold(insthold); + reg_pc1->datahold(datahold); + + reg_pc1->enable_pc(enable_pc); + + reg_pc1->pc_in(pc_in); + reg_pc1->pc_out(pc_out); + + reg_pc1->instaddr(instaddr); + reg_pc1->instdatawrite(instdatawrite); + + reg_pc1->instreq(instreq); + reg_pc1->instrw(instrw); + } +}; + +#endif + Index: tags/arelease/source/cpu/sc_risc.h =================================================================== --- tags/arelease/source/cpu/sc_risc.h (nonexistent) +++ tags/arelease/source/cpu/sc_risc.h (revision 13) @@ -0,0 +1,113 @@ +// +// $Id: sc_risc.h,v 1.1.1.1 2006-01-31 10:55:28 igorloi Exp $ +// +#ifndef _SC_RISC_H +#define _SC_RISC_H + +#include +#include "../constants/constants.h" +#include "../constants/config.h" +#include "sc_cpu.h" +#include "cp0.h" + +SC_MODULE(sc_risc) +{ + // + // Very basic signals for the CPU! + // + //! Main clock signal + sc_in in_clk; + //! Main reset signal + sc_in reset; + + // + // Instruction memory interface + // + //! Instruction memory input data + sc_in > instdataread; + sc_out > instdatawrite; + //! Instruction memory address + sc_out > instaddr; + //! Instruction memory request + sc_out instreq; + //! Instruction memory read/write signal. 1 for write. 0 for read. + sc_out instrw; + //! Hold signal from instruction memory + sc_in insthold; + + // + // Data memory interface + // + //! Data memory in/out data + sc_in > dataread; + sc_out > datawrite; + //! Data memory address + sc_out > dataaddr; + //! Data memory request + sc_out datareq; + //! Data memory read/write signal. 1 for write. 0 for read. + sc_out datarw; + //! Byte select signal. Select bytes to be written. 01 for byte, 10 for halfword + sc_out > databs; + //! Hold signal from data memory + sc_in datahold; + + //INTERRUPT SIGNAL FROM TOP_MODULE + sc_in interrupt_signal; + sc_signal m_wb_interrupt_signal; + + //interrupt enable and Kernel_mode or User_mode Signal + sc_signal enable_interrupt; + sc_signal enable_kernel_mode; + + //exceptions signal from datamem and instmem + sc_in inst_addrl; // disaligned address in instmem during fetch stage + sc_in IBUS; //page fault in instmem + sc_in data_addrl; //disaligned address in datamem during load instruction + sc_in data_addrs; //disaligned address in datamem during store instruction + sc_in DBUS; //page fault in datamem + + sc_signal m_wb_inst_addrl; + sc_signal m_wb_IBUS; + sc_signal m_wb_data_addrl; + sc_signal m_wb_data_addrs; + sc_signal m_wb_DBUS; + sc_signal m_wb_syscall_exception; // Syscall + sc_signal m_wb_illegal_instruction; // illegal instruction + sc_signal m_wb_ovf_excep; // Overflow + sc_signal > m_wb_instaddr; //victim address in INSTMEM + sc_signal > m_wb_dataaddr; //Victim Address in DATAMEM + sc_signal > ex_m_instaddr; //address of the last non-completed instruction during interrupt + + + // to CP0_STAGE + sc_signal > new_pc; + sc_signal load_epc; + sc_signal > pc_in; + sc_signal > pc_out; + sc_signal id_branch; + sc_signal id_ctrl; + sc_signal id_ex_datarw; + sc_signal id_ex_datareq; + + sc_signal addr_err; + sc_signal x_insthold; + sc_signal > cp0_inst; + sc_signal > reg_rs; + sc_signal > reg_out; + sc_signal > reg_no; + sc_signal reg_rw; + sc_signal > ex_id_forward; + + sc_signal interrupt_exception; + + sc_cpu *cpu; + cp0 *co0; + + + SC_HAS_PROCESS(sc_risc); + sc_risc (const sc_module_name& name_); + +}; + +#endif Index: tags/arelease/source/memory/memory2.h =================================================================== --- tags/arelease/source/memory/memory2.h (nonexistent) +++ tags/arelease/source/memory/memory2.h (revision 13) @@ -0,0 +1,116 @@ +#ifndef _MEMORY2_H +#define _MEMORY2_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../constants/elf.h" +#include "../constants/constants.h" +#include "../constants/config.h" + +SC_MODULE(memory2) +{ + sc_in in_clk; + sc_in reset; + + sc_in memreq; + sc_in memrw; + sc_in > membs; + sc_in > memaddr; + // sc_inout_rv<32> memdata; + sc_in > memdatawrite; + sc_out > memdataread; + // sc_out memhold; + + // Segnali per la gestioe delle eccezioni + sc_out addrl; //indirizzo disallineato in lettura + sc_out addrs; //indirizzo disallineato in scrittura + sc_out page_fault; //indirizzo mancante + + + unsigned int x[MEMSIZE]; // Lower part of kuseg (starting at 0x0000_0000) + char *memoryname; + unsigned int pc; + + void mread(); + void mwrite(); + + void page_fault_analyzer(); + void check_load_aligned(); + void check_store_aligned(); + + +#ifdef _CC_MEMDUMP_ + int memcontents; +#endif + + typedef memory2 SC_CURRENT_USER_MODULE; + memory2(sc_module_name name, char *contents_file) + { + unsigned int i = 0; + unsigned int line; + unsigned int codepos = 0; + //unsigned int datasegstart = 0; + unsigned char *buf; + unsigned char *code; + //char main[4]; +#ifdef _CC_MEMDUMP_ + unsigned int ci = 0x00000000; + + // Create blank memory file filled with 0's + memcontents = open("mem.bin", O_CREAT | O_RDWR, 0666); + for (i = 0; i < (MEMSIZE/4); i++) + write(memcontents, &ci, 4); + close(memcontents); +#endif + + + + FILE *fid = fopen(contents_file, "r"); + buf = (unsigned char*)malloc(32768); + int size = fread(buf, 1, 32768, fid); + code = (unsigned char*)malloc(MEMSIZE); + + + memcpy(code,buf,size); + codepos = size; + + i = 0; + while (i < codepos) + { + line = code[i]; + line += (code[i+1]<<8); + line += (code[i+2]<<16); + line += (code[i+3]<<24); + + x[i>>2] = line; + i += 4; + } + + SC_METHOD(mread); + sensitive << reset; + sensitive_neg << in_clk; + + + SC_METHOD(mwrite); + sensitive << reset; + sensitive_neg << in_clk; + + SC_METHOD(page_fault_analyzer); + sensitive << memaddr << memreq << memrw << membs; + + SC_METHOD(check_load_aligned); + sensitive << memaddr << memreq << memrw << membs; + + SC_METHOD(check_store_aligned); + sensitive << memaddr << memreq << memrw << membs; + } +}; + +#endif Index: tags/arelease/source/memory/memory2.cpp =================================================================== --- tags/arelease/source/memory/memory2.cpp (nonexistent) +++ tags/arelease/source/memory/memory2.cpp (revision 13) @@ -0,0 +1,253 @@ +//! Memory model for 5-stage version of MIPS +// +// $Id: memory2.cpp,v 1.1.1.1 2006-01-31 10:55:29 igorloi Exp $ +// + +#include "memory2.h" +#include +#include + +//! Bla bla.. +// +// Get the memory module @ memaddr +// Output to memdata... +// +void memory2::mread() +{ + sc_lv<32> fd3_map = FD3_MAP; + sc_uint<32> uifd3_map = fd3_map; + sc_lv<32> stop_cpu_map = STOP_CPU_MAP; + sc_uint<32> uistop_cpu_map = stop_cpu_map; + + if(memaddr == uistop_cpu_map) + sc_stop(); + else ; + + sc_lv<32> lmemaddr; + sc_uint<32> imemaddr; + sc_lv<2> byteselect; + sc_uint<32> lmemdataread; + + if (memreq.read() == SC_LOGIC_1) + {} + + if ((memreq.read() == 1) && (memrw.read() == 0) && (reset.read() == false)) + { + imemaddr = memaddr.read(); + lmemaddr = memaddr.read(); + if (lmemaddr(1,0) != "00") + { + // cout << "UNALIGNED ADDRESS" << endl; + } + + byteselect = membs.read(); + if (lmemaddr(1,0) == "01") // Unaligned... + { + lmemdataread = x[imemaddr >> 2]; + if (byteselect == "01") // Select byte, zero rest + lmemdataread = ("000000000000000000000000", lmemdataread.range(15,8)); + else if (byteselect == "10") // Select halfword, zero rest + lmemdataread = ("0000000000000000", lmemdataread.range(23,8)); + else // Select word, this line doesn't work properly because of unalignment! + lmemdataread = lmemdataread; + } + else if (lmemaddr(1,0) == "10") // Unaligned... + { + lmemdataread = x[imemaddr >> 2]; + // cout << "test " << lmemdataread << endl; + if (byteselect == "01") + lmemdataread = ("000000000000000000000000", lmemdataread.range(23,16)); + else + lmemdataread = ("0000000000000000", lmemdataread.range(31,16)); + // cout << "test2 " << lmemdataread << endl; + } + else if (lmemaddr(1,0) == "11") // Unaligned... + { + lmemdataread = x[imemaddr >> 2]; + lmemdataread = ("000000000000000000000000", lmemdataread.range(31,24)); + } + else // Aligned! + { + // cout << "go! " << byteselect << endl; + lmemdataread = x[imemaddr >> 2]; + // cout << "lmemdataread = " << lmemdataread << endl; + if (byteselect == "01") + lmemdataread = ("000000000000000000000000", lmemdataread.range(7,0)); + else if (byteselect == "10") + lmemdataread = ("0000000000000000", lmemdataread.range(15,0)); + else + lmemdataread = lmemdataread; + } + } + else + { + lmemdataread = WORD_ZERO; + } + + memdataread = lmemdataread; +} + +//! Bla bla +// +// For writing - read input from data and write to memaddr... +// +void memory2::mwrite() +{ + sc_lv<32> lmemdata; + sc_lv<32> lmemdatawrite; + sc_lv<32> lmemaddr; + sc_uint<32> imemaddr; + sc_lv<2> byteselect = membs; + +#ifdef _CC_MEMDUMP_ + // For writing + unsigned int i; + int j; +#endif + sc_uint<32> imemdata; + + if (memrw.read() == SC_LOGIC_1) + {} + + if ((memreq.read() == 1) && (memrw.read() == 1) && (reset.read() == false)) + { + lmemdatawrite = memdatawrite.read(); + + imemaddr = memaddr.read(); + lmemaddr = memaddr.read(); + if (lmemaddr.range(1,0) != "00") + { + // imemaddr = imemaddr + 4; + } + + if (lmemaddr.range(1,0) == "00") + { + lmemdata = x[imemaddr >> 2]; + if (byteselect == "01") + lmemdata = (lmemdata.range(31,8), lmemdatawrite.range(7,0)); + else if (byteselect == "10") + lmemdata = (lmemdata.range(31,16), lmemdatawrite.range(15,0)); + else + lmemdata = lmemdatawrite; + } + else if (lmemaddr.range(1,0) == "01") + { + lmemdata = x[imemaddr >> 2]; + if (byteselect == "01") // Write one byte + lmemdata = (lmemdata.range(31,16), lmemdatawrite.range(7,0), lmemdata.range(7,0)); + else if (byteselect == "10") + lmemdata = (lmemdata.range(31,24), lmemdatawrite.range(15,0), lmemdata.range(7,0)); + else // NB! Doesn't work to write entire words unaligned! + lmemdata = (lmemdatawrite.range(23,0), lmemdata.range(7,0)); + } + else if (lmemaddr.range(1,0) == "10") + { + lmemdata = x[imemaddr >> 2]; + if (byteselect == "01") + lmemdata = (lmemdata.range(31,24), lmemdatawrite.range(7,0), lmemdata.range(15,0)); + else + lmemdata = (lmemdatawrite.range(15,0), lmemdata.range(15,0)); + } + else // if (lmemaddr.range(1,0) == "11") + { + lmemdata = x[imemaddr >> 2]; + lmemdata = (lmemdatawrite.range(7,0), lmemdata.range(23,0)); + } + +#ifdef _DEBUG_MEMORY_ + cout << memoryname << ": lmemdata = " << lmemdata << endl; +#endif + imemdata = lmemdata; + x[imemaddr >> 2] = imemdata; + +#ifdef _CC_MEMDUMP_ + i = imemdata; + memcontents = open("mem.bin", O_CREAT | O_RDWR, 0666); + for (j = 0; j < 10000; j++) + { + i = x[j]; + write(memcontents, &i, 4); + } + close(memcontents); +#endif + } +} + +void memory2::page_fault_analyzer() +{ + if(memreq == SC_LOGIC_1) + { + if(( (unsigned int) memaddr.read() ) < MEMSIZE) + page_fault.write(SC_LOGIC_0); + else + page_fault.write(SC_LOGIC_1); + } + else page_fault.write(SC_LOGIC_0); +} + + +void memory2::check_load_aligned() +{ + sc_uint<2> twobit; + sc_uint<1> onebit; + + twobit = (memaddr.read()).range(1,0); + onebit = (memaddr.read()).range(0,0); + + if(memreq == SC_LOGIC_1 ) + { + if(membs.read() == "00") //accesso ad una word + { + if(twobit == 0) + addrl.write(SC_LOGIC_0); //dato allineato + else + addrl.write(SC_LOGIC_1); // dato disallineato + } + else + if(membs.read() == "10") // accesso ad una half word + { + if(memreq == SC_LOGIC_1) + if(onebit == 0 ) + addrl.write(SC_LOGIC_0); //dato allineato + else + addrl.write(SC_LOGIC_1); // dato disallineato + } + // L'accesso a singolo byte non genera mai errori + } + else + addrl.write(SC_LOGIC_0); +} + +void memory2::check_store_aligned() +{ + sc_uint<2> twobit; + sc_uint<1> onebit; + + twobit = (memaddr.read()).range(1,0); + onebit = (memaddr.read()).range(0,0); + + if((memreq.read() == SC_LOGIC_1 ) && (memrw.read() == SC_LOGIC_1 ) ) + { + if(membs.read() == "00") //aligned data accesso a word + { + if(twobit == 0) + addrs.write(SC_LOGIC_0); //dato allineato + else + addrs.write(SC_LOGIC_1); // dato disallineato + } + else + if(membs.read() == "10") // accesso ad una half word + { + if(onebit == 0) + addrs.write(SC_LOGIC_0); //dato allineato + else + addrs.write(SC_LOGIC_1); // dato disallineato + } + // L'accesso a singolo byte non genera mai errori + } + else + addrs.write(SC_LOGIC_0); +} + + + Index: tags/arelease/source/memory/Makefile =================================================================== --- tags/arelease/source/memory/Makefile (nonexistent) +++ tags/arelease/source/memory/Makefile (revision 13) @@ -0,0 +1,36 @@ +TARGET_ARCH = linux + +CC = g++ +OPT = -O3 +DEBUG = -g +OTHER = -Wall +CFLAGS = $(OPT) $(OTHER) +# CFLAGS = $(DEBUG) $(OTHER) ram16x1d.cpp + +MODULE = D_M +SRCS = memory2.cpp + +OBJS = $(SRCS:.cpp=.o) +DEPS = $(SRCS:.cpp=.d) + + +%.o : %.cpp + $(CC) $(INCDIR) $(LIBDIR) $(EXTRA) $(CFLAGS) -c -o $@ $< + +%.d: %.cpp + set -e; $(CC) -MM $(INCDIR) $(LIBDIR) $(CFLAGS) $(EXTRA) $< | sed 's/\($*\)\.o[ :]*/\1.o $@ : /g' > $@; \ + [ -s $@ ] || rm -f $@ + +%.o : %.cc + $(CC) $(INCDIR) $(LIBDIR) $(EXTRA) $(CFLAGS) -c -o $@ $< + +%.d: %.cc + set -e; $(CC) -MM $(INCDIR) $(LIBDIR) $(CFLAGS) $(EXTRA) $< | sed 's/\($*\)\.o[ :]*/\1.o $@ : /g' > $@; \ + [ -s $@ ] || rm -f $@ + + +$(MODULE): $(OBJS) + $(CC) $(CFLAGS) $(INCDIR) $(LIBDIR) -o $@ $(OBJS) $(LIBS) 2>&1 | c++filt + + +include ./Makefile.defs Index: tags/arelease/source/memory/Makefile.defs =================================================================== --- tags/arelease/source/memory/Makefile.defs (nonexistent) +++ tags/arelease/source/memory/Makefile.defs (revision 13) @@ -0,0 +1,33 @@ +## Variable that points to SystemC installation path +SYSTEMC = /home/chester/Desktop/systemc-2.0.1 + + +INCDIR = -I. -I.. -I$(SYSTEMC)/include +LIBDIR = -L. -L.. -L$(SYSTEMC)/lib-$(TARGET_ARCH) + +LIBS = -lsystemc -lm $(EXTRA_LIBS) + + +EXE = $(MODULE).x + +.SUFFIXES: .cc .cpp .o .x + +$(EXE): $(OBJS) $(SYSTEMC)/lib-$(TARGET_ARCH)/libsystemc.a + $(CC) $(CFLAGS) $(INCDIR) $(LIBDIR) -o $@ $(OBJS) $(LIBS) 2>&1 | c++filt + +.cpp.o: + $(CC) $(CFLAGS) $(INCDIR) -c $< + +.cc.o: + $(CC) $(CFLAGS) $(INCDIR) -c $< + +clean:: + rm -f $(OBJS) *~ $(EXE) core + +ultraclean: clean + rm -f Makefile.deps + +Makefile.deps: +# $(CC) $(CFLAGS) $(INCDIR) -M $(SRCS) >> Makefile.deps + +#include Makefile.deps Index: tags/arelease/source/top.h =================================================================== --- tags/arelease/source/top.h (nonexistent) +++ tags/arelease/source/top.h (revision 13) @@ -0,0 +1,130 @@ +#include +#include "./constants/config.h" +#include "./cpu/sc_risc.h" +#include "./memory/memory2.h" +#include "./embedded_perif/mux.h" +#include "./embedded_perif/decoder.h" +#include "./generators/reset_gen.h" +#include "./generators/timer.h" +//#include "./generators/clock_gen.h" + +SC_MODULE(top) +{ + sc_in in_clk; + sc_signal reset; + + sc_signal > dataread_m_dec, dataread_dec_cpu, datawrite, instdataread, instdatawrite; + sc_signal > instaddr, dataaddr; + sc_signal instreq, datareq, instrw, datarw; + sc_signal > databs; + sc_signal insthold, datahold; + sc_signal > instbs; + sc_signal data_addrl, data_addrs, inst_addrl, inst_addrs; + sc_signal IBUS, DBUS; + + sc_signal > selector; + sc_signal > DUMMY_WIRE; + sc_signal interrupt_signal, interrupt_signal_2; + + //clock_gen *clock_gen1; + mux *mux_data; + decoder *decod; + reset_gen *reset_gen1; + sc_risc *risc; + memory2 *instmem; + memory2 *datamem; + sample_clock_generator *s_c_g; + + typedef top SC_CURRENT_USER_MODULE; + top(sc_module_name name, char *contents_file) + { + instbs = "00"; + insthold = false; + datahold = false; + DUMMY_WIRE = WORD_ZERO; + + reset_gen1 = new reset_gen("reset-blok"); + reset_gen1->in_clk(in_clk); + reset_gen1->reset(reset); + + //clock_gen1 = new clock_gen("clock-generator"); + //clock_gen1->in_clk(in_clk); + + mux_data = new mux("Multiplexer_Input"); + mux_data->in_0(dataread_m_dec); + mux_data->in_1(DUMMY_WIRE); + mux_data->in_2(DUMMY_WIRE); + mux_data->in_3(DUMMY_WIRE); + mux_data->in_4(DUMMY_WIRE); + mux_data->in_5(DUMMY_WIRE); + mux_data->in_6(DUMMY_WIRE); + mux_data->in_7(DUMMY_WIRE); + mux_data->sel(selector); + mux_data->out_mux(dataread_dec_cpu); + + + decod = new decoder("DECODER_input"); + decod->sel(selector); + decod->dataaddr(dataaddr); + + risc = new sc_risc("risc-processor"); + risc->in_clk(in_clk); + risc->reset(reset); + risc->instdataread(instdataread); + risc->instdatawrite(instdatawrite); + risc->instaddr(instaddr); + risc->instreq(instreq); + risc->instrw(instrw); + risc->insthold(insthold); + risc->dataread(dataread_dec_cpu); + risc->datawrite(datawrite); + risc->dataaddr(dataaddr); + risc->datareq(datareq); + risc->datarw(datarw); + risc->databs(databs); + risc->datahold(datahold); + risc->data_addrl(data_addrl); + risc->data_addrs(data_addrs); + risc->DBUS(DBUS); + risc->inst_addrl(inst_addrl); + risc->IBUS(IBUS); + risc->interrupt_signal(interrupt_signal); //commentare questa riga per non generare interrupt + //risc->interrupt_signal(interrupt_signal_2); //commentare questa riga per generare interrupt + + instmem = new memory2("instruction-memory", contents_file); + instmem->memoryname = "instruction-memory"; + instmem->in_clk(in_clk); + instmem->reset(reset); + instmem->memaddr(instaddr); + instmem->memdataread(instdataread); + instmem->memdatawrite(instdatawrite); + instmem->memreq(instreq); + instmem->memrw(instrw); + instmem->membs(instbs); + instmem->addrl(inst_addrl); + instmem->addrs(inst_addrs); + instmem->page_fault(IBUS); + + datamem = new memory2("data-memory", contents_file); + datamem->memoryname = "data-memory"; + datamem->in_clk(in_clk); + datamem->reset(reset); + datamem->memaddr(dataaddr); + datamem->memdataread(dataread_m_dec); + datamem->memdatawrite(datawrite); + datamem->memreq(datareq); + datamem->memrw(datarw); + datamem->membs(databs); + datamem->addrl(data_addrl); + datamem->addrs(data_addrs); + datamem->page_fault(DBUS); + + s_c_g = new sample_clock_generator("sample_clock_generator"); + s_c_g->in_clk(in_clk); + s_c_g->reset(reset); + s_c_g->sample_clock(interrupt_signal); + + + interrupt_signal_2.write(false); + }; +}; Index: tags/arelease/source/generators/reset_gen.h =================================================================== --- tags/arelease/source/generators/reset_gen.h (nonexistent) +++ tags/arelease/source/generators/reset_gen.h (revision 13) @@ -0,0 +1,15 @@ +#include "systemc.h" + +SC_MODULE(reset_gen) +{ + sc_in in_clk; + sc_out reset; + + void do_reset(); + + SC_CTOR(reset_gen) + { + SC_THREAD(do_reset); + sensitive << in_clk.pos(); + } +}; Index: tags/arelease/source/generators/timer.cpp =================================================================== --- tags/arelease/source/generators/timer.cpp (nonexistent) +++ tags/arelease/source/generators/timer.cpp (revision 13) @@ -0,0 +1,22 @@ +#include "timer.h" + +void sample_clock_generator::do_sample_clock_generator() +{ + if(reset.read() == true) + count = 0; + else + count = count + 1 ; + + if (count == 50) + { + count = 0; + sample_clock.write(true); + } + else + sample_clock.write(false); + + + + + +} Index: tags/arelease/source/generators/timer.h =================================================================== --- tags/arelease/source/generators/timer.h (nonexistent) +++ tags/arelease/source/generators/timer.h (revision 13) @@ -0,0 +1,19 @@ +#include "systemc.h" + +SC_MODULE(sample_clock_generator) +{ + sc_in in_clk; + sc_in reset; + sc_out sample_clock; + + unsigned int count; + + void do_sample_clock_generator(); + + SC_CTOR(sample_clock_generator) + { + SC_METHOD(do_sample_clock_generator); + sensitive_pos << in_clk; + sensitive << reset; + } +}; Index: tags/arelease/source/generators/reset_gen.cpp =================================================================== --- tags/arelease/source/generators/reset_gen.cpp (nonexistent) +++ tags/arelease/source/generators/reset_gen.cpp (revision 13) @@ -0,0 +1,20 @@ +#include "reset_gen.h" + +void reset_gen::do_reset() +{ + reset.write(false); + wait(); + wait(); + + reset.write(true); + + wait(); + wait(); + wait(); + wait(); + reset.write(false); + wait(); + wait(); + wait(); + wait(); +} Index: tags/arelease/source/generators/Makefile =================================================================== --- tags/arelease/source/generators/Makefile (nonexistent) +++ tags/arelease/source/generators/Makefile (revision 13) @@ -0,0 +1,39 @@ +#Makefile Mips R2000 developed by Igor Loi +#v 1.0 2004/12/05 21:42 Diee Cagliari +# Thanks to Nicolai Ascanium from IMM + +TARGET_ARCH = linux + +CC = g++ +OPT = -O3 +DEBUG = -g +OTHER = -Wall +CFLAGS = $(OPT) $(OTHER) +# CFLAGS = $(DEBUG) $(OTHER) +MODULE = mips2 +SRCS = timer.cpp + +OBJS = $(SRCS:.cpp=.o) +DEPS = $(SRCS:.cpp=.d) + + +%.o : %.cpp + $(CC) $(INCDIR) $(LIBDIR) $(EXTRA) $(CFLAGS) -c -o $@ $< + +%.d: %.cpp + set -e; $(CC) -MM $(INCDIR) $(LIBDIR) $(CFLAGS) $(EXTRA) $< | sed 's/\($*\)\.o[ :]*/\1.o $@ : /g' > $@; \ + [ -s $@ ] || rm -f $@ + +%.o : %.cc + $(CC) $(INCDIR) $(LIBDIR) $(EXTRA) $(CFLAGS) -c -o $@ $< + +%.d: %.cc + set -e; $(CC) -MM $(INCDIR) $(LIBDIR) $(CFLAGS) $(EXTRA) $< | sed 's/\($*\)\.o[ :]*/\1.o $@ : /g' > $@; \ + [ -s $@ ] || rm -f $@ + + +$(MODULE): $(OBJS) + $(CC) $(CFLAGS) $(INCDIR) $(LIBDIR) -o $@ $(OBJS) $(LIBS) 2>&1 | c++filt + + +include ./Makefile.defs Index: tags/arelease/source/generators/Makefile.defs =================================================================== --- tags/arelease/source/generators/Makefile.defs (nonexistent) +++ tags/arelease/source/generators/Makefile.defs (revision 13) @@ -0,0 +1,33 @@ +## Variable that points to SystemC installation path +SYSTEMC = /home/chester/Desktop/systemc-2.0.1 + + +INCDIR = -I. -I.. -I$(SYSTEMC)/include +LIBDIR = -L. -L.. -L$(SYSTEMC)/lib-$(TARGET_ARCH) + +LIBS = -lsystemc -lm $(EXTRA_LIBS) + + +EXE = $(MODULE).x + +.SUFFIXES: .cc .cpp .o .x + +$(EXE): $(OBJS) $(SYSTEMC)/lib-$(TARGET_ARCH)/libsystemc.a + $(CC) $(CFLAGS) $(INCDIR) $(LIBDIR) -o $@ $(OBJS) $(LIBS) 2>&1 | c++filt + +.cpp.o: + $(CC) $(CFLAGS) $(INCDIR) -c $< + +.cc.o: + $(CC) $(CFLAGS) $(INCDIR) -c $< + +clean:: + rm -f $(OBJS) *~ $(EXE) core + +ultraclean: clean + rm -f Makefile.deps + +Makefile.deps: +# $(CC) $(CFLAGS) $(INCDIR) -M $(SRCS) >> Makefile.deps + +#include Makefile.deps Index: tags/arelease/source/top_debug.cpp =================================================================== --- tags/arelease/source/top_debug.cpp (nonexistent) +++ tags/arelease/source/top_debug.cpp (revision 13) @@ -0,0 +1,409 @@ +#include "top_debug.h" + +void decode(sc_lv<32> if_id_inst, unsigned int i, ostream& out) +{ + + sc_lv<32> inst = if_id_inst; + sc_lv<6> func = inst.range(5,0); + sc_lv<6> op = inst.range(31,26); + + char *charinst=0; + + sc_lv<5> rs, rt ,rd ,lrs, lrt, lrd, lsa; // lv version of reg # + sc_uint<5> uirs, uirt, uird, uisa; // unsigned integer version of reg # + sc_int<32> is, it, id; // integer version of register contents... + + //! The immediate value in an instruction + sc_lv<16> imm; + sc_lv<32> imm_sign, imm_zero; + sc_int<32> iimm_sign, iimm_zero; + sc_uint<32> uiimm_sign, uiimm_zero; + sc_lv<28> instr_index; + sc_uint<28> uiinstr_index; + + // register destinations and recipients + rs = inst.range(25,21); + rt = inst.range(20,16); + rd = inst.range(15,11); + uirs = lrs = inst.range(25,21); + uirt = lrt = inst.range(20,16); + uird = lrd = inst.range(15,11); + uisa = lsa = inst.range(10,6); + + + // Immediate values + imm = inst.range(15,0); + uiimm_zero = iimm_zero = imm_zero = (HALFWORD_ZERO,imm); + if( imm[15] == '1') + uiimm_sign = iimm_sign = imm_sign = (HALFWORD_ONE,imm); + else + uiimm_sign = iimm_sign = imm_sign = (HALFWORD_ZERO,imm); + + uiinstr_index = instr_index = (inst.range(25,0), "00"); + + + + //switch stage + if(op == OP_RFORMAT) + { + if(func == FUNC_JR) + { + out << " MIPS (ID): jr $"<< dec << (unsigned int)uirs << endl; + } + else if(func == FUNC_JALR) + { + if (uird == 0) + out << " MIPS (ID): jalr $" << dec << (unsigned int)uirs << endl; + else + out << " MIPS (ID): jalr $" << dec << (unsigned int)uird << ", $" << dec << (unsigned int)uirs << endl; + } + + /* + + */ + else + if(func == FUNC_MTHI || + func == FUNC_MFLO || + func == FUNC_MULT || + func == FUNC_MULTU || + func == FUNC_DIV || + func == FUNC_DIVU) + + if (func == FUNC_MTHI) {charinst = "mthi"; out << " MIPS (ID): " << charinst << " $" << dec << (unsigned int) uirs << " [Hi]" << endl;} + + if (func == FUNC_MFLO) {charinst = "mflo"; out << " MIPS (ID): " << charinst << " $" << dec << (unsigned int) uird << " [Lo]" << endl;} + + if (func == FUNC_MULT) {charinst = "mult"; out << " MIPS (ID): " << charinst << " [Hi,Lo]," <<" $" << dec << (unsigned int)uirs << ", $" << dec << (unsigned int)uirt << endl;} + + if (func == FUNC_MULTU) {charinst = "multu"; out << " MIPS (ID): " << charinst <<" [Hi,Lo], $" << dec << (unsigned int)uirs << ", $" << dec << (unsigned int)uirt << endl;} + + if (func == FUNC_DIV) {charinst = "div"; out << " MIPS (ID): " << charinst << " [Quoz = Hi, Resto = Lo], $" << dec << (unsigned int)uirs << ", $" << dec << (unsigned int)uirt << endl;} + + if (func == FUNC_DIVU) {charinst = "divu"; out << " MIPS (ID): " << charinst << " [Quoz = Hi, Rest = Lo], $" << dec << (unsigned int)uirs << ", $" << dec << (unsigned int)uirt << endl;} + + + else if(func == FUNC_SLL || + func == FUNC_SRL || + func == FUNC_SRA) + { + if (func == FUNC_SLL) charinst = "sll"; + if (func == FUNC_SRL) charinst = "srl"; + if (func == FUNC_SRA) charinst = "sra"; + if (func == FUNC_SLL && (unsigned int)uird == 0) + out << " MIPS (ID): nop" << endl; + else + out << " MIPS (ID): " << charinst << " $" << dec << (unsigned int)uird <<", $" << dec << (unsigned int)uirt <<", " << dec << (unsigned int)uisa << endl; + } + else if(func == FUNC_SLLV || + func == FUNC_SRLV || + func == FUNC_SRAV || + func == FUNC_ADD || + func == FUNC_ADDU || + func == FUNC_SUB || + func == FUNC_SUBU || + func == FUNC_AND || + func == FUNC_OR || + func == FUNC_XOR || + func == FUNC_NOR || + func == FUNC_SLT || + func == FUNC_SLTU) + { + + // printf("MIPS (ID): R-Format - read next line!\n"); + if (func == FUNC_SLLV) charinst = "sllv"; + if (func == FUNC_SRLV) charinst = "srlv"; + if (func == FUNC_SRAV) charinst = "srav"; + if (func == FUNC_ADD) charinst = "add"; + if (func == FUNC_ADDU) charinst = "addu"; + if (func == FUNC_SUB) charinst = "sub"; + if (func == FUNC_SUBU) charinst = "subu"; + if (func == FUNC_AND) charinst = "and"; + if (func == FUNC_OR) charinst = "or"; + if (func == FUNC_XOR) charinst = "xor"; + if (func == FUNC_NOR) charinst = "nor"; + if (func == FUNC_SLT) charinst = "slt"; + if (func == FUNC_SLTU) charinst = "sltu"; + out << " MIPS (ID): " << charinst << " $" << dec << (unsigned int)uird << ", $" << dec << (unsigned int)uirs << ", $" << dec << (unsigned int)uirt << endl; + } + else if (func == FUNC_BREAK) + { + out << " MIPS (ID): BREAK" << endl; + } + + else if (func == FUNC_SYSCALL) + { + out << " MIPS (ID): SYSCALL" << endl; + } + + else if (func == FUNC_BREAK || func == FUNC_SYSCALL) + { + out << " Exception!!" << endl; + } + + else + { + out << " * UNKNOWN FUNCTION CODE FOR R-format" << endl; + } + } + else if(op == OP_BRANCH) + { + // PRINTLN("Branch format"); + if(lrt.range(1,0) == BRANCH_BLTZ) + { + out << " MIPS (ID): bltz $" << dec << (unsigned int)uirs << ", " << dec << (unsigned int)iimm_sign << endl; + } + + else if(lrt.range(1,0) == BRANCH_BGEZ) + { + out << " MIPS (ID): bgez $" << dec << (unsigned int)uirs << ", " << dec << (unsigned int)iimm_sign << endl; + } + + else if(lrt.range(1,0) == BRANCH_BLTZAL) + { + out << " MIPS (ID): bltzal $"<< dec << (unsigned int)uirs << ", " << dec << (unsigned int)iimm_sign << endl; + } + else if(lrt.range(1,0) == BRANCH_BGEZAL) + { + + out << " MIPS (ID): bgezal $" << dec << (unsigned int)uirs << ", " << dec << (unsigned int)iimm_sign << endl; + } + } + + + else if(op == OP_J) + { + + out << " MIPS (ID): j "<< dec << (unsigned int) uiinstr_index << endl; + } + + + else if(op == OP_JAL) + { + out << " MIPS (ID): jal " << dec << (unsigned int) uiinstr_index << endl; + } + + + else if(op == OP_BEQ) + { + out << " MIPS (ID): beq $" << dec << (unsigned int)uirt << ", $" << dec << (unsigned int)uirs << ", " << dec << (unsigned int)iimm_sign << endl; + } + + + else if(op == OP_BNE) + { + out << " MIPS (ID): bne $"<< dec << (unsigned int)uirt << ", $" << dec << (unsigned int)uirs << ", " << dec << (unsigned int)iimm_sign << endl; + } + + + else if(op == OP_BLEZ) + { + out << " MIPS (ID): blez $" << dec << (unsigned int) uirs << ", " << dec << (unsigned int) iimm_sign << endl; + } + + + else if(op == OP_BGTZ) + { + out << " MIPS (ID): bgtz $" << dec << (unsigned int)uirs << ", " << (unsigned int)iimm_sign << endl; + } + + + else if(op == OP_ADDI) + { + out << " MIPS (ID): addi $" << dec << (unsigned int)uirt << ", $" << dec << (unsigned int)uirs << ", " << dec << (unsigned int)iimm_sign << endl; + } + + + else if(op == OP_ADDIU) + { + out << " MIPS (ID): addiu $" << dec << (unsigned int)uirt << ", $" << dec << (unsigned int)uirs << ", " << dec << (int)uiimm_sign << endl; + } + + + else if(op == OP_SLTI) + { + out << " MIPS (ID): slti $" << dec << (unsigned int)uirt << ", $" << dec << (unsigned int)uirs << ", " << dec << (unsigned int)iimm_sign << endl; + } + + + else if(op == OP_SLTIU) + { + out << " MIPS (ID): sltiu $" << dec << (unsigned int)uirt << ", $" << dec << (unsigned int)uirs << ", " << dec << (unsigned int)iimm_sign << endl; + } + + + else if(op == OP_ANDI) + { + out << " MIPS (ID): andi $" << dec << (unsigned int)uirt << ", $" << dec << (unsigned int)uirs << ", 0x" << hex << (unsigned int)iimm_sign << endl; + } + + + else if(op == OP_ORI) + { + out << " MIPS (ID): ori $" << dec << (unsigned int)uirt << ", $" << dec << (unsigned int)uirs << ", 0x" << hex << (unsigned int)iimm_sign << endl; + } + + + else if(op == OP_XORI) + { + out << " MIPS (ID): xori $" << dec << (unsigned int)uirt << ", $" << dec << (unsigned int)uirs << ", 0x" << hex << (unsigned int)iimm_sign << endl; + } + + + else if(op == OP_LUI) + { + out << " MIPS (ID): lui $" << dec << (unsigned int)uirt << ", " << dec << (unsigned int)iimm_sign << endl; + } + + + else if(op == OP_LB || + op == OP_LH || + op == OP_LWL || + op == OP_LW || + op == OP_LBU || + op == OP_LHU || + op == OP_LWR) + { + if (op == OP_LB) charinst = "lb"; + if (op == OP_LH) charinst = "lh"; + if (op == OP_LWL) charinst = "lwl"; + if (op == OP_LW) charinst = "lw"; + if (op == OP_LBU) charinst = "lbu"; + if (op == OP_LHU) charinst = "lhu"; + if (op == OP_LWR) charinst = "lwr"; + out << " MIPS (ID): " << charinst << " $" << dec << (unsigned int)uirt << ", " << dec << (unsigned int)iimm_sign << "($" << dec << (unsigned int)uirs << ") (" << dec << (unsigned int)(is + iimm_sign) << ")" << endl; + } + + + else if(op == OP_SB || + op == OP_SH || + op == OP_SWL || + op == OP_SW || + op == OP_SWR) + { + if (op == OP_SB) charinst = "sb"; + if (op == OP_SH) charinst = "sh"; + if (op == OP_SWL) charinst = "swl"; + if (op == OP_SW) charinst = "sw"; + if (op == OP_SWR) charinst = "swr"; + out << " MIPS (ID): " << charinst <<" $" << dec << (unsigned int)uirt << ", " << dec << (unsigned int)iimm_sign << "($" << dec << (unsigned int)uirs << ") (" << dec << (unsigned int)(is + iimm_sign) << ")" << endl; + } + + + else if(op == OP_CACHE) + { + out << " MIPS (ID): CACHE $" << dec << (unsigned int)uirt << ", $" << dec << (unsigned int)iimm_sign.range(15,0) << "(" << dec << (unsigned int) uirs << ")" << endl; + } + + + else if(op == OP_COPROC0) + { + out << " MIPS (ID): CP0 instruction" << endl; + } + else + { + if(lrs == RS_MFC0) + { + out << " MIPS (ID): mfc0 $" << dec << (unsigned int)uirt << ", $" << dec << (unsigned int)uird << endl; + } + else if(lrs == RS_MTC0) + { + out << " MIPS (ID): mtc0 $" << dec << (unsigned int)uirt << ", $" << dec << (unsigned int)uird << endl; + } + } + } + + + + + + + + + +void top_debug::debug_signals() +{ + ofstream out("GIGINO.txt"); + + out << endl; + out << "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx" << endl; + out << " Simulationon after " << sc_simulation_time() << "ns Clock n°" << sc_simulation_time()/20 << " Reset =" << top_level->reset << endl; + out << "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx REGISTERS xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx" << endl; + out << endl; + for (int n=0; n < 8; n++) + { + out << "$"<< dec << n <<" = 0x" << hex << setw(8) << setfill('0') <<(unsigned int) ((sc_uint<32>)(top_level->risc->cpu->id->localreg->r[n])); + + out << " $"<< dec << n+8 <<" = 0x" << hex << setw(8) << setfill('0') <<(unsigned int) ((sc_uint<32>)(top_level->risc->cpu->id->localreg->r[n+8])); + + out << " $"<< dec << n+16 <<" = 0x" << hex << setw(8) << setfill('0') <<(unsigned int) ((sc_uint<32>)(top_level->risc->cpu->id->localreg->r[n+16])); + + out << " $"<< dec << n+24 <<" = 0x" << hex << setw(8) << setfill('0') <<(unsigned int) ((sc_uint<32>)(top_level->risc->cpu->id->localreg->r[n+24]))<< endl; + + } + + out << " [HI] = " << hex << setw(8) << setfill('0') << (unsigned int) ((sc_uint<32>) top_level->risc->cpu->ex->out_hi) << endl; + + out << " [LO] = " << hex << setw(8) << setfill('0') << (unsigned int) ((sc_uint<32>) top_level->risc->cpu->ex->out_lo) << endl; + + + out << endl; + out << "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx DATA xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx" << endl; + + out << " dataaddr = 0x" << hex << setw(8) << setfill('0') << (unsigned int) ((sc_uint<32>)(top_level->dataaddr)) << endl; + out << " dataread = 0x" << hex << setw(8) << setfill('0') << (unsigned int) ((sc_uint<32>) (top_level->dataread_dec_cpu)) << " ("<< top_level->dataread_dec_cpu <<")"<< endl; + out << " datawrite = 0x" << hex << setw(8) << setfill('0') << (unsigned int) ((sc_uint<32>) (top_level->datawrite)) << " ("<< top_level->datawrite <<")"<< endl; + out << " datarw = " << top_level->datarw << endl; + out << " datareq = " << top_level->datareq << endl; + out << " databs = " << top_level->databs << endl; + + out << endl; + out << "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx INST_MEM xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx" << endl; + + decode(top_level->instdataread,((unsigned int) ((sc_uint<32>)(top_level->instaddr))), out); + + out << " PC = 0x" << hex << setw(8) << setfill('0') << ((unsigned int)((sc_uint<32>)(top_level->instaddr))) << endl; + out << " InstDataRead = 0x" << hex << setw(8) << setfill('0') << (unsigned int) ((sc_uint<32>) (top_level->instdataread)) << " " << top_level->instdataread << endl; + + out << " instreq = " << top_level->instreq << endl; + + out << endl; + out << endl; + + + out << "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx MEMORY xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx" << endl; + + int temp, temp2, Start, Stop; + Start = Start_pos; + Stop = Finish_pos; + temp = (Start + (Stop - Start)/4); + temp2 = ((Stop - Start)/4); + + for(int n= Start; n < temp; n=n+4) + { + out << "[0x"<< hex << n << "] = 0x"<< hex << setw(8) << setfill('0') << top_level->datamem->x[(n >> 2)] << " "; + + out << "[0x"<< hex << (n + temp2) << "] = 0x"<< hex << setw(8) << setfill('0') << top_level->datamem->x[((n+temp2) >> 2)] << " "; + + out << "[0x"<< hex << (n + 2*temp2) << "] = 0x"<< hex << setw(8) << setfill('0') << top_level->datamem->x[((n+2*temp2) >> 2)] << " "; + + out << "[0x"<< hex << (n + 3*temp2) << "] = 0x"<< hex << setw(8) << setfill('0') << top_level->datamem->x[((n+3*temp2) >> 2)] << " " << endl; + + /*out << "cella [0x"<< hex << (n+8) << "] = "<< hex << setw(8) << setfill('0') << top_level->datamem->x[((n+8) >> 2)] << " "; + + out << "cella [0x"<< hex << (n+12) << "] = "<< hex << setw(8) << setfill('0') << top_level->datamem->x[((n+12) >> 2)] << endl;*/ + + } + + + + char buffer[256]; + ifstream examplefile ("GIGINO.txt"); + if (! examplefile.is_open()) + { cout << "Error opening file"; exit (1); } + + while (! examplefile.eof() ) + { + examplefile.getline (buffer,100); + fprintf (fp ,"%s\n", buffer); + } +} Index: tags/arelease/source/constants/tracce_per_gtkwave.cpp =================================================================== --- tags/arelease/source/constants/tracce_per_gtkwave.cpp (nonexistent) +++ tags/arelease/source/constants/tracce_per_gtkwave.cpp (revision 13) @@ -0,0 +1,112 @@ + sc_trace(trace_file, debug_level->top_level->in_clk, "clk"); + sc_trace(trace_file, debug_level->top_level->reset, "reset"); + sc_trace(trace_file, debug_level->top_level->instaddr, "instaddr"); + sc_trace(trace_file, debug_level->top_level->instdataread, "instdataread"); + sc_trace(trace_file, debug_level->top_level->instreq, "instreq"); + sc_trace(trace_file, debug_level->top_level->instrw, "instrw"); + sc_trace(trace_file, debug_level->top_level->insthold, "insthold"); + sc_trace(trace_file, debug_level->top_level->dataaddr, "dataaddr"); + sc_trace(trace_file, debug_level->top_level->dataread_m_dec, "dataread_m_dec"); + sc_trace(trace_file, debug_level->top_level->dataread_dec_cpu, "dataread_dec_cpu"); + sc_trace(trace_file, debug_level->top_level->datawrite, "datawrite"); + sc_trace(trace_file, debug_level->top_level->datareq, "datareq"); + sc_trace(trace_file, debug_level->top_level->datarw, "datarw"); + sc_trace(trace_file, debug_level->top_level->databs, "databs"); + sc_trace(trace_file, debug_level->top_level->datahold, "datahold"); + + sc_trace(trace_file, debug_level->top_level->risc->cpu->enable_pc, "enable_pc"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->enable_fetch, "enable_fetch"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->enable_decode, "enable_decode"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->enable_execute, "enable_execute"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->enable_memstage, "enable_memstage"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_exception, "if_exception"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id_exception, "id_exception"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex_exception, "ex_exception"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem_exception, "mem_exception"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->wb_exception, "wb_exception"); + + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->DBUS, "DBUS"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->data_addrl, "data_addrl"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->data_addrl, "data_addrs"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->ex_m_ovf_excep, "ex_m_ovf_excep"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->ex_m_syscall_exception, "ex_m_syscall_exception"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->ex_m_illegal_instruction, "ex_m_illegal_instruction"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->ex_m_inst_addrl, "ex_m_inst_addrl"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->mem->ex_m_IBUS, "ex_m_IBUS"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_id_instaddr, "if_id_instaddr"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id_ex_instaddr, "id_ex_instaddr"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->ex_m_instaddr, "ex_m_instaddr"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->m_wb_instaddr, "m_wb_instaddr"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->m_wb_dataaddr, "m_wb_dataaddr"); + sc_trace(trace_file, debug_level->top_level->risc->co0->cause, "cause"); + sc_trace(trace_file, debug_level->top_level->risc->co0->check_excep, "check_excep"); + sc_trace(trace_file, debug_level->top_level->risc->co0->to_EPC, "to_EPC"); + sc_trace(trace_file, debug_level->top_level->risc->co0->to_BadVAddr, "to_BadVAddr"); + //CP0 REGISTERS + sc_trace(trace_file, debug_level->top_level->risc->co0->cp0_r->cp0regs[8] , "cp0_regs[8]"); + sc_trace(trace_file, debug_level->top_level->risc->co0->cp0_r->cp0regs[14], "cp0_regs[14]"); + sc_trace(trace_file, debug_level->top_level->risc->co0->cp0_r->cp0regs[13], "cp0_regs[13]"); + sc_trace(trace_file, debug_level->top_level->risc->co0->cp0_r->cp0regs[12], "cp0_regs[12]"); + sc_trace(trace_file, debug_level->top_level->risc->co0->sspc->insthold, "sspc.insthold"); + sc_trace(trace_file, debug_level->top_level->risc->co0->sspc->new_pc, "sspc.new_pc"); + sc_trace(trace_file, debug_level->top_level->risc->co0->sspc->load_epc, "sspc.load_epc"); + sc_trace(trace_file, debug_level->top_level->risc->co0->sspc->check_excep, "sspc.check_excep"); + sc_trace(trace_file, debug_level->top_level->risc->co0->sspc->currentstate, "sspc.currentstate"); + sc_trace(trace_file, debug_level->top_level->risc->co0->sspc->nextstate, "sspc.nextstate"); + sc_trace(trace_file, debug_level->top_level->risc->co0->sspc->x_insthold, "sspc.x_insthold"); + sc_trace(trace_file, debug_level->top_level->risc->co0->sspc->in_clk, "sspc.in_clk"); + sc_trace(trace_file, debug_level->top_level->risc->co0->sspc->cp0_inst, "sspc.cp0_inst"); + sc_trace(trace_file, debug_level->top_level->risc->co0->sspc->EPC_FOR_RFE, "sspc.EPC_FOR_RFE"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_mux_fw2, "id.id_mux_fw2"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->id->id_sign_extend , "id.id_sign_extend"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->interrupt_signal, "interrupt_signal"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->m_wb_interrupt_signal, "m_wb_interrupt_signal"); + //sc_trace(trace_file, debug_level->top_level->risc->co0->excp->m_wb_interrupt_signal, "excp.m_wb_interrupt_signal"); + + + //PC_STAGE + sc_trace(trace_file, debug_level->top_level->risc->cpu->pc->enable_pc, "pc.enable_pc"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->pc->pc_in, "pc.pc_in"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->pc->pc_out, "pc.pc_out"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->pc->instaddr, "pc.instaddr"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->pc->instdatawrite, "pc.instdatawrite"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->pc->instreq, "pc.instreq"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->pc->instrw, "pc.instrw"); + + //IF_STAGE + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->pc_in, "if_s.pc_in"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->pc_out, "if_s.pc_out"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->id_new_pc, "if_s.id_new_pc"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->id_jmp_tar, "if_s.id_jmp_tar"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->id_ctrl, "if_s.id_ctrl"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->id_branch, "if_s.id_branch"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->instdataread, "if_s.instdataread"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->if_id_inst, "if_s.if_id_inst"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->if_id_next_pc, "if_s.if_id_next_pc"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->new_pc;, "if_s.new_pc;"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->load_epc, "if_s.load_epc"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->IBUS, "if_s.IBUS"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->inst_addrl, "if_s.inst_addrl"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->if_id_IBUS, "if_s.if_id_IBUS"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->if_id_inst_addrl, "if_s.if_id_inst_addrl"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->pc_if_instaddr, "if_s.pc_if_instaddr"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->if_exception, "if_s.if_exception"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->enable_fetch, "if_s.enable_fetch"); + sc_trace(trace_file, debug_level->top_level->risc->cpu->if_s->if_pc_add, "if_s.if_pc_add"); + + + + + + + + + + + + + + + + + \ No newline at end of file Index: tags/arelease/source/constants/avrucpackage.h =================================================================== --- tags/arelease/source/constants/avrucpackage.h (nonexistent) +++ tags/arelease/source/constants/avrucpackage.h (revision 13) @@ -0,0 +1,103 @@ +// +// $Id: avrucpackage.h,v 1.1.1.1 2006-01-31 10:55:27 igorloi Exp $ +// +#ifndef _AVRUCPACKAGE_H +#define _AVRUCPACKAGE_H +#include + +#define ext_mux_in_num 63 + +/* +type ext_mux_din_type is array(0 to ext_mux_in_num) of std_logic_vector(7 downto 0); +subtype ext_mux_en_type is std_logic_vector(0 to ext_mux_in_num); +*/ + +// I/O port addresses +#define IOAdrWidth 6 + +// I/O register file +#define RAMPZ_Address "111011" +#define SPL_Address "111101" +#define SPH_Address "111110" +#define SREG_Address "111111" + +// UART +#define UDR_Address "001100" +#define UBRR_Address "001001" +#define USR_Address "001011" +#define UCR_Address "001010" + +// Timer/Counter +#define TCCR0_Address "110011" +#define TCCR1A_Address "101111" +#define TCCR1B_Address "101110" +#define TCCR2_Address "100101" +#define ASSR_Address "110000" +#define TIMSK_Address "110111" +#define TIFR_Address "110110" +#define TCNT0_Address "110010" +#define TCNT2_Address "100100" +#define OCR0_Address "110001" +#define OCR2_Address "100011" +#define TCNT1H_Address "101101" +#define TCNT1L_Address "101100" +#define OCR1AH_Address "101011" +#define OCR1AL_Address "101010" +#define OCR1BH_Address "101001" +#define OCR1BL_Address "101000" +#define ICR1AH_Address "100111" +#define ICR1AL_Address "100110" + +// Service module +#define MCUCR_Address "110101" +#define EIMSK_Address "111001" +#define EIFR_Address "111000" +#define EICR_Address "111010" +#define MCUSR_Address "110100" +#define XDIV_Address "111100" + +// PORTA addresses +#define PORTA_Address "011001" +#define DDRA_Address "011010" +#define PINA_Address "011001" + +// PORTB addresses +#define PORTB_Address "011000" +#define DDRB_Address "010111" +#define PINB_Address "010110" + +// PORTC addresses +#define PORTC_Address "010101" + +// PORTD addresses +#define PORTD_Address "010010" +#define DDRD_Address "010001" +#define PIND_Address "010000" + +// PORTE addresses +#define PORTE_Address "000011" +#define DDRE_Address "000010" +#define PINE_Address "000001" + +// PORTF addresses +#define PINF_Address "000000" + +// Analog to digital converter +#define ADCL_Address "000100" +#define ADCH_Address "000101" +#define ADCSR_Address "000110" +#define ADMUX_Address "000111" + +// Analog comparator +#define ACSR_Address "001000" + +// For pm_fetch_dec + +// LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL PURPOSE REGISTER (R0-R31) 0x00..0x19 +#define const_ram_to_reg "00000000000" +// LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x20 0x3F +#define const_ram_to_io_a "00000000001" +// LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x20 0x3F +#define const_ram_to_io_b "00000000010" + +#endif Index: tags/arelease/source/constants/constants.h =================================================================== --- tags/arelease/source/constants/constants.h (nonexistent) +++ tags/arelease/source/constants/constants.h (revision 13) @@ -0,0 +1,175 @@ +// +// $Id: constants.h,v 1.1.1.1 2006-01-31 10:55:27 igorloi Exp $ +// +#ifndef _CONSTANTS_H +#define _CONSTANTS_H +// #include "config.h" +#include + +//#ifndef _DEBUG_ +//#define _DEBUG_ +//#endif + +#ifdef _DEBUG_ +#define PRINT(aa) cout << "MIPS: " << aa +#define PRINTLN(aa) cout << "MIPS: " << aa << endl +#define PRINT2(aa,bb) cout << "MIPS: " << aa << bb +#define PRINT2LN(aa,bb) cout << "MIPS: " << aa << bb << endl +#define PRINT3(aa,bb,cc) cout << "MIPS: " << aa << bb << cc +#define PRINT3LN(aa,bb,cc) cout << "MIPS: " << aa << bb << cc < > context_register; + + + //! Proccesor cycle count (9) + /*! + [31,0] Count + */ + // sc_signal > count_register; + + //! Timer interrupt control (11) + /*! + [31,0] Compare + */ + // sc_signal > compare_register; + + //! The Status register (12) + /*! + [31,28] CU3-CU0 + [27] RP + [26] FR + [25] RE + [24] MX + [23] PX + [22] BEV + [21] TS + [20] SR + [19] NMI + [15,8] IM7-IM0 + [7] KX + [6] SX + [5] UX + [4,3] KSU + [2] ERL + [1] EXL + [0] IE + Note: To enable interrupt => IE=1, EXL=0, ERL=0 (and Debug_DM=0 OBS: not implemented). + */ + // sc_signal > status_register; + + //! The Cause register (13) + /*! + 0[31] BD + [29,28] CE + [23] IV + [22] WP + [15,8] IP (6 hardware IP[7,2] and 2 software IP[1,0]) + [5,2] ExcCode + */ + // sc_signal > cause_register; + + + //! The EPC (Exception Program Counter) register (14) + /*! + [31,0] EPC + */ + // sc_signal > epc_register; + + + //! The PRID (Processor Revision Identifier) register (15) + /*! + [31,24] Company Option + [23,16] CompanyID + [15,8] ProcessorID + [7,0] Revision + */ + /// sc_signal > prid_register; + + + //! Configuration Register, Selection 0(16) + /*! + [31] M + [30,16] Impl + [15] BE + [14,13] AT + [12,10] AR + [9,7] MT + [2,0] K0 + */ + // sc_signal > config_register; + + + //! Old Instruction addr + /*! + This register is used to store previous instruction address. + */ + // sc_signal > id_ex_pc_in; + + +#endif Index: tags/arelease/source/constants/debug_signal.h =================================================================== --- tags/arelease/source/constants/debug_signal.h (nonexistent) +++ tags/arelease/source/constants/debug_signal.h (revision 13) @@ -0,0 +1,9 @@ +//File di configurazione del File di Log del Processore! + + +//Definisce l'indirizzo di start per la stampa su file delle locazioni di memoria +#define Start_pos 0x1000 + +//Definisce l'indirizzo di Finish per la stampa su file delle locazioni di memoria +#define Finish_pos 0x1080 + Index: tags/arelease/source/constants/avrconstants.h =================================================================== --- tags/arelease/source/constants/avrconstants.h (nonexistent) +++ tags/arelease/source/constants/avrconstants.h (revision 13) @@ -0,0 +1,88 @@ +// +// Excerpt from iom103.h +// +#ifndef _AVRCONSTANTS_H +#define _AVRCONSTANTS_H + + +/* Watchdog Timer Control Register */ +#define WDTCR 0x21 + +/* Timer2 Output Compare Register */ +#define OCR2 0x23 + +/* Timer/Counter 2 */ +#define TCNT2 0x24 + +/* Timer/Counter 2 Control register */ +#define TCCR2 0x25 + +/* T/C 1 Input Capture Register */ +#define ICR1L 0x26 +#define ICR1H 0x27 + +/* Timer/Counter1 Output Compare Register B */ +#define OCR1BL 0x28 +#define OCR1BH 0x29 + +/* Timer/Counter1 Output Compare Register A */ +#define OCR1AL 0x2A +#define OCR1AH 0x2B + +/* Timer/Counter 1 */ +#define TCNT1L 0x2C +#define TCNT1H 0x2D + +/* Timer/Counter 1 Control and Status Register */ +#define TCCR1B 0x2E + +/* Timer/Counter 1 Control Register */ +#define TCCR1A 0x2F + +/* Timer/Counter 0 Asynchronous Control & Status Register */ +#define ASSR 0x30 + +/* Output Compare Register 0 */ +#define OCR0 0x31 + +/* Timer/Counter 0 */ +#define TCNT0 0x32 + +/* Timer/Counter 0 Control Register */ +#define TCCR0 0x33 + +/* MCU Status Register */ +#define MCUSR 0x34 + +/* MCU general Control Register */ +#define MCUCR 0x35 + +/* Timer/Counter Interrupt Flag Register */ +#define TIFR 0x36 + +/* Timer/Counter Interrupt MaSK register */ +#define TIMSK 0x37 + +/* External Interrupt Flag Register */ +#define EIFR 0x38 + +/* External Interrupt MaSK register */ +#define EIMSK 0x39 + +/* External Interrupt Control Register */ +#define EICR 0x3A + +/* RAM Page Z select register */ +#define RAMPZ 0x3B + +/* XDIV Divide control register */ +#define XDIV 0x3C + +/* Stack Pointer */ +#define SPL 0x3D +#define SPH 0x3E + +/* Status REGister */ +#define SREG 0x3F + +#endif Index: tags/arelease/source/constants/config.h =================================================================== --- tags/arelease/source/constants/config.h (nonexistent) +++ tags/arelease/source/constants/config.h (revision 13) @@ -0,0 +1,220 @@ +#ifndef _CONFIG_H +#define _CONFIG_H + +/* + add Pipelined Multiplicator +*/ +//#define _MULT_PIPELINE_ + +/* + set the depth of the pipeline Multiplicator + For combinatorial Multiplier, set 0 +*/ +#define DEPTH_MULT_PIPE 3 + + +/*! + add ocp connection to the cpu +*/ +#define _OCP_ + +/* + * The starting address for PC upon RESET + */ +#define PC_START 0 + +/*! + Size of memory ramb4_s16_s16 +*/ +#define MEMSIZE 32768 +// #define _MEMOFF_ 492 + + +/*! + no speciel elements for synthesis or back ann +*/ +#define _HIGH_LEVEL_SIM_ 1 +#include + +/* + Write various debug output... + */ +#define _DEBUG_ 1 + +/*! + Write signal values with every clock cycle +*/ +#define DEBUG_SIGNALS 1 + +/* + Write instructions to output + */ +#define _DEBUG_INSTRUCTION_ 1 + +/* + Write ***...for each clock tick + */ +#define CLOCK_DEBUG 1 + +/* + Write regfile contents upon writes + */ +#define REGFILE_DEBUG 1 + +/* + Each clock cycle (cc), do a memory-dump to file... + */ +#define _CC_MEMDUMP_ 1 + +/* + Write PC (in ID stage) every cc. + */ +#define DEBUG_PC 1 + +/* + Write RAM inputs and outputs + */ +//#define _DEBUG_MEMORY_ 1 + + +/*! + Memory map + From: 0x7FFFFF00 + To : 0x7FFFFFFC +*/ +#define OCP_MAP "01111111111111111111111000000000" +#define OCP_MAP_STOP "01111111111111111111111111110100" +#define FD3_MAP "01111111111111111111111111111000" +#define STOP_CPU_MAP "01111111111111111111111111111100" + +/*! + Memory map + From: 0x7FFFFD00 + To : 0x7FFFFDFC +*/ +#define OCP_MAP_GCD "01111111111111111111110100000000" +#define OCP_MAP_STOP_GCD "01111111111111111111110111111100" + + +/* + Defines for including various stages of the pipeline in the trace-file. +*/ +#define SIGNAL_SC_CPU 1 +#define SIGNAL_PC_STAGE 1 +#define SIGNAL_IF_STAGE 1 +#define SIGNAL_ID_STAGE 1 +#define SIGNAL_EX_STAGE 1 +#define SIGNAL_MEM_STAGE 1 +#define SIGNAL_WB_STAGE 1 +#define SIGNAL_CP0 1 +#define SIGNAL_OCP 1 +#define SIGNAL_OCP_GCD 1 +#define SIGNAL_DATAMEM 1 + + +/* + Very special options for creating traces for Power Compiler + Don't define more than one of these at a time! +*/ +//#define SIGNAL_SC_CPU_INPUTS_ONLY 1 +//#define SIGNAL_PC_STAGE_INPUTS_ONLY 1 +//define SIGNAL_IF_STAGE_INPUTS_ONLY 1 +//#define SIGNAL_ID_STAGE_INPUTS_ONLY 1 +//#define SIGNAL_EX_STAGE_INPUTS_ONLY 1 +//#define SIGNAL_MEM_STAGE_INPUTS_ONLY 1 + +/* + Do not modify below! +*/ +#if defined(SIGNAL_SC_CPU_INPUTS_ONLY) +#undef SIGNAL_PC_STAGE +#undef SIGNAL_IF_STAGE +#undef SIGNAL_ID_STAGE +#undef SIGNAL_EX_STAGE +#undef SIGNAL_MEM_STAGE +#undef SIGNAL_WB_STAGE +#undef SIGNAL_CP0 +#undef SIGNAL_OCP +#undef SIGNAL_OCP_GCD +#undef SIGNAL_DATAMEM +#endif + +#if defined(SIGNAL_PC_STAGE_INPUTS_ONLY) +#undef SIGNAL_SC_CPU +#undef SIGNAL_IF_STAGE +#undef SIGNAL_ID_STAGE +#undef SIGNAL_EX_STAGE +#undef SIGNAL_MEM_STAGE +#undef SIGNAL_WB_STAGE +#undef SIGNAL_CP0 +#undef SIGNAL_OCP +#undef SIGNAL_OCP_GCD +#undef SIGNAL_DATAMEM +#endif + +#if defined(SIGNAL_IF_STAGE_INPUTS_ONLY) +#undef SIGNAL_SC_CPU +#undef SIGNAL_PC_STAGE +#undef SIGNAL_ID_STAGE +#undef SIGNAL_EX_STAGE +#undef SIGNAL_MEM_STAGE +#undef SIGNAL_WB_STAGE +#undef SIGNAL_CP0 +#undef SIGNAL_OCP +#undef SIGNAL_OCP_GCD +#undef SIGNAL_DATAMEM +#endif + +#if defined(SIGNAL_ID_STAGE_INPUTS_ONLY) +#undef SIGNAL_SC_CPU +#undef SIGNAL_PC_STAGE +#undef SIGNAL_IF_STAGE +#undef SIGNAL_EX_STAGE +#undef SIGNAL_MEM_STAGE +#undef SIGNAL_WB_STAGE +#undef SIGNAL_CP0 +#undef SIGNAL_OCP +#undef SIGNAL_OCP_GCD +#undef SIGNAL_DATAMEM +#endif + +#if defined(SIGNAL_EX_STAGE_INPUTS_ONLY) +#undef SIGNAL_SC_CPU +#undef SIGNAL_PC_STAGE +#undef SIGNAL_IF_STAGE +#undef SIGNAL_ID_STAGE +#undef SIGNAL_MEM_STAGE +#undef SIGNAL_WB_STAGE +#undef SIGNAL_CP0 +#undef SIGNAL_OCP +#undef SIGNAL_OCP_GCD +#undef SIGNAL_DATAMEM +#endif + +#if defined(SIGNAL_EX_STAGE_INPUTS_ONLY) +#undef SIGNAL_SC_CPU +#undef SIGNAL_PC_STAGE +#undef SIGNAL_IF_STAGE +#undef SIGNAL_ID_STAGE +#undef SIGNAL_MEM_STAGE +#undef SIGNAL_WB_STAGE +#undef SIGNAL_CP0 +#undef SIGNAL_OCP +#undef SIGNAL_OCP_GCD +#undef SIGNAL_DATAMEM +#endif + +#if defined(SIGNAL_MEM_STAGE_INPUTS_ONLY) +#undef SIGNAL_SC_CPU +#undef SIGNAL_PC_STAGE +#undef SIGNAL_IF_STAGE +#undef SIGNAL_ID_STAGE +#undef SIGNAL_EX_STAGE +#undef SIGNAL_WB_STAGE +#undef SIGNAL_CP0 +#undef SIGNAL_OCP +#undef SIGNAL_OCP_GCD +#undef SIGNAL_DATAMEM +#endif + +#endif Index: tags/arelease/source/constants/mipsconstants.h =================================================================== --- tags/arelease/source/constants/mipsconstants.h (nonexistent) +++ tags/arelease/source/constants/mipsconstants.h (revision 13) @@ -0,0 +1,480 @@ +// +// $Id: mipsconstants.h,v 1.1.1.1 2006-01-31 10:55:27 igorloi Exp $ +// Excerpt from mipsregs.h from the Linux kernel! +// +#ifndef _MIPSCONSTANTS_H +#define _MIPSCONSTANTS_H + +/* + * Coprocessor 0 register names + */ +#define CP0_INDEX 0 +#define CP0_RANDOM 1 +#define CP0_ENTRYLO0 2 +#define CP0_ENTRYLO1 3 +#define CP0_CONF 3 +#define CP0_CONTEXT 4 +#define CP0_PAGEMASK 5 +#define CP0_WIRED 6 +#define CP0_INFO 7 +#define CP0_BADVADDR 8 +#define CP0_COUNT 9 +#define CP0_ENTRYHI 10 +#define CP0_COMPARE 11 +#define CP0_STATUS 12 +#define CP0_CAUSE 13 +#define CP0_EPC 14 +#define CP0_PRID 15 +#define CP0_CONFIG 16 +#define CP0_LLADDR 17 +#define CP0_WATCHLO 18 +#define CP0_WATCHHI 19 +#define CP0_XCONTEXT 20 +#define CP0_FRAMEMASK 21 +#define CP0_DIAGNOSTIC 22 +#define CP0_DEBUG 23 +#define CP0_DEPC 24 +#define CP0_PERFORMANCE 25 +#define CP0_ECC 26 +#define CP0_CACHEERR 27 +#define CP0_TAGLO 28 +#define CP0_TAGHI 29 +#define CP0_ERROREPC 30 +#define CP0_DESAVE 31 + +/* + * R4640/R4650 cp0 register names. These registers are listed + * here only for completeness; without MMU these CPUs are not useable + * by Linux. A future ELKS port might take make Linux run on them + * though ... + */ +#define CP0_IBASE $0 +#define CP0_IBOUND $1 +#define CP0_DBASE $2 +#define CP0_DBOUND $3 +#define CP0_CALG $17 +#define CP0_IWATCH $18 +#define CP0_DWATCH $19 + +/* + * Coprocessor 0 Set 1 register names + */ +#define CP0_S1_DERRADDR0 $26 +#define CP0_S1_DERRADDR1 $27 +#define CP0_S1_INTCONTROL $20 + +/* + * TX39 Series + */ +#define CP0_TX39_CACHE $7 + +/* + * Coprocessor 1 (FPU) register names + */ +#define CP1_REVISION $0 +#define CP1_STATUS $31 + +/* + * FPU Status Register Values + */ +/* + * Status Register Values + */ + +#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ +#define FPU_CSR_COND 0x00800000 /* $fcc0 */ +#define FPU_CSR_COND0 0x00800000 /* $fcc0 */ +#define FPU_CSR_COND1 0x02000000 /* $fcc1 */ +#define FPU_CSR_COND2 0x04000000 /* $fcc2 */ +#define FPU_CSR_COND3 0x08000000 /* $fcc3 */ +#define FPU_CSR_COND4 0x10000000 /* $fcc4 */ +#define FPU_CSR_COND5 0x20000000 /* $fcc5 */ +#define FPU_CSR_COND6 0x40000000 /* $fcc6 */ +#define FPU_CSR_COND7 0x80000000 /* $fcc7 */ + +/* + * X the exception cause indicator + * E the exception enable + * S the sticky/flag bit +*/ +#define FPU_CSR_ALL_X 0x0003f000 +#define FPU_CSR_UNI_X 0x00020000 +#define FPU_CSR_INV_X 0x00010000 +#define FPU_CSR_DIV_X 0x00008000 +#define FPU_CSR_OVF_X 0x00004000 +#define FPU_CSR_UDF_X 0x00002000 +#define FPU_CSR_INE_X 0x00001000 + +#define FPU_CSR_ALL_E 0x00000f80 +#define FPU_CSR_INV_E 0x00000800 +#define FPU_CSR_DIV_E 0x00000400 +#define FPU_CSR_OVF_E 0x00000200 +#define FPU_CSR_UDF_E 0x00000100 +#define FPU_CSR_INE_E 0x00000080 + +#define FPU_CSR_ALL_S 0x0000007c +#define FPU_CSR_INV_S 0x00000040 +#define FPU_CSR_DIV_S 0x00000020 +#define FPU_CSR_OVF_S 0x00000010 +#define FPU_CSR_UDF_S 0x00000008 +#define FPU_CSR_INE_S 0x00000004 + +/* rounding mode */ +#define FPU_CSR_RN 0x0 /* nearest */ +#define FPU_CSR_RZ 0x1 /* towards zero */ +#define FPU_CSR_RU 0x2 /* towards +Infinity */ +#define FPU_CSR_RD 0x3 /* towards -Infinity */ + + +/* + * Values for PageMask register + */ +#ifdef CONFIG_CPU_VR41XX + +/* Why doesn't stupidity hurt ... */ + +#define PM_1K 0x00000000 +#define PM_4K 0x00001800 +#define PM_16K 0x00007800 +#define PM_64K 0x0001f800 +#define PM_256K 0x0007f800 + +#else + +#define PM_4K 0x00000000 +#define PM_16K 0x00006000 +#define PM_64K 0x0001e000 +#define PM_256K 0x0007e000 +#define PM_1M 0x001fe000 +#define PM_4M 0x007fe000 +#define PM_16M 0x01ffe000 +#define PM_64M 0x07ffe000 +#define PM_256M 0x1fffe000 + +#endif + +/* + * Values used for computation of new tlb entries + */ +#define PL_4K 12 +#define PL_16K 14 +#define PL_64K 16 +#define PL_256K 18 +#define PL_1M 20 +#define PL_4M 22 +#define PL_16M 24 +#define PL_64M 26 +#define PL_256M 28 + +/* + * R4x00 interrupt enable / cause bits + */ +#define IE_SW0 (_ULCAST_(1) << 8) +#define IE_SW1 (_ULCAST_(1) << 9) +#define IE_IRQ0 (_ULCAST_(1) << 10) +#define IE_IRQ1 (_ULCAST_(1) << 11) +#define IE_IRQ2 (_ULCAST_(1) << 12) +#define IE_IRQ3 (_ULCAST_(1) << 13) +#define IE_IRQ4 (_ULCAST_(1) << 14) +#define IE_IRQ5 (_ULCAST_(1) << 15) + +/* + * R4x00 interrupt cause bits + */ +#define C_SW0 (_ULCAST_(1) << 8) +#define C_SW1 (_ULCAST_(1) << 9) +#define C_IRQ0 (_ULCAST_(1) << 10) +#define C_IRQ1 (_ULCAST_(1) << 11) +#define C_IRQ2 (_ULCAST_(1) << 12) +#define C_IRQ3 (_ULCAST_(1) << 13) +#define C_IRQ4 (_ULCAST_(1) << 14) +#define C_IRQ5 (_ULCAST_(1) << 15) + +/* + * Bitfields in the R4xx0 cp0 status register + */ +#define ST0_IE 0x00000001 +#define ST0_EXL 0x00000002 +#define ST0_ERL 0x00000004 +#define ST0_KSU 0x00000018 +# define KSU_USER 0x00000010 +# define KSU_SUPERVISOR 0x00000008 +# define KSU_KERNEL 0x00000000 +#define ST0_UX 0x00000020 +#define ST0_SX 0x00000040 +#define ST0_KX 0x00000080 +#define ST0_DE 0x00010000 +#define ST0_CE 0x00020000 + +/* + * Bitfields in the R[23]000 cp0 status register. + */ +#define ST0_IEC 0x00000001 +#define ST0_KUC 0x00000002 +#define ST0_IEP 0x00000004 +#define ST0_KUP 0x00000008 +#define ST0_IEO 0x00000010 +#define ST0_KUO 0x00000020 +/* bits 6 & 7 are reserved on R[23]000 */ +#define ST0_ISC 0x00010000 +#define ST0_SWC 0x00020000 +#define ST0_CM 0x00080000 + +/* + * Bits specific to the R4640/R4650 + */ +#define ST0_UM (_ULCAST_(1) << 4) +#define ST0_IL (_ULCAST_(1) << 23) +#define ST0_DL (_ULCAST_(1) << 24) + +/* + * Bitfields in the TX39 family CP0 Configuration Register 3 + */ +#define TX39_CONF_ICS_SHIFT 19 +#define TX39_CONF_ICS_MASK 0x00380000 +#define TX39_CONF_ICS_1KB 0x00000000 +#define TX39_CONF_ICS_2KB 0x00080000 +#define TX39_CONF_ICS_4KB 0x00100000 +#define TX39_CONF_ICS_8KB 0x00180000 +#define TX39_CONF_ICS_16KB 0x00200000 + +#define TX39_CONF_DCS_SHIFT 16 +#define TX39_CONF_DCS_MASK 0x00070000 +#define TX39_CONF_DCS_1KB 0x00000000 +#define TX39_CONF_DCS_2KB 0x00010000 +#define TX39_CONF_DCS_4KB 0x00020000 +#define TX39_CONF_DCS_8KB 0x00030000 +#define TX39_CONF_DCS_16KB 0x00040000 + +#define TX39_CONF_CWFON 0x00004000 +#define TX39_CONF_WBON 0x00002000 +#define TX39_CONF_RF_SHIFT 10 +#define TX39_CONF_RF_MASK 0x00000c00 +#define TX39_CONF_DOZE 0x00000200 +#define TX39_CONF_HALT 0x00000100 +#define TX39_CONF_LOCK 0x00000080 +#define TX39_CONF_ICE 0x00000020 +#define TX39_CONF_DCE 0x00000010 +#define TX39_CONF_IRSIZE_SHIFT 2 +#define TX39_CONF_IRSIZE_MASK 0x0000000c +#define TX39_CONF_DRSIZE_SHIFT 0 +#define TX39_CONF_DRSIZE_MASK 0x00000003 + +/* + * Status register bits available in all MIPS CPUs. + */ +#define ST0_IM 0x0000ff00 +#define STATUSB_IP0 8 +#define STATUSF_IP0 (_ULCAST_(1) << 8) +#define STATUSB_IP1 9 +#define STATUSF_IP1 (_ULCAST_(1) << 9) +#define STATUSB_IP2 10 +#define STATUSF_IP2 (_ULCAST_(1) << 10) +#define STATUSB_IP3 11 +#define STATUSF_IP3 (_ULCAST_(1) << 11) +#define STATUSB_IP4 12 +#define STATUSF_IP4 (_ULCAST_(1) << 12) +#define STATUSB_IP5 13 +#define STATUSF_IP5 (_ULCAST_(1) << 13) +#define STATUSB_IP6 14 +#define STATUSF_IP6 (_ULCAST_(1) << 14) +#define STATUSB_IP7 15 +#define STATUSF_IP7 (_ULCAST_(1) << 15) +#define STATUSB_IP8 0 +#define STATUSF_IP8 (_ULCAST_(1) << 0) +#define STATUSB_IP9 1 +#define STATUSF_IP9 (_ULCAST_(1) << 1) +#define STATUSB_IP10 2 +#define STATUSF_IP10 (_ULCAST_(1) << 2) +#define STATUSB_IP11 3 +#define STATUSF_IP11 (_ULCAST_(1) << 3) +#define STATUSB_IP12 4 +#define STATUSF_IP12 (_ULCAST_(1) << 4) +#define STATUSB_IP13 5 +#define STATUSF_IP13 (_ULCAST_(1) << 5) +#define STATUSB_IP14 6 +#define STATUSF_IP14 (_ULCAST_(1) << 6) +#define STATUSB_IP15 7 +#define STATUSF_IP15 (_ULCAST_(1) << 7) +#define ST0_CH 0x00040000 +#define ST0_SR 0x00100000 +#define ST0_TS 0x00200000 +#define ST0_BEV 0x00400000 +#define ST0_RE 0x02000000 +#define ST0_FR 0x04000000 +#define ST0_CU 0xf0000000 +#define ST0_CU0 0x10000000 +#define ST0_CU1 0x20000000 +#define ST0_CU2 0x40000000 +#define ST0_CU3 0x80000000 +#define ST0_XX 0x80000000 /* MIPS IV naming */ + +/* + * Bitfields and bit numbers in the coprocessor 0 cause register. + * + * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. + */ +#define CAUSEB_EXCCODE 2 +#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) +#define CAUSEB_IP 8 +#define CAUSEF_IP (_ULCAST_(255) << 8) +#define CAUSEB_IP0 8 +#define CAUSEF_IP0 (_ULCAST_(1) << 8) +#define CAUSEB_IP1 9 +#define CAUSEF_IP1 (_ULCAST_(1) << 9) +#define CAUSEB_IP2 10 +#define CAUSEF_IP2 (_ULCAST_(1) << 10) +#define CAUSEB_IP3 11 +#define CAUSEF_IP3 (_ULCAST_(1) << 11) +#define CAUSEB_IP4 12 +#define CAUSEF_IP4 (_ULCAST_(1) << 12) +#define CAUSEB_IP5 13 +#define CAUSEF_IP5 (_ULCAST_(1) << 13) +#define CAUSEB_IP6 14 +#define CAUSEF_IP6 (_ULCAST_(1) << 14) +#define CAUSEB_IP7 15 +#define CAUSEF_IP7 (_ULCAST_(1) << 15) +#define CAUSEB_IV 23 +#define CAUSEF_IV (_ULCAST_(1) << 23) +#define CAUSEB_CE 28 +#define CAUSEF_CE (_ULCAST_(3) << 28) +#define CAUSEB_BD 31 +#define CAUSEF_BD (_ULCAST_(1) << 31) + +/* + * Bits in the coprocessor 0 config register. + */ +/* Generic bits. */ +#define CONF_CM_CACHABLE_NO_WA 0 +#define CONF_CM_CACHABLE_WA 1 +#define CONF_CM_UNCACHED 2 +#define CONF_CM_CACHABLE_NONCOHERENT 3 +#define CONF_CM_CACHABLE_CE 4 +#define CONF_CM_CACHABLE_COW 5 +#define CONF_CM_CACHABLE_CUW 6 +#define CONF_CM_CACHABLE_ACCELERATED 7 +#define CONF_CM_CMASK 7 +#define CONF_BE (_ULCAST_(1) << 15) + +/* Bits common to various processors. */ +#define CONF_CU (_ULCAST_(1) << 3) +#define CONF_DB (_ULCAST_(1) << 4) +#define CONF_IB (_ULCAST_(1) << 5) +#define CONF_DC (_ULCAST_(7) << 6) +#define CONF_IC (_ULCAST_(7) << 9) +#define CONF_EB (_ULCAST_(1) << 13) +#define CONF_EM (_ULCAST_(1) << 14) +#define CONF_SM (_ULCAST_(1) << 16) +#define CONF_SC (_ULCAST_(1) << 17) +#define CONF_EW (_ULCAST_(3) << 18) +#define CONF_EP (_ULCAST_(15)<< 24) +#define CONF_EC (_ULCAST_(7) << 28) +#define CONF_CM (_ULCAST_(1) << 31) + +/* Bits specific to the R4xx0. */ +#define R4K_CONF_SW (_ULCAST_(1) << 20) +#define R4K_CONF_SS (_ULCAST_(1) << 21) +#define R4K_CONF_SB (_ULCAST_(3) << 22) + +/* Bits specific to the R5000. */ +#define R5K_CONF_SE (_ULCAST_(1) << 12) +#define R5K_CONF_SS (_ULCAST_(3) << 20) + +/* Bits specific to the R10000. */ +#define R10K_CONF_DN (_ULCAST_(3) << 3) +#define R10K_CONF_CT (_ULCAST_(1) << 5) +#define R10K_CONF_PE (_ULCAST_(1) << 6) +#define R10K_CONF_PM (_ULCAST_(3) << 7) +#define R10K_CONF_EC (_ULCAST_(15)<< 9) +#define R10K_CONF_SB (_ULCAST_(1) << 13) +#define R10K_CONF_SK (_ULCAST_(1) << 14) +#define R10K_CONF_SS (_ULCAST_(7) << 16) +#define R10K_CONF_SC (_ULCAST_(7) << 19) +#define R10K_CONF_DC (_ULCAST_(7) << 26) +#define R10K_CONF_IC (_ULCAST_(7) << 29) + +/* Bits specific to the VR41xx. */ +#define VR41_CONF_CS (_ULCAST_(1) << 12) +#define VR41_CONF_M16 (_ULCAST_(1) << 20) +#define VR41_CONF_AD (_ULCAST_(1) << 23) + +/* Bits specific to the R30xx. */ +#define R30XX_CONF_FDM (_ULCAST_(1) << 19) +#define R30XX_CONF_REV (_ULCAST_(1) << 22) +#define R30XX_CONF_AC (_ULCAST_(1) << 23) +#define R30XX_CONF_RF (_ULCAST_(1) << 24) +#define R30XX_CONF_HALT (_ULCAST_(1) << 25) +#define R30XX_CONF_FPINT (_ULCAST_(7) << 26) +#define R30XX_CONF_DBR (_ULCAST_(1) << 29) +#define R30XX_CONF_SB (_ULCAST_(1) << 30) +#define R30XX_CONF_LOCK (_ULCAST_(1) << 31) + +/* Bits specific to the TX49. */ +#define TX49_CONF_DC (_ULCAST_(1) << 16) +#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ +#define TX49_CONF_HALT (_ULCAST_(1) << 18) +#define TX49_CONF_CWFON (_ULCAST_(1) << 27) + +/* Bits specific to the MIPS32/64 PRA. */ +#define MIPS_CONF_MT (_ULCAST_(7) << 7) +#define MIPS_CONF_AR (_ULCAST_(7) << 10) +#define MIPS_CONF_AT (_ULCAST_(3) << 13) +#define MIPS_CONF_M (_ULCAST_(1) << 31) + +/* + * R10000 performance counter definitions. + * + * FIXME: The R10000 performance counter opens a nice way to implement CPU + * time accounting with a precission of one cycle. I don't have + * R10000 silicon but just a manual, so ... + */ + +/* + * Events counted by counter #0 + */ +#define CE0_CYCLES 0 +#define CE0_INSN_ISSUED 1 +#define CE0_LPSC_ISSUED 2 +#define CE0_S_ISSUED 3 +#define CE0_SC_ISSUED 4 +#define CE0_SC_FAILED 5 +#define CE0_BRANCH_DECODED 6 +#define CE0_QW_WB_SECONDARY 7 +#define CE0_CORRECTED_ECC_ERRORS 8 +#define CE0_ICACHE_MISSES 9 +#define CE0_SCACHE_I_MISSES 10 +#define CE0_SCACHE_I_WAY_MISSPREDICTED 11 +#define CE0_EXT_INTERVENTIONS_REQ 12 +#define CE0_EXT_INVALIDATE_REQ 13 +#define CE0_VIRTUAL_COHERENCY_COND 14 +#define CE0_INSN_GRADUATED 15 + +/* + * Events counted by counter #1 + */ +#define CE1_CYCLES 0 +#define CE1_INSN_GRADUATED 1 +#define CE1_LPSC_GRADUATED 2 +#define CE1_S_GRADUATED 3 +#define CE1_SC_GRADUATED 4 +#define CE1_FP_INSN_GRADUATED 5 +#define CE1_QW_WB_PRIMARY 6 +#define CE1_TLB_REFILL 7 +#define CE1_BRANCH_MISSPREDICTED 8 +#define CE1_DCACHE_MISS 9 +#define CE1_SCACHE_D_MISSES 10 +#define CE1_SCACHE_D_WAY_MISSPREDICTED 11 +#define CE1_EXT_INTERVENTION_HITS 12 +#define CE1_EXT_INVALIDATE_REQ 13 +#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14 +#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15 + +/* + * These flags define in which priviledge mode the counters count events + */ +#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */ +#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */ +#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */ +#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */ + +#endif Index: tags/arelease/source/constants/elf.h =================================================================== --- tags/arelease/source/constants/elf.h (nonexistent) +++ tags/arelease/source/constants/elf.h (revision 13) @@ -0,0 +1,120 @@ +#ifndef _LINUX_ELF_H +#define _LINUX_ELF_H + +/* 32-bit ELF base types. */ +typedef unsigned long Elf32_Addr; +typedef unsigned short Elf32_Half; +typedef unsigned long Elf32_Off; +// typedef __s32 Elf32_Sword; +typedef unsigned long Elf32_Word; + +/* +typedef struct dynamic{ + Elf32_Sword d_tag; + union{ + Elf32_Sword d_val; + Elf32_Addr d_ptr; + } d_un; +} Elf32_Dyn; + +typedef struct elf32_rel { + Elf32_Addr r_offset; + Elf32_Word r_info; +} Elf32_Rel; + +typedef struct elf32_rela{ + Elf32_Addr r_offset; + Elf32_Word r_info; + Elf32_Sword r_addend; +} Elf32_Rela; +*/ + +typedef struct elf32_sym{ + Elf32_Word st_name; + Elf32_Addr st_value; + Elf32_Word st_size; + unsigned char st_info; + unsigned char st_other; + Elf32_Half st_shndx; +} Elf32_Sym; + +#define EI_NIDENT 16 + +typedef struct elf32_hdr{ + unsigned char e_ident[EI_NIDENT]; + Elf32_Half e_type; + Elf32_Half e_machine; + Elf32_Word e_version; + Elf32_Addr e_entry; /* Entry point */ + Elf32_Off e_phoff; + Elf32_Off e_shoff; + Elf32_Word e_flags; + Elf32_Half e_ehsize; + Elf32_Half e_phentsize; + Elf32_Half e_phnum; + Elf32_Half e_shentsize; + Elf32_Half e_shnum; + Elf32_Half e_shstrndx; +} Elf32_Ehdr; + +/* These constants define the permissions on sections in the program + header, p_flags. */ +#define PF_R 0x4 +#define PF_W 0x2 +#define PF_X 0x1 + +typedef struct elf32_phdr{ + Elf32_Word p_type; + Elf32_Off p_offset; + Elf32_Addr p_vaddr; + Elf32_Addr p_paddr; + Elf32_Word p_filesz; + Elf32_Word p_memsz; + Elf32_Word p_flags; + Elf32_Word p_align; +} Elf32_Phdr; + +typedef struct { + Elf32_Word sh_name; + Elf32_Word sh_type; + Elf32_Word sh_flags; + Elf32_Addr sh_addr; + Elf32_Off sh_offset; + Elf32_Word sh_size; + Elf32_Word sh_link; + Elf32_Word sh_info; + Elf32_Word sh_addralign; + Elf32_Word sh_entsize; +} Elf32_Shdr; + +/* sh_type */ +#define SHT_NULL 0 +#define SHT_PROGBITS 1 +#define SHT_SYMTAB 2 +#define SHT_STRTAB 3 +#define SHT_RELA 4 +#define SHT_HASH 5 +#define SHT_DYNAMIC 6 +#define SHT_NOTE 7 +#define SHT_NOBITS 8 +#define SHT_REL 9 +#define SHT_SHLIB 10 +#define SHT_DYNSYM 11 +#define SHT_NUM 12 +#define SHT_LOPROC 0x70000000 +#define SHT_HIPROC 0x7fffffff +#define SHT_LOUSER 0x80000000 +#define SHT_HIUSER 0xffffffff +#define SHT_MIPS_LIST 0x70000000 +#define SHT_MIPS_CONFLICT 0x70000002 +#define SHT_MIPS_GPTAB 0x70000003 +#define SHT_MIPS_UCODE 0x70000004 + +/* sh_flags */ +#define SHF_WRITE 0x1 +#define SHF_ALLOC 0x2 +#define SHF_EXECINSTR 0x4 +#define SHF_MASKPROC 0xf0000000 +#define SHF_MIPS_GPREL 0x10000000 + +#endif /* _LINUX_ELF_H */ Index: tags/arelease/source/Makefile =================================================================== --- tags/arelease/source/Makefile (nonexistent) +++ tags/arelease/source/Makefile (revision 13) @@ -0,0 +1,59 @@ +#Makefile Mips R2000 developed by Igor Loi +#v 1.0 2004/12/05 21:42 Diee Cagliari +# Thanks to Nicolai Ascanium from IMM + +TARGET_ARCH = linux + +CC = g++ +OPT = -O3 +DEBUG = -g +OTHER = -Wall +CFLAGS = $(OPT) $(OTHER) +# CFLAGS = $(DEBUG) $(OTHER) +MODULE = mips2 +SRCS = embedded_perif/decoder.cpp embedded_perif/mux.cpp top.cpp \ + cpu/pc_stage.cpp cpu/pc_stage/reg_pc.cpp \ + \ + cpu/if_stage.cpp cpu/if_stage/reg_if.cpp cpu/if_stage/add.cpp cpu/if_stage/select_next_pc.cpp \ + cpu/if_stage/if_ctrl.cpp\ + cpu/id_stage/mux_writeregister.cpp cpu/id_stage/sign_extend.cpp cpu/id_stage/add_new_pc.cpp \ + cpu/id_stage/mux_forward_select.cpp cpu/id_stage/mux_jump.cpp cpu/id_stage/mux_alu1.cpp \ + cpu/id_stage/mux_alu2.cpp cpu/id_stage/comparator.cpp cpu/id_stage/forwarding_control.cpp \ + cpu/id_stage/reg_id.cpp cpu/id_stage/control.cpp cpu/id_stage/regfile_high.cpp \ + cpu/id_stage/decode_ctrl.cpp cpu/id_stage.cpp \ + cpu/ex_stage/alu.cpp cpu/ex_stage/multiply.cpp cpu/ex_stage/backwrite.cpp cpu/ex_stage/reg_ex.cpp \ + cpu/ex_stage/mux_lo.cpp cpu/ex_stage/mux_hi.cpp cpu/ex_stage/mux_rd.cpp cpu/ex_stage/execute_ctrl.cpp \ + cpu/ex_stage/fsm.cpp cpu/ex_stage.cpp \ + cpu/mem_stage.cpp cpu/mem_stage/select_mem.cpp cpu/mem_stage/multiplexer_mem.cpp \ + cpu/mem_stage/reg_mem.cpp cpu/mem_stage/memstage_ctrl.cpp cpu/mem_stage/mux_interrupt.cpp \ + cpu/mem_stage/flag_interr.cpp\ + cpu/cp0.cpp cpu/cp0/set_stop_pc.cpp cpu/cp0/exception.cpp cpu/cp0/cp0_register.cpp \ + cpu/sc_cpu.cpp cpu/sc_risc.cpp generators/reset_gen.cpp generators/timer.cpp cpu/enable_stage.cpp \ + cpu/writeback_ctrl.cpp cpu/mux_instaddr.cpp cpu/or_gate.cpp\ + memory/memory2.cpp \ + main.cpp top_debug.cpp + +OBJS = $(SRCS:.cpp=.o) +DEPS = $(SRCS:.cpp=.d) + + +%.o : %.cpp + $(CC) $(INCDIR) $(LIBDIR) $(EXTRA) $(CFLAGS) -c -o $@ $< + +%.d: %.cpp + set -e; $(CC) -MM $(INCDIR) $(LIBDIR) $(CFLAGS) $(EXTRA) $< | sed 's/\($*\)\.o[ :]*/\1.o $@ : /g' > $@; \ + [ -s $@ ] || rm -f $@ + +%.o : %.cc + $(CC) $(INCDIR) $(LIBDIR) $(EXTRA) $(CFLAGS) -c -o $@ $< + +%.d: %.cc + set -e; $(CC) -MM $(INCDIR) $(LIBDIR) $(CFLAGS) $(EXTRA) $< | sed 's/\($*\)\.o[ :]*/\1.o $@ : /g' > $@; \ + [ -s $@ ] || rm -f $@ + + +$(MODULE): $(OBJS) + $(CC) $(CFLAGS) $(INCDIR) $(LIBDIR) -o $@ $(OBJS) $(LIBS) 2>&1 | c++filt + + +include ./Makefile.defs Index: tags/arelease/source/Makefile.defs =================================================================== --- tags/arelease/source/Makefile.defs (nonexistent) +++ tags/arelease/source/Makefile.defs (revision 13) @@ -0,0 +1,33 @@ +## Variable that points to SystemC installation path +SYSTEMC = /home/chester/Desktop/systemc-2.0.1 + + +INCDIR = -I. -I.. -I$(SYSTEMC)/include +LIBDIR = -L. -L.. -L$(SYSTEMC)/lib-$(TARGET_ARCH) + +LIBS = -lsystemc -lm $(EXTRA_LIBS) + + +EXE = $(MODULE).x + +.SUFFIXES: .cc .cpp .o .x + +$(EXE): $(OBJS) $(SYSTEMC)/lib-$(TARGET_ARCH)/libsystemc.a + $(CC) $(CFLAGS) $(INCDIR) $(LIBDIR) -o $@ $(OBJS) $(LIBS) 2>&1 | c++filt + +.cpp.o: + $(CC) $(CFLAGS) $(INCDIR) -c $< + +.cc.o: + $(CC) $(CFLAGS) $(INCDIR) -c $< + +clean:: + rm -f $(OBJS) *~ $(EXE) core + +ultraclean: clean + rm -f Makefile.deps + +Makefile.deps: +# $(CC) $(CFLAGS) $(INCDIR) -M $(SRCS) >> Makefile.deps + +#include Makefile.deps Index: tags/arelease/source/embedded_perif/mux.h =================================================================== --- tags/arelease/source/embedded_perif/mux.h (nonexistent) +++ tags/arelease/source/embedded_perif/mux.h (revision 13) @@ -0,0 +1,24 @@ +// Multiplexer 8 -> 1 +// V 1.0 +// Diee Cagliari + +#include + +SC_MODULE(mux) +{ + sc_in > in_0, in_1, in_2, in_3, in_4, in_5, in_6, in_7; + sc_out > out_mux; + + sc_in > sel; + + void do_mux(); + + SC_CTOR(mux) + { + SC_METHOD(do_mux); + sensitive << in_0 << in_1 << in_2 << in_3 << in_4 << in_5 << in_6 << in_7; + sensitive << sel; + + } +}; + Index: tags/arelease/source/embedded_perif/amba_interface.cpp =================================================================== --- tags/arelease/source/embedded_perif/amba_interface.cpp (nonexistent) +++ tags/arelease/source/embedded_perif/amba_interface.cpp (revision 13) @@ -0,0 +1 @@ + Index: tags/arelease/source/embedded_perif/amba_interface.h =================================================================== --- tags/arelease/source/embedded_perif/amba_interface.h (nonexistent) +++ tags/arelease/source/embedded_perif/amba_interface.h (revision 13) @@ -0,0 +1,20 @@ +#include "systemc.h" + +SC_MODULE(amba_interface) +{ + sc_in in_clk; + sc_in reset; + + sc_out > dataread; + sc_in > datawrite; + sc_in datarw; + sc_in datareq; + sc_in > dataaddr; + sc_in > databs; + sc_out datahold; + + SC_CTOR(amba_interface) + { + + } +}; Index: tags/arelease/source/embedded_perif/decoder.cpp =================================================================== --- tags/arelease/source/embedded_perif/decoder.cpp (nonexistent) +++ tags/arelease/source/embedded_perif/decoder.cpp (revision 13) @@ -0,0 +1,34 @@ +#include "decoder.h" + +void decoder::do_decoder() +{ + sc_uint<32> uaddr; + uaddr = dataaddr.read(); + + switch(uaddr) + { + case 0x00006000: sel.write("001"); + break; + + case 0x00006004: sel.write("010"); + break; + + case 0x00006008: sel.write("011"); + break; + + case 0x0000600c: sel.write("100"); + break; + + case 0x00006010: sel.write("101"); + break; + + case 0x00006014: sel.write("110"); + break; + + case 0x00006018: sel.write("111"); + break; + + default: sel.write("000"); + break; + } +} Index: tags/arelease/source/embedded_perif/mux.cpp =================================================================== --- tags/arelease/source/embedded_perif/mux.cpp (nonexistent) +++ tags/arelease/source/embedded_perif/mux.cpp (revision 13) @@ -0,0 +1,37 @@ +#include "mux.h" + +void mux::do_mux() +{ + sc_uint<3> usel; + usel = sel.read(); + + switch(usel) + { + case 0: out_mux.write(in_0); + break; + + case 1: out_mux.write(in_1); + break; + + case 2: out_mux.write(in_2); + break; + + case 3: out_mux.write(in_3); + break; + + case 4: out_mux.write(in_4); + break; + + case 5: out_mux.write(in_5); + break; + + case 6: out_mux.write(in_6); + break; + + case 7: out_mux.write(in_7); + break; + + default: out_mux.write(in_0); + break; + } +} Index: tags/arelease/source/embedded_perif/decoder.h =================================================================== --- tags/arelease/source/embedded_perif/decoder.h (nonexistent) +++ tags/arelease/source/embedded_perif/decoder.h (revision 13) @@ -0,0 +1,21 @@ +// Modulo decoder +// Diee Cagliari +// V 1.0 + +#include + +SC_MODULE(decoder) +{ + sc_in > dataaddr; + + sc_out > sel; + + void do_decoder(); + + SC_CTOR(decoder) + { + SC_METHOD(do_decoder); + sensitive << dataaddr; + }; + +}; Index: tags/arelease/source/top_debug.h =================================================================== --- tags/arelease/source/top_debug.h (nonexistent) +++ tags/arelease/source/top_debug.h (revision 13) @@ -0,0 +1,36 @@ +#include "systemc.h" +#include "top.h" +#include "./constants/constants.h" +#include "./constants/debug_signal.h" +#include "stdio.h" +#include "fstream.h" +#include "iostream.h" + +SC_MODULE(top_debug) +{ + sc_in in_clk; + + void debug_signals(); + + FILE *fp; + top *top_level; + + typedef top_debug SC_CURRENT_USER_MODULE; + top_debug(sc_module_name name, char *contents_file) + { + top_level = new top("Top-level", contents_file); + top_level->in_clk(in_clk); + + + fp = fopen("LOG.txt","wt"); + fprintf(fp,"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n"); + fprintf(fp,"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx MIPS R2000 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n"); + fprintf(fp,"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx LOG FILE xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n"); + fprintf(fp,"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx V 1.0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n"); + fprintf(fp,"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx DIEE Igor Loi xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n"); + fprintf(fp,"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n"); + + SC_METHOD(debug_signals); + sensitive_pos << in_clk; + } +}; Index: tags/arelease/PROGRAMMING_CLASSIC/Toolchain/sdelinux-5.01-4.i386.rpm =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: tags/arelease/PROGRAMMING_CLASSIC/Toolchain/sdelinux-5.01-4.i386.rpm =================================================================== --- tags/arelease/PROGRAMMING_CLASSIC/Toolchain/sdelinux-5.01-4.i386.rpm (nonexistent) +++ tags/arelease/PROGRAMMING_CLASSIC/Toolchain/sdelinux-5.01-4.i386.rpm (revision 13)
tags/arelease/PROGRAMMING_CLASSIC/Toolchain/sdelinux-5.01-4.i386.rpm Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: tags/arelease/PROGRAMMING_CLASSIC/link.xn =================================================================== --- tags/arelease/PROGRAMMING_CLASSIC/link.xn (nonexistent) +++ tags/arelease/PROGRAMMING_CLASSIC/link.xn (revision 13) @@ -0,0 +1,88 @@ +/* + * Linker script for the mips programs. Created for the 32bit mips + * little endian achitecture. + */ + +OUTPUT(program.elf) /* Default output name */ +OUTPUT_ARCH(mips) /* Output arch is mips... no shit :-) */ +ENTRY(_start) /* Entry point for program */ + +SECTIONS +{ + /**** Code and read-only data ****/ + + . = 0x00000000; /* Here the code should be loaded so we */ + /* set the location counter to this */ + /* address. */ + .text . : { + + _ftext = .; /* Start of code and read-only data */ + + crt0.o (.text) /* This must be the first file since */ + /* this has the program entry point */ + *(.text) /* The rest of the object files */ + _ecode = .; /* End of code */ + + *(.rodata) + + . = ALIGN(8); + _etext = .; /* End of code and read-only data */ + } = 0 + + .reginfo : { *(.reginfo) } /* Contains masks of registers used and */ + /* $gp value ($gp register is not used) */ + + /**** Initialised data ****/ + + .data : + { + _fdata = .; /* Start of initialised data */ + *(.data) + + . = ALIGN(8); + + *(.lit8) /* Place 8-byte constants here */ + *(.lit4) /* Place 4-byte constants here */ + *(.sdata) /* Place subsequent data */ + + . = ALIGN(8); + + _edata = .; /* End of initialised data */ + } + + .reginfo : + { + /**/ + } + + /**** Uninitialised data ****/ + . = 0x00000000; + _fbss = .; /* Start of uninitialised data */ + + .sbss : + { + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.scommon) /* Place small common symbols here */ + } + + .bss : + { + *(.dynbss) + *(.bss) + *(.bss.*) + *(COMMON) /* Place common symbols here */ + + _sp_end = .; + /* Allocate room for stack */ + . = ALIGN(8) ; + . = 0x4000 ; + _sp = . - 16; + } + + _end = .; /* End of unitialised data */ + +} + + Index: tags/arelease/PROGRAMMING_CLASSIC/mau/instructions.asm =================================================================== --- tags/arelease/PROGRAMMING_CLASSIC/mau/instructions.asm (nonexistent) +++ tags/arelease/PROGRAMMING_CLASSIC/mau/instructions.asm (revision 13) @@ -0,0 +1,310 @@ +@00000000 MIPS (ID): lui $29, 0 +@00000004 MIPS (ID): addiu $29, $29, 16368 +@00000008 MIPS (ID): addiu $8, $0, 0 +@0000000c MIPS (ID): lui $9, 0 +@00000010 MIPS (ID): addiu $9, $9, 16384 +@00000014 MIPS (ID): jal 620 +@00000018 MIPS (ID): nop +@0000001c MIPS (ID): j 28 +@00000020 MIPS (ID): addiu $29, $29, -40 +@00000024 MIPS (ID): sw $31, 36($29) (36) +@00000028 MIPS (ID): sw $30, 32($29) (32) +@0000002c MIPS (ID): or $30, $29, $0 +@00000030 MIPS (ID): sw $4, 40($30) (40) +@00000034 MIPS (ID): sw $5, 44($30) (44) +@00000038 MIPS (ID): sw $6, 48($30) (48) +@0000003c MIPS (ID): lw $2, 44($30) (44) +@00000040 MIPS (ID): nop +@00000044 MIPS (ID): sw $2, 16($30) (16) +@00000048 MIPS (ID): lw $2, 48($30) (48) +@0000004c MIPS (ID): nop +@00000050 MIPS (ID): sw $2, 20($30) (20) +@00000054 MIPS (ID): lw $3, 44($30) (44) +@00000058 MIPS (ID): lw $2, 48($30) (48) +@0000005c MIPS (ID): nop +@00000060 MIPS (ID): addu $3, $3, $2 +@00000064 MIPS (ID): sra $2, $3, 31 +@00000068 MIPS (ID): srl $2, $2, 31 +@0000006c MIPS (ID): addu $2, $3, $2 +@00000070 MIPS (ID): sra $2, $2, 1 +@00000074 MIPS (ID): sll $3, $2, 2 +@00000078 MIPS (ID): lw $2, 40($30) (40) +@0000007c MIPS (ID): nop +@00000080 MIPS (ID): addu $2, $3, $2 +@00000084 MIPS (ID): lw $2, 0($2) (0) +@00000088 MIPS (ID): nop +@0000008c MIPS (ID): sw $2, 28($30) (28) +@00000090 MIPS (ID): lw $2, 16($30) (16) +@00000094 MIPS (ID): nop +@00000098 MIPS (ID): sll $3, $2, 2 +@0000009c MIPS (ID): lw $2, 40($30) (40) +@000000a0 MIPS (ID): nop +@000000a4 MIPS (ID): addu $2, $3, $2 +@000000a8 MIPS (ID): lw $3, 0($2) (0) +@000000ac MIPS (ID): lw $2, 28($30) (28) +@000000b0 MIPS (ID): nop +@000000b4 MIPS (ID): slt $2, $3, $2 +@000000b8 MIPS (ID): bne $0, $2, 3 +@000000bc MIPS (ID): nop +@000000c0 MIPS (ID): beq $0, $0, 6 +@000000c4 MIPS (ID): nop +@000000c8 MIPS (ID): lw $2, 16($30) (16) +@000000cc MIPS (ID): nop +@000000d0 MIPS (ID): addiu $2, $2, 1 +@000000d4 MIPS (ID): beq $0, $0, -18 +@000000d8 MIPS (ID): sw $2, 16($30) (16) +@000000dc MIPS (ID): nop +@000000e0 MIPS (ID): lw $2, 20($30) (20) +@000000e4 MIPS (ID): nop +@000000e8 MIPS (ID): sll $3, $2, 2 +@000000ec MIPS (ID): lw $2, 40($30) (40) +@000000f0 MIPS (ID): nop +@000000f4 MIPS (ID): addu $2, $3, $2 +@000000f8 MIPS (ID): lw $3, 0($2) (0) +@000000fc MIPS (ID): lw $2, 28($30) (28) +@00000100 MIPS (ID): nop +@00000104 MIPS (ID): slt $2, $2, $3 +@00000108 MIPS (ID): bne $0, $2, 3 +@0000010c MIPS (ID): nop +@00000110 MIPS (ID): beq $0, $0, 6 +@00000114 MIPS (ID): nop +@00000118 MIPS (ID): lw $2, 20($30) (20) +@0000011c MIPS (ID): nop +@00000120 MIPS (ID): addiu $2, $2, -1 +@00000124 MIPS (ID): beq $0, $0, -18 +@00000128 MIPS (ID): sw $2, 20($30) (20) +@0000012c MIPS (ID): lw $2, 16($30) (16) +@00000130 MIPS (ID): lw $3, 20($30) (20) +@00000134 MIPS (ID): nop +@00000138 MIPS (ID): slt $2, $3, $2 +@0000013c MIPS (ID): bne $0, $2, 42 +@00000140 MIPS (ID): nop +@00000144 MIPS (ID): lw $2, 16($30) (16) +@00000148 MIPS (ID): nop +@0000014c MIPS (ID): sll $3, $2, 2 +@00000150 MIPS (ID): lw $2, 40($30) (40) +@00000154 MIPS (ID): nop +@00000158 MIPS (ID): addu $2, $3, $2 +@0000015c MIPS (ID): lw $2, 0($2) (0) +@00000160 MIPS (ID): nop +@00000164 MIPS (ID): sw $2, 24($30) (24) +@00000168 MIPS (ID): lw $2, 16($30) (16) +@0000016c MIPS (ID): nop +@00000170 MIPS (ID): sll $3, $2, 2 +@00000174 MIPS (ID): lw $2, 40($30) (40) +@00000178 MIPS (ID): nop +@0000017c MIPS (ID): addu $4, $3, $2 +@00000180 MIPS (ID): lw $2, 20($30) (20) +@00000184 MIPS (ID): nop +@00000188 MIPS (ID): sll $3, $2, 2 +@0000018c MIPS (ID): lw $2, 40($30) (40) +@00000190 MIPS (ID): nop +@00000194 MIPS (ID): addu $2, $3, $2 +@00000198 MIPS (ID): lw $2, 0($2) (0) +@0000019c MIPS (ID): nop +@000001a0 MIPS (ID): sw $2, 0($4) (0) +@000001a4 MIPS (ID): lw $2, 20($30) (20) +@000001a8 MIPS (ID): nop +@000001ac MIPS (ID): sll $3, $2, 2 +@000001b0 MIPS (ID): lw $2, 40($30) (40) +@000001b4 MIPS (ID): nop +@000001b8 MIPS (ID): addu $3, $3, $2 +@000001bc MIPS (ID): lw $2, 24($30) (24) +@000001c0 MIPS (ID): nop +@000001c4 MIPS (ID): sw $2, 0($3) (0) +@000001c8 MIPS (ID): lw $2, 16($30) (16) +@000001cc MIPS (ID): nop +@000001d0 MIPS (ID): addiu $2, $2, 1 +@000001d4 MIPS (ID): sw $2, 16($30) (16) +@000001d8 MIPS (ID): lw $2, 20($30) (20) +@000001dc MIPS (ID): nop +@000001e0 MIPS (ID): addiu $2, $2, -1 +@000001e4 MIPS (ID): sw $2, 20($30) (20) +@000001e8 MIPS (ID): lw $2, 16($30) (16) +@000001ec MIPS (ID): lw $3, 20($30) (20) +@000001f0 MIPS (ID): nop +@000001f4 MIPS (ID): slt $2, $3, $2 +@000001f8 MIPS (ID): beq $0, $2, -91 +@000001fc MIPS (ID): nop +@00000200 MIPS (ID): lw $2, 44($30) (44) +@00000204 MIPS (ID): lw $3, 20($30) (20) +@00000208 MIPS (ID): nop +@0000020c MIPS (ID): slt $2, $2, $3 +@00000210 MIPS (ID): beq $0, $2, 6 +@00000214 MIPS (ID): nop +@00000218 MIPS (ID): lw $4, 40($30) (40) +@0000021c MIPS (ID): lw $5, 44($30) (44) +@00000220 MIPS (ID): lw $6, 20($30) (20) +@00000224 MIPS (ID): jal 32 +@00000228 MIPS (ID): nop +@0000022c MIPS (ID): lw $2, 16($30) (16) +@00000230 MIPS (ID): lw $3, 48($30) (48) +@00000234 MIPS (ID): nop +@00000238 MIPS (ID): slt $2, $2, $3 +@0000023c MIPS (ID): beq $0, $2, 6 +@00000240 MIPS (ID): nop +@00000244 MIPS (ID): lw $4, 40($30) (40) +@00000248 MIPS (ID): lw $5, 16($30) (16) +@0000024c MIPS (ID): lw $6, 48($30) (48) +@00000250 MIPS (ID): jal 32 +@00000254 MIPS (ID): nop +@00000258 MIPS (ID): or $29, $30, $0 +@0000025c MIPS (ID): lw $31, 36($29) (36) +@00000260 MIPS (ID): lw $30, 32($29) (32) +@00000264 MIPS (ID): jr $31 +@00000268 MIPS (ID): addiu $29, $29, 40 +@0000026c MIPS (ID): addiu $29, $29, -88 +@00000270 MIPS (ID): sw $31, 84($29) (84) +@00000274 MIPS (ID): sw $30, 80($29) (80) +@00000278 MIPS (ID): or $30, $29, $0 +@0000027c MIPS (ID): addiu $2, $0, 1024 +@00000280 MIPS (ID): sw $2, 68($30) (68) +@00000284 MIPS (ID): addiu $2, $0, 4 +@00000288 MIPS (ID): sw $2, 72($30) (72) +@0000028c MIPS (ID): lw $3, 68($30) (68) +@00000290 MIPS (ID): lw $2, 72($30) (72) +@00000294 MIPS (ID): nop +@00000298 MIPS (ID): mult [Hi,Lo], $3, $2 +@0000029c MIPS (ID): mflo $2 [Lo] +@000002a0 MIPS (ID): sw $2, 64($30) (64) +@000002a4 MIPS (ID): addiu $2, $0, 13 +@000002a8 MIPS (ID): sw $2, 16($30) (16) +@000002ac MIPS (ID): addiu $2, $0, 34 +@000002b0 MIPS (ID): sw $2, 20($30) (20) +@000002b4 MIPS (ID): addiu $2, $0, 86 +@000002b8 MIPS (ID): sw $2, 24($30) (24) +@000002bc MIPS (ID): addiu $2, $0, 23 +@000002c0 MIPS (ID): sw $2, 28($30) (28) +@000002c4 MIPS (ID): addiu $2, $0, 52 +@000002c8 MIPS (ID): sw $2, 32($30) (32) +@000002cc MIPS (ID): addiu $2, $0, 43 +@000002d0 MIPS (ID): sw $2, 36($30) (36) +@000002d4 MIPS (ID): addiu $2, $0, 45 +@000002d8 MIPS (ID): sw $2, 40($30) (40) +@000002dc MIPS (ID): addiu $2, $0, 87 +@000002e0 MIPS (ID): sw $2, 44($30) (44) +@000002e4 MIPS (ID): addiu $2, $0, 12 +@000002e8 MIPS (ID): sw $2, 48($30) (48) +@000002ec MIPS (ID): addiu $2, $0, 24 +@000002f0 MIPS (ID): sw $2, 52($30) (52) +@000002f4 MIPS (ID): addiu $2, $0, 35 +@000002f8 MIPS (ID): sw $2, 56($30) (56) +@000002fc MIPS (ID): addiu $2, $0, 100 +@00000300 MIPS (ID): sw $2, 60($30) (60) +@00000304 MIPS (ID): addiu $4, $30, 16 +@00000308 MIPS (ID): or $5, $0, $0 +@0000030c MIPS (ID): jal 32 +@00000310 MIPS (ID): addiu $6, $0, 11 +@00000314 MIPS (ID): lui $2, 256 +@00000318 MIPS (ID): ori $2, $2, 0x1000 +@0000031c MIPS (ID): sw $2, 76($30) (76) +@00000320 MIPS (ID): lw $3, 76($30) (76) +@00000324 MIPS (ID): lw $2, 16($30) (16) +@00000328 MIPS (ID): nop +@0000032c MIPS (ID): sw $2, 0($3) (0) +@00000330 MIPS (ID): lui $2, 256 +@00000334 MIPS (ID): ori $2, $2, 0x1004 +@00000338 MIPS (ID): sw $2, 76($30) (76) +@0000033c MIPS (ID): lw $3, 76($30) (76) +@00000340 MIPS (ID): lw $2, 20($30) (20) +@00000344 MIPS (ID): nop +@00000348 MIPS (ID): sw $2, 0($3) (0) +@0000034c MIPS (ID): lui $2, 256 +@00000350 MIPS (ID): ori $2, $2, 0x1008 +@00000354 MIPS (ID): sw $2, 76($30) (76) +@00000358 MIPS (ID): lw $3, 76($30) (76) +@0000035c MIPS (ID): lw $2, 24($30) (24) +@00000360 MIPS (ID): nop +@00000364 MIPS (ID): sw $2, 0($3) (0) +@00000368 MIPS (ID): lui $2, 256 +@0000036c MIPS (ID): ori $2, $2, 0x100c +@00000370 MIPS (ID): sw $2, 76($30) (76) +@00000374 MIPS (ID): lw $3, 76($30) (76) +@00000378 MIPS (ID): lw $2, 28($30) (28) +@0000037c MIPS (ID): nop +@00000380 MIPS (ID): sw $2, 0($3) (0) +@00000384 MIPS (ID): lui $2, 256 +@00000388 MIPS (ID): ori $2, $2, 0x1010 +@0000038c MIPS (ID): sw $2, 76($30) (76) +@00000390 MIPS (ID): lw $3, 76($30) (76) +@00000394 MIPS (ID): lw $2, 32($30) (32) +@00000398 MIPS (ID): nop +@0000039c MIPS (ID): sw $2, 0($3) (0) +@000003a0 MIPS (ID): lui $2, 256 +@000003a4 MIPS (ID): ori $2, $2, 0x1014 +@000003a8 MIPS (ID): sw $2, 76($30) (76) +@000003ac MIPS (ID): lw $3, 76($30) (76) +@000003b0 MIPS (ID): lw $2, 36($30) (36) +@000003b4 MIPS (ID): nop +@000003b8 MIPS (ID): sw $2, 0($3) (0) +@000003bc MIPS (ID): lui $2, 256 +@000003c0 MIPS (ID): ori $2, $2, 0x1018 +@000003c4 MIPS (ID): sw $2, 76($30) (76) +@000003c8 MIPS (ID): lw $3, 76($30) (76) +@000003cc MIPS (ID): lw $2, 40($30) (40) +@000003d0 MIPS (ID): nop +@000003d4 MIPS (ID): sw $2, 0($3) (0) +@000003d8 MIPS (ID): lui $2, 256 +@000003dc MIPS (ID): ori $2, $2, 0x101c +@000003e0 MIPS (ID): sw $2, 76($30) (76) +@000003e4 MIPS (ID): lw $3, 76($30) (76) +@000003e8 MIPS (ID): lw $2, 44($30) (44) +@000003ec MIPS (ID): nop +@000003f0 MIPS (ID): sw $2, 0($3) (0) +@000003f4 MIPS (ID): lui $2, 256 +@000003f8 MIPS (ID): ori $2, $2, 0x1020 +@000003fc MIPS (ID): sw $2, 76($30) (76) +@00000400 MIPS (ID): lw $3, 76($30) (76) +@00000404 MIPS (ID): lw $2, 48($30) (48) +@00000408 MIPS (ID): nop +@0000040c MIPS (ID): sw $2, 0($3) (0) +@00000410 MIPS (ID): lui $2, 256 +@00000414 MIPS (ID): ori $2, $2, 0x1024 +@00000418 MIPS (ID): sw $2, 76($30) (76) +@0000041c MIPS (ID): lw $3, 76($30) (76) +@00000420 MIPS (ID): lw $2, 52($30) (52) +@00000424 MIPS (ID): nop +@00000428 MIPS (ID): sw $2, 0($3) (0) +@0000042c MIPS (ID): lui $2, 256 +@00000430 MIPS (ID): ori $2, $2, 0x1028 +@00000434 MIPS (ID): sw $2, 76($30) (76) +@00000438 MIPS (ID): lw $3, 76($30) (76) +@0000043c MIPS (ID): lw $2, 56($30) (56) +@00000440 MIPS (ID): nop +@00000444 MIPS (ID): sw $2, 0($3) (0) +@00000448 MIPS (ID): lui $2, 256 +@0000044c MIPS (ID): ori $2, $2, 0x102c +@00000450 MIPS (ID): sw $2, 76($30) (76) +@00000454 MIPS (ID): lw $3, 76($30) (76) +@00000458 MIPS (ID): lw $2, 60($30) (60) +@0000045c MIPS (ID): nop +@00000460 MIPS (ID): sw $2, 0($3) (0) +@00000464 MIPS (ID): lui $2, 256 +@00000468 MIPS (ID): ori $2, $2, 0x1030 +@0000046c MIPS (ID): sw $2, 76($30) (76) +@00000470 MIPS (ID): lw $3, 76($30) (76) +@00000474 MIPS (ID): lw $2, 64($30) (64) +@00000478 MIPS (ID): nop +@0000047c MIPS (ID): sw $2, 0($3) (0) +@00000480 MIPS (ID): nop +@00000484 MIPS (ID): lui $2, 32767 +@00000488 MIPS (ID): ori $2, $2, 0xfffffffc +@0000048c MIPS (ID): sw $2, 76($30) (76) +@00000490 MIPS (ID): lw $2, 76($30) (76) +@00000494 MIPS (ID): nop +@00000498 MIPS (ID): sw $0, 0($2) (0) +@0000049c MIPS (ID): or $2, $0, $0 +@000004a0 MIPS (ID): or $29, $30, $0 +@000004a4 MIPS (ID): lw $31, 84($29) (84) +@000004a8 MIPS (ID): lw $30, 80($29) (80) +@000004ac MIPS (ID): jr $31 +@000004b0 MIPS (ID): addiu $29, $29, 88 +@000004b4 MIPS (ID): nop +@000004b8 MIPS (ID): nop +@000004bc MIPS (ID): nop +@000004c0 MIPS (ID): sb $0, 768($0) (768) +@000004c4 MIPS (ID): nop +@000004c8 MIPS (ID): nop +@000004cc MIPS (ID): nop +@000004d0 MIPS (ID): nop +@000004d4 MIPS (ID): nop Index: tags/arelease/PROGRAMMING_CLASSIC/mau/main+quick disassemblato.txt =================================================================== --- tags/arelease/PROGRAMMING_CLASSIC/mau/main+quick disassemblato.txt (nonexistent) +++ tags/arelease/PROGRAMMING_CLASSIC/mau/main+quick disassemblato.txt (revision 13) @@ -0,0 +1,297 @@ + +00000000 : + 0: 27bdffd8 addiu $sp,$sp,-40 + 4: afbf0024 sw $ra,36($sp) + 8: afbe0020 sw $s8,32($sp) + c: 03a0f025 move $s8,$sp + 10: afc40028 sw $a0,40($s8) + 14: afc5002c sw $a1,44($s8) + 18: afc60030 sw $a2,48($s8) + 1c: 8fc2002c lw $v0,44($s8) + 20: 00000000 nop + 24: afc20010 sw $v0,16($s8) + 28: 8fc20030 lw $v0,48($s8) + 2c: 00000000 nop + 30: afc20014 sw $v0,20($s8) + 34: 8fc3002c lw $v1,44($s8) + 38: 8fc20030 lw $v0,48($s8) + 3c: 00000000 nop + 40: 00621821 addu $v1,$v1,$v0 + 44: 000317c3 sra $v0,$v1,0x1f + 48: 000217c2 srl $v0,$v0,0x1f + 4c: 00621021 addu $v0,$v1,$v0 + 50: 00021043 sra $v0,$v0,0x1 + 54: 00021880 sll $v1,$v0,0x2 + 58: 8fc20028 lw $v0,40($s8) + 5c: 00000000 nop + 60: 00621021 addu $v0,$v1,$v0 + 64: 8c420000 lw $v0,0($v0) + 68: 00000000 nop + 6c: afc2001c sw $v0,28($s8) + 70: 8fc20010 lw $v0,16($s8) + 74: 00000000 nop + 78: 00021880 sll $v1,$v0,0x2 + 7c: 8fc20028 lw $v0,40($s8) + 80: 00000000 nop + 84: 00621021 addu $v0,$v1,$v0 + 88: 8c430000 lw $v1,0($v0) + 8c: 8fc2001c lw $v0,28($s8) + 90: 00000000 nop + 94: 0062102a slt $v0,$v1,$v0 + 98: 14400003 bnez $v0,a8 + 9c: 00000000 nop + a0: 10000006 b bc + a4: 00000000 nop + a8: 8fc20010 lw $v0,16($s8) + ac: 00000000 nop + b0: 24420001 addiu $v0,$v0,1 + b4: 1000ffee b 70 + b8: afc20010 sw $v0,16($s8) + bc: 00000000 nop + c0: 8fc20014 lw $v0,20($s8) + c4: 00000000 nop + c8: 00021880 sll $v1,$v0,0x2 + cc: 8fc20028 lw $v0,40($s8) + d0: 00000000 nop + d4: 00621021 addu $v0,$v1,$v0 + d8: 8c430000 lw $v1,0($v0) + dc: 8fc2001c lw $v0,28($s8) + e0: 00000000 nop + e4: 0043102a slt $v0,$v0,$v1 + e8: 14400003 bnez $v0,f8 + ec: 00000000 nop + f0: 10000006 b 10c + f4: 00000000 nop + f8: 8fc20014 lw $v0,20($s8) + fc: 00000000 nop + 100: 2442ffff addiu $v0,$v0,-1 + 104: 1000ffee b c0 + 108: afc20014 sw $v0,20($s8) + 10c: 8fc20010 lw $v0,16($s8) + 110: 8fc30014 lw $v1,20($s8) + 114: 00000000 nop + 118: 0062102a slt $v0,$v1,$v0 + 11c: 1440002a bnez $v0,1c8 + 120: 00000000 nop + 124: 8fc20010 lw $v0,16($s8) + 128: 00000000 nop + 12c: 00021880 sll $v1,$v0,0x2 + 130: 8fc20028 lw $v0,40($s8) + 134: 00000000 nop + 138: 00621021 addu $v0,$v1,$v0 + 13c: 8c420000 lw $v0,0($v0) + 140: 00000000 nop + 144: afc20018 sw $v0,24($s8) + 148: 8fc20010 lw $v0,16($s8) + 14c: 00000000 nop + 150: 00021880 sll $v1,$v0,0x2 + 154: 8fc20028 lw $v0,40($s8) + 158: 00000000 nop + 15c: 00622021 addu $a0,$v1,$v0 + 160: 8fc20014 lw $v0,20($s8) + 164: 00000000 nop + 168: 00021880 sll $v1,$v0,0x2 + 16c: 8fc20028 lw $v0,40($s8) + 170: 00000000 nop + 174: 00621021 addu $v0,$v1,$v0 + 178: 8c420000 lw $v0,0($v0) + 17c: 00000000 nop + 180: ac820000 sw $v0,0($a0) + 184: 8fc20014 lw $v0,20($s8) + 188: 00000000 nop + 18c: 00021880 sll $v1,$v0,0x2 + 190: 8fc20028 lw $v0,40($s8) + 194: 00000000 nop + 198: 00621821 addu $v1,$v1,$v0 + 19c: 8fc20018 lw $v0,24($s8) + 1a0: 00000000 nop + 1a4: ac620000 sw $v0,0($v1) + 1a8: 8fc20010 lw $v0,16($s8) + 1ac: 00000000 nop + 1b0: 24420001 addiu $v0,$v0,1 + 1b4: afc20010 sw $v0,16($s8) + 1b8: 8fc20014 lw $v0,20($s8) + 1bc: 00000000 nop + 1c0: 2442ffff addiu $v0,$v0,-1 + 1c4: afc20014 sw $v0,20($s8) + 1c8: 8fc20010 lw $v0,16($s8) + 1cc: 8fc30014 lw $v1,20($s8) + 1d0: 00000000 nop + 1d4: 0062102a slt $v0,$v1,$v0 + 1d8: 1040ffa5 beqz $v0,70 + 1dc: 00000000 nop + 1e0: 8fc2002c lw $v0,44($s8) + 1e4: 8fc30014 lw $v1,20($s8) + 1e8: 00000000 nop + 1ec: 0043102a slt $v0,$v0,$v1 + 1f0: 10400006 beqz $v0,20c + 1f4: 00000000 nop + 1f8: 8fc40028 lw $a0,40($s8) + 1fc: 8fc5002c lw $a1,44($s8) + 200: 8fc60014 lw $a2,20($s8) + 204: 0c000000 jal 0 + 208: 00000000 nop + 20c: 8fc20010 lw $v0,16($s8) + 210: 8fc30030 lw $v1,48($s8) + 214: 00000000 nop + 218: 0043102a slt $v0,$v0,$v1 + 21c: 10400006 beqz $v0,238 + 220: 00000000 nop + 224: 8fc40028 lw $a0,40($s8) + 228: 8fc50010 lw $a1,16($s8) + 22c: 8fc60030 lw $a2,48($s8) + 230: 0c000000 jal 0 + 234: 00000000 nop + 238: 03c0e825 move $sp,$s8 + 23c: 8fbf0024 lw $ra,36($sp) + 240: 8fbe0020 lw $s8,32($sp) + 244: 03e00008 jr $ra + 248: 27bd0028 addiu $sp,$sp,40 + +0000024c
: + 24c: 27bdffa8 addiu $sp,$sp,-88 + 250: afbf0054 sw $ra,84($sp) + 254: afbe0050 sw $s8,80($sp) + 258: 03a0f025 move $s8,$sp + 25c: 24020400 li $v0,1024 + 260: afc20044 sw $v0,68($s8) + 264: 24020004 li $v0,4 + 268: afc20048 sw $v0,72($s8) + 26c: 8fc30044 lw $v1,68($s8) + 270: 8fc20048 lw $v0,72($s8) + 274: 00000000 nop + 278: 00620018 mult $v1,$v0 + 27c: 00001012 mflo $v0 + 280: afc20040 sw $v0,64($s8) + 284: 2402000d li $v0,13 + 288: afc20010 sw $v0,16($s8) + 28c: 24020022 li $v0,34 + 290: afc20014 sw $v0,20($s8) + 294: 24020056 li $v0,86 + 298: afc20018 sw $v0,24($s8) + 29c: 24020017 li $v0,23 + 2a0: afc2001c sw $v0,28($s8) + 2a4: 24020034 li $v0,52 + 2a8: afc20020 sw $v0,32($s8) + 2ac: 2402002b li $v0,43 + 2b0: afc20024 sw $v0,36($s8) + 2b4: 2402002d li $v0,45 + 2b8: afc20028 sw $v0,40($s8) + 2bc: 24020057 li $v0,87 + 2c0: afc2002c sw $v0,44($s8) + 2c4: 2402000c li $v0,12 + 2c8: afc20030 sw $v0,48($s8) + 2cc: 24020018 li $v0,24 + 2d0: afc20034 sw $v0,52($s8) + 2d4: 24020023 li $v0,35 + 2d8: afc20038 sw $v0,56($s8) + 2dc: 24020064 li $v0,100 + 2e0: afc2003c sw $v0,60($s8) + 2e4: 27c40010 addiu $a0,$s8,16 + 2e8: 00002825 move $a1,$zero + 2ec: 0c000000 jal 0 + 2f0: 2406000b li $a2,11 + 2f4: 3c020100 lui $v0,0x100 + 2f8: 34421000 ori $v0,$v0,0x1000 + 2fc: afc2004c sw $v0,76($s8) + 300: 8fc3004c lw $v1,76($s8) + 304: 8fc20010 lw $v0,16($s8) + 308: 00000000 nop + 30c: ac620000 sw $v0,0($v1) + 310: 3c020100 lui $v0,0x100 + 314: 34421004 ori $v0,$v0,0x1004 + 318: afc2004c sw $v0,76($s8) + 31c: 8fc3004c lw $v1,76($s8) + 320: 8fc20014 lw $v0,20($s8) + 324: 00000000 nop + 328: ac620000 sw $v0,0($v1) + 32c: 3c020100 lui $v0,0x100 + 330: 34421008 ori $v0,$v0,0x1008 + 334: afc2004c sw $v0,76($s8) + 338: 8fc3004c lw $v1,76($s8) + 33c: 8fc20018 lw $v0,24($s8) + 340: 00000000 nop + 344: ac620000 sw $v0,0($v1) + 348: 3c020100 lui $v0,0x100 + 34c: 3442100c ori $v0,$v0,0x100c + 350: afc2004c sw $v0,76($s8) + 354: 8fc3004c lw $v1,76($s8) + 358: 8fc2001c lw $v0,28($s8) + 35c: 00000000 nop + 360: ac620000 sw $v0,0($v1) + 364: 3c020100 lui $v0,0x100 + 368: 34421010 ori $v0,$v0,0x1010 + 36c: afc2004c sw $v0,76($s8) + 370: 8fc3004c lw $v1,76($s8) + 374: 8fc20020 lw $v0,32($s8) + 378: 00000000 nop + 37c: ac620000 sw $v0,0($v1) + 380: 3c020100 lui $v0,0x100 + 384: 34421014 ori $v0,$v0,0x1014 + 388: afc2004c sw $v0,76($s8) + 38c: 8fc3004c lw $v1,76($s8) + 390: 8fc20024 lw $v0,36($s8) + 394: 00000000 nop + 398: ac620000 sw $v0,0($v1) + 39c: 3c020100 lui $v0,0x100 + 3a0: 34421018 ori $v0,$v0,0x1018 + 3a4: afc2004c sw $v0,76($s8) + 3a8: 8fc3004c lw $v1,76($s8) + 3ac: 8fc20028 lw $v0,40($s8) + 3b0: 00000000 nop + 3b4: ac620000 sw $v0,0($v1) + 3b8: 3c020100 lui $v0,0x100 + 3bc: 3442101c ori $v0,$v0,0x101c + 3c0: afc2004c sw $v0,76($s8) + 3c4: 8fc3004c lw $v1,76($s8) + 3c8: 8fc2002c lw $v0,44($s8) + 3cc: 00000000 nop + 3d0: ac620000 sw $v0,0($v1) + 3d4: 3c020100 lui $v0,0x100 + 3d8: 34421020 ori $v0,$v0,0x1020 + 3dc: afc2004c sw $v0,76($s8) + 3e0: 8fc3004c lw $v1,76($s8) + 3e4: 8fc20030 lw $v0,48($s8) + 3e8: 00000000 nop + 3ec: ac620000 sw $v0,0($v1) + 3f0: 3c020100 lui $v0,0x100 + 3f4: 34421024 ori $v0,$v0,0x1024 + 3f8: afc2004c sw $v0,76($s8) + 3fc: 8fc3004c lw $v1,76($s8) + 400: 8fc20034 lw $v0,52($s8) + 404: 00000000 nop + 408: ac620000 sw $v0,0($v1) + 40c: 3c020100 lui $v0,0x100 + 410: 34421028 ori $v0,$v0,0x1028 + 414: afc2004c sw $v0,76($s8) + 418: 8fc3004c lw $v1,76($s8) + 41c: 8fc20038 lw $v0,56($s8) + 420: 00000000 nop + 424: ac620000 sw $v0,0($v1) + 428: 3c020100 lui $v0,0x100 + 42c: 3442102c ori $v0,$v0,0x102c + 430: afc2004c sw $v0,76($s8) + 434: 8fc3004c lw $v1,76($s8) + 438: 8fc2003c lw $v0,60($s8) + 43c: 00000000 nop + 440: ac620000 sw $v0,0($v1) + 444: 3c020100 lui $v0,0x100 + 448: 34421030 ori $v0,$v0,0x1030 + 44c: afc2004c sw $v0,76($s8) + 450: 8fc3004c lw $v1,76($s8) + 454: 8fc20040 lw $v0,64($s8) + 458: 00000000 nop + 45c: ac620000 sw $v0,0($v1) + 460: 00000000 nop + 464: 3c027fff lui $v0,0x7fff + 468: 3442fffc ori $v0,$v0,0xfffc + 46c: afc2004c sw $v0,76($s8) + 470: 8fc2004c lw $v0,76($s8) + 474: 00000000 nop + 478: ac400000 sw $zero,0($v0) + 47c: 00001025 move $v0,$zero + 480: 03c0e825 move $sp,$s8 + 484: 8fbf0054 lw $ra,84($sp) + 488: 8fbe0050 lw $s8,80($sp) + 48c: 03e00008 jr $ra + 490: 27bd0058 addiu $sp,$sp,88 Index: tags/arelease/PROGRAMMING_CLASSIC/mau/instructions.hex =================================================================== --- tags/arelease/PROGRAMMING_CLASSIC/mau/instructions.hex (nonexistent) +++ tags/arelease/PROGRAMMING_CLASSIC/mau/instructions.hex (revision 13) @@ -0,0 +1,310 @@ +@00000000 3c 1d 00 00 +@00000004 27 bd 3f f0 +@00000008 24 08 00 00 +@0000000c 3c 09 00 00 +@00000010 25 29 40 00 +@00000014 0c 00 00 9b +@00000018 00 00 00 00 +@0000001c 08 00 00 07 +@00000020 27 bd ff d8 +@00000024 af bf 00 24 +@00000028 af be 00 20 +@0000002c 03 a0 f0 25 +@00000030 af c4 00 28 +@00000034 af c5 00 2c +@00000038 af c6 00 30 +@0000003c 8f c2 00 2c +@00000040 00 00 00 00 +@00000044 af c2 00 10 +@00000048 8f c2 00 30 +@0000004c 00 00 00 00 +@00000050 af c2 00 14 +@00000054 8f c3 00 2c +@00000058 8f c2 00 30 +@0000005c 00 00 00 00 +@00000060 00 62 18 21 +@00000064 00 03 17 c3 +@00000068 00 02 17 c2 +@0000006c 00 62 10 21 +@00000070 00 02 10 43 +@00000074 00 02 18 80 +@00000078 8f c2 00 28 +@0000007c 00 00 00 00 +@00000080 00 62 10 21 +@00000084 8c 42 00 00 +@00000088 00 00 00 00 +@0000008c af c2 00 1c +@00000090 8f c2 00 10 +@00000094 00 00 00 00 +@00000098 00 02 18 80 +@0000009c 8f c2 00 28 +@000000a0 00 00 00 00 +@000000a4 00 62 10 21 +@000000a8 8c 43 00 00 +@000000ac 8f c2 00 1c +@000000b0 00 00 00 00 +@000000b4 00 62 10 2a +@000000b8 14 40 00 03 +@000000bc 00 00 00 00 +@000000c0 10 00 00 06 +@000000c4 00 00 00 00 +@000000c8 8f c2 00 10 +@000000cc 00 00 00 00 +@000000d0 24 42 00 01 +@000000d4 10 00 ff ee +@000000d8 af c2 00 10 +@000000dc 00 00 00 00 +@000000e0 8f c2 00 14 +@000000e4 00 00 00 00 +@000000e8 00 02 18 80 +@000000ec 8f c2 00 28 +@000000f0 00 00 00 00 +@000000f4 00 62 10 21 +@000000f8 8c 43 00 00 +@000000fc 8f c2 00 1c +@00000100 00 00 00 00 +@00000104 00 43 10 2a +@00000108 14 40 00 03 +@0000010c 00 00 00 00 +@00000110 10 00 00 06 +@00000114 00 00 00 00 +@00000118 8f c2 00 14 +@0000011c 00 00 00 00 +@00000120 24 42 ff ff +@00000124 10 00 ff ee +@00000128 af c2 00 14 +@0000012c 8f c2 00 10 +@00000130 8f c3 00 14 +@00000134 00 00 00 00 +@00000138 00 62 10 2a +@0000013c 14 40 00 2a +@00000140 00 00 00 00 +@00000144 8f c2 00 10 +@00000148 00 00 00 00 +@0000014c 00 02 18 80 +@00000150 8f c2 00 28 +@00000154 00 00 00 00 +@00000158 00 62 10 21 +@0000015c 8c 42 00 00 +@00000160 00 00 00 00 +@00000164 af c2 00 18 +@00000168 8f c2 00 10 +@0000016c 00 00 00 00 +@00000170 00 02 18 80 +@00000174 8f c2 00 28 +@00000178 00 00 00 00 +@0000017c 00 62 20 21 +@00000180 8f c2 00 14 +@00000184 00 00 00 00 +@00000188 00 02 18 80 +@0000018c 8f c2 00 28 +@00000190 00 00 00 00 +@00000194 00 62 10 21 +@00000198 8c 42 00 00 +@0000019c 00 00 00 00 +@000001a0 ac 82 00 00 +@000001a4 8f c2 00 14 +@000001a8 00 00 00 00 +@000001ac 00 02 18 80 +@000001b0 8f c2 00 28 +@000001b4 00 00 00 00 +@000001b8 00 62 18 21 +@000001bc 8f c2 00 18 +@000001c0 00 00 00 00 +@000001c4 ac 62 00 00 +@000001c8 8f c2 00 10 +@000001cc 00 00 00 00 +@000001d0 24 42 00 01 +@000001d4 af c2 00 10 +@000001d8 8f c2 00 14 +@000001dc 00 00 00 00 +@000001e0 24 42 ff ff +@000001e4 af c2 00 14 +@000001e8 8f c2 00 10 +@000001ec 8f c3 00 14 +@000001f0 00 00 00 00 +@000001f4 00 62 10 2a +@000001f8 10 40 ff a5 +@000001fc 00 00 00 00 +@00000200 8f c2 00 2c +@00000204 8f c3 00 14 +@00000208 00 00 00 00 +@0000020c 00 43 10 2a +@00000210 10 40 00 06 +@00000214 00 00 00 00 +@00000218 8f c4 00 28 +@0000021c 8f c5 00 2c +@00000220 8f c6 00 14 +@00000224 0c 00 00 08 +@00000228 00 00 00 00 +@0000022c 8f c2 00 10 +@00000230 8f c3 00 30 +@00000234 00 00 00 00 +@00000238 00 43 10 2a +@0000023c 10 40 00 06 +@00000240 00 00 00 00 +@00000244 8f c4 00 28 +@00000248 8f c5 00 10 +@0000024c 8f c6 00 30 +@00000250 0c 00 00 08 +@00000254 00 00 00 00 +@00000258 03 c0 e8 25 +@0000025c 8f bf 00 24 +@00000260 8f be 00 20 +@00000264 03 e0 00 08 +@00000268 27 bd 00 28 +@0000026c 27 bd ff a8 +@00000270 af bf 00 54 +@00000274 af be 00 50 +@00000278 03 a0 f0 25 +@0000027c 24 02 04 00 +@00000280 af c2 00 44 +@00000284 24 02 00 04 +@00000288 af c2 00 48 +@0000028c 8f c3 00 44 +@00000290 8f c2 00 48 +@00000294 00 00 00 00 +@00000298 00 62 00 18 +@0000029c 00 00 10 12 +@000002a0 af c2 00 40 +@000002a4 24 02 00 0d +@000002a8 af c2 00 10 +@000002ac 24 02 00 22 +@000002b0 af c2 00 14 +@000002b4 24 02 00 56 +@000002b8 af c2 00 18 +@000002bc 24 02 00 17 +@000002c0 af c2 00 1c +@000002c4 24 02 00 34 +@000002c8 af c2 00 20 +@000002cc 24 02 00 2b +@000002d0 af c2 00 24 +@000002d4 24 02 00 2d +@000002d8 af c2 00 28 +@000002dc 24 02 00 57 +@000002e0 af c2 00 2c +@000002e4 24 02 00 0c +@000002e8 af c2 00 30 +@000002ec 24 02 00 18 +@000002f0 af c2 00 34 +@000002f4 24 02 00 23 +@000002f8 af c2 00 38 +@000002fc 24 02 00 64 +@00000300 af c2 00 3c +@00000304 27 c4 00 10 +@00000308 00 00 28 25 +@0000030c 0c 00 00 08 +@00000310 24 06 00 0b +@00000314 3c 02 01 00 +@00000318 34 42 10 00 +@0000031c af c2 00 4c +@00000320 8f c3 00 4c +@00000324 8f c2 00 10 +@00000328 00 00 00 00 +@0000032c ac 62 00 00 +@00000330 3c 02 01 00 +@00000334 34 42 10 04 +@00000338 af c2 00 4c +@0000033c 8f c3 00 4c +@00000340 8f c2 00 14 +@00000344 00 00 00 00 +@00000348 ac 62 00 00 +@0000034c 3c 02 01 00 +@00000350 34 42 10 08 +@00000354 af c2 00 4c +@00000358 8f c3 00 4c +@0000035c 8f c2 00 18 +@00000360 00 00 00 00 +@00000364 ac 62 00 00 +@00000368 3c 02 01 00 +@0000036c 34 42 10 0c +@00000370 af c2 00 4c +@00000374 8f c3 00 4c +@00000378 8f c2 00 1c +@0000037c 00 00 00 00 +@00000380 ac 62 00 00 +@00000384 3c 02 01 00 +@00000388 34 42 10 10 +@0000038c af c2 00 4c +@00000390 8f c3 00 4c +@00000394 8f c2 00 20 +@00000398 00 00 00 00 +@0000039c ac 62 00 00 +@000003a0 3c 02 01 00 +@000003a4 34 42 10 14 +@000003a8 af c2 00 4c +@000003ac 8f c3 00 4c +@000003b0 8f c2 00 24 +@000003b4 00 00 00 00 +@000003b8 ac 62 00 00 +@000003bc 3c 02 01 00 +@000003c0 34 42 10 18 +@000003c4 af c2 00 4c +@000003c8 8f c3 00 4c +@000003cc 8f c2 00 28 +@000003d0 00 00 00 00 +@000003d4 ac 62 00 00 +@000003d8 3c 02 01 00 +@000003dc 34 42 10 1c +@000003e0 af c2 00 4c +@000003e4 8f c3 00 4c +@000003e8 8f c2 00 2c +@000003ec 00 00 00 00 +@000003f0 ac 62 00 00 +@000003f4 3c 02 01 00 +@000003f8 34 42 10 20 +@000003fc af c2 00 4c +@00000400 8f c3 00 4c +@00000404 8f c2 00 30 +@00000408 00 00 00 00 +@0000040c ac 62 00 00 +@00000410 3c 02 01 00 +@00000414 34 42 10 24 +@00000418 af c2 00 4c +@0000041c 8f c3 00 4c +@00000420 8f c2 00 34 +@00000424 00 00 00 00 +@00000428 ac 62 00 00 +@0000042c 3c 02 01 00 +@00000430 34 42 10 28 +@00000434 af c2 00 4c +@00000438 8f c3 00 4c +@0000043c 8f c2 00 38 +@00000440 00 00 00 00 +@00000444 ac 62 00 00 +@00000448 3c 02 01 00 +@0000044c 34 42 10 2c +@00000450 af c2 00 4c +@00000454 8f c3 00 4c +@00000458 8f c2 00 3c +@0000045c 00 00 00 00 +@00000460 ac 62 00 00 +@00000464 3c 02 01 00 +@00000468 34 42 10 30 +@0000046c af c2 00 4c +@00000470 8f c3 00 4c +@00000474 8f c2 00 40 +@00000478 00 00 00 00 +@0000047c ac 62 00 00 +@00000480 00 00 00 00 +@00000484 3c 02 7f ff +@00000488 34 42 ff fc +@0000048c af c2 00 4c +@00000490 8f c2 00 4c +@00000494 00 00 00 00 +@00000498 ac 40 00 00 +@0000049c 00 00 10 25 +@000004a0 03 c0 e8 25 +@000004a4 8f bf 00 54 +@000004a8 8f be 00 50 +@000004ac 03 e0 00 08 +@000004b0 27 bd 00 58 +@000004b4 00 00 00 00 +@000004b8 00 00 00 00 +@000004bc 00 00 00 00 +@000004c0 a0 00 03 00 +@000004c4 00 00 00 00 +@000004c8 00 00 00 00 +@000004cc 00 00 00 00 +@000004d0 00 00 00 00 +@000004d4 00 00 00 00 Index: tags/arelease/PROGRAMMING_CLASSIC/regdef.h =================================================================== --- tags/arelease/PROGRAMMING_CLASSIC/regdef.h (nonexistent) +++ tags/arelease/PROGRAMMING_CLASSIC/regdef.h (revision 13) @@ -0,0 +1,45 @@ +/* + * Register definitions + * + * This file is subject to the terms and conditions of the GNU General + * Public License. See the file "COPYING" in the main directory of + * this archive for more details. + */ +#ifndef _REGDEF_H +#define _REGDEF_H + +#define zero $0 /* wired zero */ +#define AT $at /* assembler temp - uppercase because of ".set at" */ +#define v0 $2 /* return value - caller saved */ +#define v1 $3 +#define a0 $4 /* argument registers */ +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define t0 $8 /* caller saved in 32 bit (arg reg 64 bit) */ +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 /* caller saved */ +#define t5 $13 +#define t6 $14 +#define t7 $15 +#define s0 $16 /* callee saved */ +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 /* caller saved */ +#define t9 $25 /* callee address for PIC/temp */ +#define k0 $26 /* kernel temporary */ +#define k1 $27 +#define gp $28 /* global pointer - caller saved for PIC */ +#define sp $29 /* stack pointer */ +#define fp $30 /* frame pointer */ +#define s8 $30 /* callee saved */ +#define ra $31 /* return address */ + +#endif /* _REGDEF_H */ Index: tags/arelease/PROGRAMMING_CLASSIC/My_Program.bin =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: tags/arelease/PROGRAMMING_CLASSIC/My_Program.bin =================================================================== --- tags/arelease/PROGRAMMING_CLASSIC/My_Program.bin (nonexistent) +++ tags/arelease/PROGRAMMING_CLASSIC/My_Program.bin (revision 13)
tags/arelease/PROGRAMMING_CLASSIC/My_Program.bin Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: tags/arelease/PROGRAMMING_CLASSIC/crt0.S =================================================================== --- tags/arelease/PROGRAMMING_CLASSIC/crt0.S (nonexistent) +++ tags/arelease/PROGRAMMING_CLASSIC/crt0.S (revision 13) @@ -0,0 +1,36 @@ +/* + * Starting point for everything (bootstrap) + * + * Initializes the stack pointer and jumps to main(). + */ + +#include "regdef.h" + + .text + .align 2 + .globl _start + .ent _start +_start: + .set noreorder + + /* Setup stack pointer */ + la sp, _sp + + /* Clear bss */ + la t0, 0x00000000 /* First address */ + la t1, _end /* Last address */ +bbs_zero: + /*sw zero, 0(t0) + bne t0, t1, bbs_zero + addiu t0, 4*/ + + /* Jump to main */ + jal main + nop + + /* Run endless loop when the program terminates */ +loop: + j loop + + .set reorder + .end _start Index: tags/arelease/PROGRAMMING_CLASSIC/My_Program =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: tags/arelease/PROGRAMMING_CLASSIC/My_Program =================================================================== --- tags/arelease/PROGRAMMING_CLASSIC/My_Program (nonexistent) +++ tags/arelease/PROGRAMMING_CLASSIC/My_Program (revision 13)
tags/arelease/PROGRAMMING_CLASSIC/My_Program Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: tags/arelease/PROGRAMMING_CLASSIC/Disassembler/DISASSEMBLER_ELF =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: tags/arelease/PROGRAMMING_CLASSIC/Disassembler/DISASSEMBLER_ELF =================================================================== --- tags/arelease/PROGRAMMING_CLASSIC/Disassembler/DISASSEMBLER_ELF (nonexistent) +++ tags/arelease/PROGRAMMING_CLASSIC/Disassembler/DISASSEMBLER_ELF (revision 13)
tags/arelease/PROGRAMMING_CLASSIC/Disassembler/DISASSEMBLER_ELF Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: tags/arelease/PROGRAMMING_CLASSIC/Disassembler/My_Program.bin =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: tags/arelease/PROGRAMMING_CLASSIC/Disassembler/My_Program.bin =================================================================== --- tags/arelease/PROGRAMMING_CLASSIC/Disassembler/My_Program.bin (nonexistent) +++ tags/arelease/PROGRAMMING_CLASSIC/Disassembler/My_Program.bin (revision 13)
tags/arelease/PROGRAMMING_CLASSIC/Disassembler/My_Program.bin Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: tags/arelease/PROGRAMMING_CLASSIC/Disassembler/readme.txt =================================================================== --- tags/arelease/PROGRAMMING_CLASSIC/Disassembler/readme.txt (nonexistent) +++ tags/arelease/PROGRAMMING_CLASSIC/Disassembler/readme.txt (revision 13) @@ -0,0 +1,11 @@ + +Disassembler for MipsR2000 Processor! +This program converts Bin files into HEX or ASM format! + +Usage: + + Type ./DISASSEMBLER_ELF "progran_name.bin" + where "program_name.bin" is the bin file that you want to convert + + In Run-Time Type "A" for ASM format, or "H" for HEX format, and Hit "Enter" + Index: tags/arelease/PROGRAMMING_CLASSIC/Makefile =================================================================== --- tags/arelease/PROGRAMMING_CLASSIC/Makefile (nonexistent) +++ tags/arelease/PROGRAMMING_CLASSIC/Makefile (revision 13) @@ -0,0 +1,88 @@ +# ********************************************** +# Programs to build +# ********************************************** + +PROGS = My_Program + +# ********************************************** +# Endianness EB | EL +# ********************************************** + +#ENDIAN = EB +ENDIAN = EL + +# ********************************************** +# Bootstrap object file +# ********************************************** + +BOOTSTRAP = crt0.o + +# ********************************************** +# Compiler toolchain +# ********************************************** + +ifeq ($(ENDIAN),EL) +CC = mipsel-linux-gcc +LD = mipsel-linux-ld +OBJCOPY = mipsel-linux-objcopy +OBJDUMP = mipsel-linux-objdump +endif + +ifeq ($(ENDIAN),EB) +CC = mips-linux-gcc +LD = mips-linux-ld +OBJCOPY = mips-linux-objcopy +OBJDUMP = mips-linux-objdump +endif + +# ********************************************** +# Compiler and linker options +# ********************************************** + +W_OPTS = -Wimplicit -Wformat -Wall -Wstrict-prototypes +W_OPTS_A = -Wformat -Wall -Wstrict-prototypes + + +CC_OPTS = -Wa,-32 -mips1 -mno-abicalls -fno-pic -G 0 -pipe \ + -D$(ENDIAN) -fno-strict-aliasing -c -nostdinc + +CC_OPTS_A = -Wa,-32 -mips1 -mno-abicalls -fno-pic -G 0 -pipe \ + -D$(ENDIAN) -fno-strict-aliasing -c -nostdinc + + +LD_SCRIPT = link.xn +LD_OPTS = -G 0 -static -T $(LD_SCRIPT) + +ifeq ($(ENDIAN),EB) +LD_FORMAT = elf32-tradbigmips +endif + +ifeq ($(ENDIAN),EL) +LD_FORMAT = elf32-tradlittlemips +endif + + +# ********************************************** +# Rules +# ********************************************** + +%.o : %.c + $(CC) $(W_OPTS) $(CC_OPTS) -o $@ $< + +%.o : %.S + $(CC) $(W_OPTS_A) $(CC_OPTS_A) -o $@ $< + +%.o : %.s + $(CC) $(W_OPTS_A) $(CC_OPTS_A) -o $@ $< + +all: $(PROGS) + + +My_Program : $(BOOTSTRAP) My_Program.o + $(LD) $(LD_OPTS) -o $@ $? + $(OBJCOPY) -O binary $@ $@.bin + +clean : + rm -f $(PROGS) *.bin *.o + rm -f *~ + Index: tags/arelease/PROGRAMMING_CLASSIC/My_Program.c =================================================================== --- tags/arelease/PROGRAMMING_CLASSIC/My_Program.c (nonexistent) +++ tags/arelease/PROGRAMMING_CLASSIC/My_Program.c (revision 13) @@ -0,0 +1,69 @@ +#define memstore(address,save) { \ +unsigned int *ctrlstore = (unsigned int *) address; \ +*ctrlstore = save;} + +#define ADDR_IO 0x00009000 +#define ADDR_STOP 0x7FFFFFFC +#define ADDR_QUICK 0x00003F00 + + +void quicksort (int a[], int lo, int hi) +{ + int i=lo, j=hi, h; + int x=a[(lo+hi)/2]; + + // partition + do + { + while (a[i]x) j--; + if (i<=j) + { + h=a[i]; a[i]=a[j]; a[j]=h; + i++; j--; + } + } while (i<=j); + + // recursion + if (lo

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