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Rev 12 → Rev 13

/trunk/rtl/verilog/spi_top.v
76,11 → 76,10
reg [32-1:0] wb_dat_o;
reg wb_ack_o;
reg wb_err_o;
reg wb_int_o;
// Internal signals
reg [`SPI_DIVIDER_BIT_NB-1:0] divider; // Divider register
reg [`SPI_DIVIDER_LEN-1:0] divider; // Divider register
reg [`SPI_CTRL_BIT_NB-1:0] ctrl; // Control and status register
reg [`SPI_SS_NB-1:0] ss; // Slave select register
reg [32-1:0] wb_dat; // wb data out
126,12 → 125,30
`SPI_RX_2: wb_dat = 32'b0;
`SPI_RX_3: wb_dat = 32'b0;
`else
`SPI_RX_0: wb_dat = {{32-`SPI_MAX_CHAR{1'b0}}, rx};
`ifdef SPI_MAX_CHAR_32
`SPI_RX_0: wb_dat = rx;
`SPI_RX_1: wb_dat = 32'b0;
`SPI_RX_2: wb_dat = 32'b0;
`SPI_RX_3: wb_dat = 32'b0;
`else
`ifdef SPI_MAX_CHAR_16
`SPI_RX_0: wb_dat = {16'b0, rx};
`SPI_RX_1: wb_dat = 32'b0;
`SPI_RX_2: wb_dat = 32'b0;
`SPI_RX_3: wb_dat = 32'b0;
`else
`ifdef SPI_MAX_CHAR_8
`SPI_RX_0: wb_dat = {24'b0, rx};
`SPI_RX_1: wb_dat = 32'b0;
`SPI_RX_2: wb_dat = 32'b0;
`SPI_RX_3: wb_dat = 32'b0;
`endif
`endif
`endif
`endif
`endif
`SPI_CTRL: wb_dat = {{32-`SPI_CTRL_BIT_NB{1'b0}}, ctrl};
`SPI_DEVIDE: wb_dat = {{32-`SPI_DIVIDER_BIT_NB{1'b0}}, divider};
`SPI_DEVIDE: wb_dat = {{32-`SPI_DIVIDER_LEN{1'b0}}, divider};
`SPI_SS: wb_dat = {{32-`SPI_SS_NB{1'b0}}, ss};
default: wb_dat = 32'bx;
endcase
156,13 → 173,7
end
// Wb error
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
wb_err_o <= #Tp 1'b0;
else
wb_err_o <= #Tp wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111) & ~wb_err_o;
end
assign wb_err_o = 1'b0;
// Interrupt
always @(posedge wb_clk_i or posedge wb_rst_i)
179,9 → 190,30
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
divider <= #Tp {`SPI_DIVIDER_BIT_NB{1'b0}};
divider <= #Tp {`SPI_DIVIDER_LEN{1'b0}};
else if (spi_divider_sel && wb_we_i && !tip)
divider <= #Tp wb_dat_i[`SPI_DIVIDER_BIT_NB-1:0];
begin
`ifdef SPI_DIVIDER_LEN_8
if (wb_sel_i[3])
divider <= #Tp wb_dat_i[7:0];
`endif
`ifdef SPI_DIVIDER_LEN_16
if (wb_sel_i[3])
divider[7:0] <= #Tp wb_dat_i[7:0];
if (wb_sel_i[2])
divider[15:8] <= #Tp wb_dat_i[15:8];
`endif
`ifdef SPI_DIVIDER_LEN_32
if (wb_sel_i[3])
divider[7:0] <= #Tp wb_dat_i[7:0];
if (wb_sel_i[2])
divider[15:8] <= #Tp wb_dat_i[15:8];
if (wb_sel_i[1])
divider[23:16] <= #Tp wb_dat_i[23:16];
if (wb_sel_i[0])
divider[31:24] <= #Tp wb_dat_i[31:24];
`endif
end
end
// Ctrl register
191,13 → 223,10
ctrl <= #Tp {`SPI_CTRL_BIT_NB{1'b0}};
else if(spi_ctrl_sel && wb_we_i && !tip)
begin
ctrl[`SPI_CTRL_GO] <= #Tp wb_dat_i[`SPI_CTRL_GO] | ctrl[`SPI_CTRL_GO];
ctrl[`SPI_CTRL_RX_NEGEDGE] <= #Tp wb_dat_i[`SPI_CTRL_RX_NEGEDGE];
ctrl[`SPI_CTRL_TX_NEGEDGE] <= #Tp wb_dat_i[`SPI_CTRL_TX_NEGEDGE];
ctrl[`SPI_CTRL_CHAR_LEN] <= #Tp wb_dat_i[`SPI_CTRL_CHAR_LEN];
ctrl[`SPI_CTRL_LSB] <= #Tp wb_dat_i[`SPI_CTRL_LSB];
ctrl[`SPI_CTRL_IE] <= #Tp wb_dat_i[`SPI_CTRL_IE];
ctrl[`SPI_CTRL_ASS] <= #Tp wb_dat_i[`SPI_CTRL_ASS];
if (wb_sel_i[3])
ctrl[7:0] <= #Tp wb_dat_i[7:0] | {7'b0, ctrl[0]};
if (wb_sel_i[2])
ctrl[`SPI_CTRL_BIT_NB-1:8] <= #Tp wb_dat_i[`SPI_CTRL_BIT_NB-1:8];
end
else if(tip && last_bit && pos_edge)
ctrl[`SPI_CTRL_GO] <= #Tp 1'b0;
217,7 → 246,28
if (wb_rst_i)
ss <= #Tp {`SPI_SS_NB{1'b0}};
else if(spi_ss_sel && wb_we_i && !tip)
ss <= #Tp wb_dat_i[`SPI_SS_NB-1:0];
begin
`ifdef SPI_SS_NB_8
if (wb_sel_i[3])
ss <= #Tp wb_dat_i[7:0];
`endif
`ifdef SPI_SS_NB_16
if (wb_sel_i[3])
ss[7:0] <= #Tp wb_dat_i[7:0];
if (wb_sel_i[2])
ss[15:8] <= #Tp wb_dat_i[15:8];
`endif
`ifdef SPI_SS_NB_32
if (wb_sel_i[3])
ss[7:0] <= #Tp wb_dat_i[7:0];
if (wb_sel_i[2])
ss[15:8] <= #Tp wb_dat_i[15:8];
if (wb_sel_i[1])
ss[23:16] <= #Tp wb_dat_i[23:16];
if (wb_sel_i[0])
ss[31:24] <= #Tp wb_dat_i[31:24];
`endif
end
end
assign ss_pad_o = ~((ss & {`SPI_SS_NB{tip & ass}}) | (ss & {`SPI_SS_NB{!ass}}));
227,7 → 277,7
.neg_edge(neg_edge));
spi_shift shift (.clk(wb_clk_i), .rst(wb_rst_i), .len(char_len[`SPI_CHAR_LEN_BITS-1:0]),
.latch(spi_tx_sel[3:0] & {4{wb_we_i}}), .lsb(lsb),
.latch(spi_tx_sel[3:0] & {4{wb_we_i}}), .byte_sel(wb_sel_i), .lsb(lsb),
.go(go), .pos_edge(pos_edge), .neg_edge(neg_edge),
.rx_negedge(rx_negedge), .tx_negedge(tx_negedge),
.tip(tip), .last(last_bit),
/trunk/rtl/verilog/spi_clgen.v
50,7 → 50,7
input enable; // clock enable
input go; // start transfer
input last_clk; // last clock
input [`SPI_DIVIDER_BIT_NB-1:0] divider; // clock divider (output clock is divided by this value)
input [`SPI_DIVIDER_LEN-1:0] divider; // clock divider (output clock is divided by this value)
output clk_out; // output clock
output pos_edge; // pulse marking positive edge of clk_out
output neg_edge; // pulse marking negative edge of clk_out
59,25 → 59,25
reg pos_edge;
reg neg_edge;
reg [`SPI_DIVIDER_BIT_NB-1:0] cnt; // clock counter
reg [`SPI_DIVIDER_LEN-1:0] cnt; // clock counter
wire cnt_zero; // conter is equal to zero
wire cnt_one; // conter is equal to one
assign cnt_zero = cnt == {`SPI_DIVIDER_BIT_NB{1'b0}};
assign cnt_one = cnt == {{`SPI_DIVIDER_BIT_NB-1{1'b0}}, 1'b1};
assign cnt_zero = cnt == {`SPI_DIVIDER_LEN{1'b0}};
assign cnt_one = cnt == {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1};
// Counter counts half period
always @(posedge clk_in or posedge rst)
begin
if(rst)
cnt <= #Tp {`SPI_DIVIDER_BIT_NB{1'b1}};
cnt <= #Tp {`SPI_DIVIDER_LEN{1'b1}};
else
begin
if(!enable || cnt_zero)
cnt <= #Tp divider;
else
cnt <= #Tp cnt - {{`SPI_DIVIDER_BIT_NB-1{1'b0}}, 1'b1};
cnt <= #Tp cnt - {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1};
end
end
/trunk/rtl/verilog/spi_defines.v
43,24 → 43,26
// low frequency of system clock this can be reduced.
// Default is 16.
//
`define SPI_DIVIDER_BIT_NB 16
//`define SPI_DIVIDER_LEN_8
`define SPI_DIVIDER_LEN_16
//`define SPI_DIVIDER_LEN_32
 
//
// Maximum nuber of bits that can be send/received at once. Alloved values are
// 128, 64, 32, 16 and 8. SPI_CHAR_LEN_BITS must be also set to 7, 6, 5, 4 or 3 respectively.
// Default is 128.
// If SPI_MAX_CHAR is 64 or 128, SPI_MAX_CHAR_64 or SPI_MAX_CHAR_128 must be defined,
// otherwise comment it out.
// Maximum nuber of bits that can be send/received at once.
//
`define SPI_MAX_CHAR_128 1
//`define SPI_MAX_CHAR_64 1
`define SPI_MAX_CHAR 128
`define SPI_CHAR_LEN_BITS 7
`define SPI_MAX_CHAR_128
//`define SPI_MAX_CHAR_64
//`define SPI_MAX_CHAR_32
//`define SPI_MAX_CHAR_16
//`define SPI_MAX_CHAR_8
 
//
// Number of device select signals.
//
`define SPI_SS_NB 8
`define SPI_SS_NB_8
//`define SPI_SS_NB_16
//`define SPI_SS_NB_32
 
//
// Bits of WISHBONE address used for partial decoding of SPI registers.
//
98,3 → 100,45
`define SPI_CTRL_GO 0
 
 
`ifdef SPI_DIVIDER_LEN_8
`define SPI_DIVIDER_LEN 8
`endif
`ifdef SPI_DIVIDER_LEN_16
`define SPI_DIVIDER_LEN 16
`endif
`ifdef SPI_DIVIDER_LEN_32
`define SPI_DIVIDER_LEN 32
`endif
 
`ifdef SPI_MAX_CHAR_128
`define SPI_MAX_CHAR 128
`define SPI_CHAR_LEN_BITS 7
`endif
`ifdef SPI_MAX_CHAR_64
`define SPI_MAX_CHAR 64
`define SPI_CHAR_LEN_BITS 6
`endif
`ifdef SPI_MAX_CHAR_32
`define SPI_MAX_CHAR 32
`define SPI_CHAR_LEN_BITS 5
`endif
`ifdef SPI_MAX_CHAR_16
`define SPI_MAX_CHAR 16
`define SPI_CHAR_LEN_BITS 4
`endif
`ifdef SPI_MAX_CHAR_8
`define SPI_MAX_CHAR 8
`define SPI_CHAR_LEN_BITS 3
`endif
 
`ifdef SPI_SS_NB_8
`define SPI_SS_NB 8
`endif
`ifdef SPI_SS_NB_16
`define SPI_SS_NB 16
`endif
`ifdef SPI_SS_NB_32
`define SPI_SS_NB 32
`endif
 
 
/trunk/rtl/verilog/spi_shift.v
41,7 → 41,7
`include "spi_defines.v"
`include "timescale.v"
 
module spi_shift (clk, rst, latch, len, lsb, go,
module spi_shift (clk, rst, latch, byte_sel, len, lsb, go,
pos_edge, neg_edge, rx_negedge, tx_negedge,
tip, last,
p_in, p_out, s_clk, s_in, s_out);
51,6 → 51,7
input clk; // system clock
input rst; // reset
input [3:0] latch; // latch signal for storing the data in shift register
input [3:0] byte_sel; // byte select signals for storing the data in shift register
input [`SPI_CHAR_LEN_BITS-1:0] len; // data len in bits (minus one)
input lsb; // lbs first on the line
input go; // start stansfer
128,22 → 129,98
data <= #Tp {`SPI_MAX_CHAR{1'b0}};
`ifdef SPI_MAX_CHAR_128
else if (latch[0] && !tip)
data[31:0] <= #Tp p_in[31:0];
begin
if (byte_sel[0])
data[31:24] <= #Tp p_in[31:24];
if (byte_sel[1])
data[23:16] <= #Tp p_in[23:16];
if (byte_sel[2])
data[15:8] <= #Tp p_in[15:8];
if (byte_sel[3])
data[7:0] <= #Tp p_in[7:0];
end
else if (latch[1] && !tip)
data[63:32] <= #Tp p_in[31:0];
begin
if (byte_sel[0])
data[63:56] <= #Tp p_in[31:24];
if (byte_sel[1])
data[55:48] <= #Tp p_in[23:16];
if (byte_sel[2])
data[47:40] <= #Tp p_in[15:8];
if (byte_sel[3])
data[39:32] <= #Tp p_in[7:0];
end
else if (latch[2] && !tip)
data[95:64] <= #Tp p_in[31:0];
else if (latch[3] && !tip)
data[127:96] <= #Tp p_in[31:0];
begin
if (byte_sel[0])
data[95:88] <= #Tp p_in[31:24];
if (byte_sel[1])
data[87:80] <= #Tp p_in[23:16];
if (byte_sel[2])
data[79:72] <= #Tp p_in[15:8];
if (byte_sel[3])
data[71:64] <= #Tp p_in[7:0];
end
else if (latch[3] && !tip)
begin
if (byte_sel[0])
data[127:120] <= #Tp p_in[31:24];
if (byte_sel[1])
data[119:112] <= #Tp p_in[23:16];
if (byte_sel[2])
data[111:104] <= #Tp p_in[15:8];
if (byte_sel[3])
data[103:96] <= #Tp p_in[7:0];
end
`else
`ifdef SPI_MAX_CHAR_64
else if (latch[0] && !tip)
data[31:0] <= #Tp p_in[31:0];
begin
if (byte_sel[0])
data[31:24] <= #Tp p_in[31:24];
if (byte_sel[1])
data[23:16] <= #Tp p_in[23:16];
if (byte_sel[2])
data[15:8] <= #Tp p_in[15:8];
if (byte_sel[3])
data[7:0] <= #Tp p_in[7:0];
end
else if (latch[1] && !tip)
data[63:32] <= #Tp p_in[31:0];
begin
if (byte_sel[0])
data[63:56] <= #Tp p_in[31:24];
if (byte_sel[1])
data[55:48] <= #Tp p_in[23:16];
if (byte_sel[2])
data[47:40] <= #Tp p_in[15:8];
if (byte_sel[3])
data[39:32] <= #Tp p_in[7:0];
end
`else
else if (latch[0] && !tip)
data <= #Tp p_in[`SPI_MAX_CHAR-1:0];
begin
`ifdef `SPI_MAX_CHAR_8
if (byte_sel[3])
data[`SPI_MAX_CHAR-1:0] <= #Tp p_in[`SPI_MAX_CHAR-1:0];
`endif
`ifdef `SPI_MAX_CHAR_16
if (byte_sel[3])
data[7:0] <= #Tp p_in[7:0];
if (byte_sel[2])
data[15:8] <= #Tp p_in[15:8];
`endif
`ifdef `SPI_MAX_CHAR_32
if (byte_sel[3])
data[7:0] <= #Tp p_in[7:0];
if (byte_sel[2])
data[15:8] <= #Tp p_in[15:8];
if (byte_sel[1])
data[23:16] <= #Tp p_in[23:16];
if (byte_sel[0])
data[31:24] <= #Tp p_in[31:24];
end
`endif
`endif
`endif
else

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