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URL https://opencores.org/ocsvn/storm_core/storm_core/trunk

Subversion Repositories storm_core

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    from Rev 12 to Rev 13
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Rev 12 → Rev 13

/storm_core/trunk/rtl/WB_UNIT.vhd
112,32 → 112,32
 
-- BYTE TRANSFER --
when "01000" => -- byte transfer, no offset, no sign extension
RD_DATA_TMP := x"000000" & ENDIAN_TMP(07 downto 00);
RD_DATA_TMP := x"000000" & ENDIAN_TMP(31 downto 24);
when "01001" => -- byte transfer, no offset, sign extension
RD_DATA_TMP(7 downto 0) := ENDIAN_TMP(07 downto 00);
RD_DATA_TMP(7 downto 0) := ENDIAN_TMP(31 downto 24);
for i in 8 to 31 loop
RD_DATA_TMP(i) := ENDIAN_TMP(07);
RD_DATA_TMP(i) := ENDIAN_TMP(31);
end loop;
when "01010" => -- byte transfer, one byte offset, no sign extension
RD_DATA_TMP := x"000000" & ENDIAN_TMP(15 downto 08);
RD_DATA_TMP := x"000000" & ENDIAN_TMP(23 downto 16);
when "01011" => -- byte transfer, one byte offset, sign extension
RD_DATA_TMP(7 downto 0) := ENDIAN_TMP(15 downto 08);
RD_DATA_TMP(7 downto 0) := ENDIAN_TMP(23 downto 16);
for i in 8 to 31 loop
RD_DATA_TMP(i) := ENDIAN_TMP(15);
RD_DATA_TMP(i) := ENDIAN_TMP(23);
end loop;
when "01100" => -- byte transfer, two bytes offset, no sign extension
RD_DATA_TMP := x"000000" & ENDIAN_TMP(23 downto 16);
RD_DATA_TMP := x"000000" & ENDIAN_TMP(15 downto 08);
when "01101" => -- byte transfer, two bytes offset, sign extension
RD_DATA_TMP(7 downto 0) := ENDIAN_TMP(23 downto 16);
RD_DATA_TMP(7 downto 0) := ENDIAN_TMP(15 downto 08);
for i in 8 to 31 loop
RD_DATA_TMP(i) := ENDIAN_TMP(23);
RD_DATA_TMP(i) := ENDIAN_TMP(15);
end loop;
when "01110" => -- byte transfer, three bytes offset, no sign extension
RD_DATA_TMP := x"000000" & ENDIAN_TMP(31 downto 24);
RD_DATA_TMP := x"000000" & ENDIAN_TMP(07 downto 00);
when "01111" => -- byte transfer, three bytes offset, sign extension
RD_DATA_TMP(7 downto 0) := ENDIAN_TMP(31 downto 24);
RD_DATA_TMP(7 downto 0) := ENDIAN_TMP(07 downto 00);
for i in 8 to 31 loop
RD_DATA_TMP(i) := ENDIAN_TMP(31);
RD_DATA_TMP(i) := ENDIAN_TMP(07);
end loop;
 
-- HALFWORD TRANSFER --
/storm_core/trunk/rtl/ACCESS_ARBITER.vhd
11,7 → 11,7
-- # If you want to disable resource 1, set the #
-- # switch address to 0x00000000. #
-- # ************************************************** #
-- # Version 1.1.0, 30.08.2011 #
-- # Version 1.1.1, 06.09.2011 #
-- ######################################################
 
library IEEE;
120,26 → 120,49
variable TEMP : STD_LOGIC_VECTOR(03 downto 00);
begin
TEMP := CL1_DQ_I & CL1_ADR_I(1 downto 0);
case (TEMP) is
when "0000" | "0001" | "0010" | "0011" => -- WORD with any offset
CL1_BYTE_SEL <= "1111";
when "0100" => -- BYTE with no offset
CL1_BYTE_SEL <= "0001";
when "0101" => -- BYTE with one byte offset
CL1_BYTE_SEL <= "0010";
when "0110" => -- BYTE with two bytes offset
CL1_BYTE_SEL <= "0100";
when "0111" => -- BYTE with three bytes offset
CL1_BYTE_SEL <= "1000";
when "1000" | "1100" => -- HALFWORD with no offset
CL1_BYTE_SEL <= "0011";
when "1001" | "1101" => -- HALFWORD with one byte offset
CL1_BYTE_SEL <= "0110";
when "1010" | "1110" => -- HALFWORD with two bytes offset
CL1_BYTE_SEL <= "1100";
when others => -- HALFWORD with three bytes offset
CL1_BYTE_SEL <= "1001";
end case;
if (USE_BIG_ENDIAN = TRUE) then
case (TEMP) is
when "0000" | "0001" | "0010" | "0011" => -- WORD with any offset
CL1_BYTE_SEL <= "1111";
when "0100" => -- BYTE with no offset
CL1_BYTE_SEL <= "1000";
when "0101" => -- BYTE with one byte offset
CL1_BYTE_SEL <= "0100";
when "0110" => -- BYTE with two bytes offset
CL1_BYTE_SEL <= "0010";
when "0111" => -- BYTE with three bytes offset
CL1_BYTE_SEL <= "0001";
when "1000" | "1100" => -- HALFWORD with no offset
CL1_BYTE_SEL <= "1100";
when "1001" | "1101" => -- HALFWORD with one byte offset
CL1_BYTE_SEL <= "0110";
when "1010" | "1110" => -- HALFWORD with two bytes offset
CL1_BYTE_SEL <= "0011";
when others => -- HALFWORD with three bytes offset
CL1_BYTE_SEL <= "1001";
end case;
else
case (TEMP) is
when "0000" | "0001" | "0010" | "0011" => -- WORD with any offset
CL1_BYTE_SEL <= "1111";
when "0100" => -- BYTE with no offset
CL1_BYTE_SEL <= "0001";
when "0101" => -- BYTE with one byte offset
CL1_BYTE_SEL <= "0010";
when "0110" => -- BYTE with two bytes offset
CL1_BYTE_SEL <= "0100";
when "0111" => -- BYTE with three bytes offset
CL1_BYTE_SEL <= "1000";
when "1000" | "1100" => -- HALFWORD with no offset
CL1_BYTE_SEL <= "0011";
when "1001" | "1101" => -- HALFWORD with one byte offset
CL1_BYTE_SEL <= "0110";
when "1010" | "1110" => -- HALFWORD with two bytes offset
CL1_BYTE_SEL <= "1100";
when others => -- HALFWORD with three bytes offset
CL1_BYTE_SEL <= "1001";
end case;
end if;
end process CLIENT1_DQ_DECODER;
 
 
147,26 → 170,49
variable TEMP : STD_LOGIC_VECTOR(03 downto 00);
begin
TEMP := CL2_DQ_I & CL2_ADR_I(1 downto 0);
case (TEMP) is
when "0000" | "0001" | "0010" | "0011" => -- WORD with any offset
CL2_BYTE_SEL <= "1111";
when "0100" => -- BYTE with no offset
CL2_BYTE_SEL <= "0001";
when "0101" => -- BYTE with one byte offset
CL2_BYTE_SEL <= "0010";
when "0110" => -- BYTE with two bytes offset
CL2_BYTE_SEL <= "0100";
when "0111" => -- BYTE with three bytes offset
CL2_BYTE_SEL <= "1000";
when "1000" | "1100" => -- HALFWORD with no offset
CL2_BYTE_SEL <= "0011";
when "1001" | "1101" => -- HALFWORD with one byte offset
CL2_BYTE_SEL <= "0110";
when "1010" | "1110" => -- HALFWORD with two bytes offset
CL2_BYTE_SEL <= "1100";
when others => -- HALFWORD with three bytes offset
CL2_BYTE_SEL <= "1001";
end case;
if (USE_BIG_ENDIAN = TRUE) then
case (TEMP) is
when "0000" | "0001" | "0010" | "0011" => -- WORD with any offset
CL2_BYTE_SEL <= "1111";
when "0100" => -- BYTE with no offset
CL2_BYTE_SEL <= "1000";
when "0101" => -- BYTE with one byte offset
CL2_BYTE_SEL <= "0100";
when "0110" => -- BYTE with two bytes offset
CL2_BYTE_SEL <= "0010";
when "0111" => -- BYTE with three bytes offset
CL2_BYTE_SEL <= "0001";
when "1000" | "1100" => -- HALFWORD with no offset
CL2_BYTE_SEL <= "1100";
when "1001" | "1101" => -- HALFWORD with one byte offset
CL2_BYTE_SEL <= "0110";
when "1010" | "1110" => -- HALFWORD with two bytes offset
CL2_BYTE_SEL <= "0011";
when others => -- HALFWORD with three bytes offset
CL2_BYTE_SEL <= "1001";
end case;
else
case (TEMP) is
when "0000" | "0001" | "0010" | "0011" => -- WORD with any offset
CL2_BYTE_SEL <= "1111";
when "0100" => -- BYTE with no offset
CL2_BYTE_SEL <= "0001";
when "0101" => -- BYTE with one byte offset
CL2_BYTE_SEL <= "0010";
when "0110" => -- BYTE with two bytes offset
CL2_BYTE_SEL <= "0100";
when "0111" => -- BYTE with three bytes offset
CL2_BYTE_SEL <= "1000";
when "1000" | "1100" => -- HALFWORD with no offset
CL2_BYTE_SEL <= "0011";
when "1001" | "1101" => -- HALFWORD with one byte offset
CL2_BYTE_SEL <= "0110";
when "1010" | "1110" => -- HALFWORD with two bytes offset
CL2_BYTE_SEL <= "1100";
when others => -- HALFWORD with three bytes offset
CL2_BYTE_SEL <= "1001";
end case;
end if;
end process CLIENT2_DQ_DECODER;
 
 
269,12 → 315,12
CL1_DELAY_EN <= CL1_DELAY_EN_NXT;
CL2_DELAY_EN <= CL2_DELAY_EN_NXT;
SAH_EN <= SAH_EN_NXT;
if ((COLLISION and (not COLL_FLAG)) = '0') then
--if ((COLLISION and (not COLL_FLAG)) = '0') then
CL1_RE1_REQ_FF <= CL1_RE1_REQ;
CL1_RE2_REQ_FF <= CL1_RE2_REQ;
CL2_RE1_REQ_FF <= CL2_RE1_REQ;
CL2_RE2_REQ_FF <= CL2_RE2_REQ;
end if;
--end if;
end if;
end if;
end process CTRL_UNIT;
/storm_core/trunk/rtl/STORM_TOP_TB.vhd
84,7 → 84,7
 
-- Wishbone simulation --------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
WB_DATA_I <= (others => '0');
WB_DATA_I <= x"00030000";
WB_ACK_I <= '1';
 
 
/storm_core/trunk/rtl/OPERAND_UNIT.vhd
235,7 → 235,7
HOLD_BUS_OUT(0) <= '1'; -- enable
end if;
elsif (MEM_MATCH = '1') and (ALU_FW_IN(FWD_MEM_R_ACC) = '1') then
elsif (MEM_MATCH = '1') and (MEM_FW_IN(FWD_MEM_R_ACC) = '1') then
-- MEM Register Match with MEM_R access
HOLD_BUS_OUT(2 downto 1) <= "01"; -- 1
HOLD_BUS_OUT(0) <= '1'; -- disable
/storm_core/trunk/rtl/CORE.vhd
137,6 → 137,7
signal EXC_PC : STD_LOGIC_VECTOR(31 downto 0); -- PC value for exceptions
signal WB_CTRL : STD_LOGIC_VECTOR(31 downto 0); -- WB stage control lines
signal WB_DATA_LINE : STD_LOGIC_VECTOR(31 downto 0); -- data write back line
signal MODE_INT : STD_LOGIC_VECTOR(04 downto 0); -- current processor mode
 
begin
-- #######################################################################################################
223,7 → 224,20
I_MEM_ADR <= INF_PC;
I_MEM_DQ <= DQ_WORD;
 
-- Delay 'MODE' for 1 cycle, so it is sync to memory interface signals
-- ------------------------------------------------------------------------------
MODE_SYNC: process(gCLK, gRES, G_HALT)
begin
if rising_edge(gCLK) then
if (gRES = '1') then
MODE <= (others => '0');
elsif (G_HALT = '0') then
MODE <= MODE_INT;
end if;
end if;
end process MODE_SYNC;
 
 
-- #######################################################################################################
-- ## PIPELINE STAGE 2: OPERAND FETCH & INSTRUCITON DECODE ##
-- #######################################################################################################
352,7 → 366,7
ADR_OUT => MEM_ADR_OUT, -- address bypass output
BP_OUT => MEM_BP_OUT, -- bypass(data) output
LDST_FW_OUT => MEM_FW_PATH, -- memory forwarding path
XMEM_MODE => MODE, -- processor mode for access
XMEM_MODE => MODE_INT, -- processor mode for access
XMEM_ADR => D_MEM_ADR, -- D memory address output
XMEM_WR_DTA => D_MEM_WR_DTA, -- memory write data output
XMEM_ACC_REQ => D_MEM_REQ, -- access request
/storm_core/trunk/rtl/LOAD_STORE_UNIT.vhd
114,6 → 114,7
LDST_FW_OUT(FWD_RD_MSB downto FWD_RD_LSB) <= CTRL_IN(CTRL_RD_3 downto CTRL_RD_0);
LDST_FW_OUT(FWD_WB) <= CTRL_IN(CTRL_EN) and CTRL_IN(CTRL_WB_EN);
LDST_FW_OUT(FWD_DATA_MSB downto FWD_DATA_LSB) <= BP_TEMP;
LDST_FW_OUT(FWD_MEM_R_ACC) <= CTRL_IN(CTRL_EN) and CTRL_IN(CTRL_MEM_ACC) and (not CTRL_IN(CTRL_MEM_RW));
 
 
 

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