Subversion Repositories t80

/trunk/syn/xilinx/run/t80_leo.bat

trunk/syn/xilinx/run/t80_leo.bat Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/xilinx/run/t80.bat =================================================================== --- trunk/syn/xilinx/run/t80.bat (nonexistent) +++ trunk/syn/xilinx/run/t80.bat (revision 13) @@ -0,0 +1,44 @@ +set name=t80 +rem set target=xc2v250-cs144-6 +rem set target=xcv300e-pq240-8 +set target=xc2s200-pq208-5 + +if "%2" == "" goto default +set target=%2 +:default + +cd ..\out + +if "%1" == "" goto xst + +set name=t80_leo + +copy ..\bin\t80_leo.pin %name%.ucf + +ngdbuild -p %target% %1 %name%.ngd + +goto builddone + +:xst + +copy ..\bin\%name%.pin %name%.ucf + +xst -ifn ../bin/%name%.scr -ofn ../log/%name%.srp +ngdbuild -p %target% %name%.ngc + +:builddone + +move %name%.bld ..\log + +map -p %target% -cm speed -c 100 -tx on -o %name%_map %name% +move %name%_map.mrp ..\log\%name%.mrp + +par -ol 3 -t 1 -c 0 %name%_map -w %name% +move %name%.par ..\log + +trce %name%.ncd -o ../log/%name%.twr %name%_map.pcf + +bitgen -w %name% +move %name%.bgn ..\log + +cd ..\run

trunk/syn/xilinx/run/t80.bat Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/xilinx/run/t80debug_leo.bat =================================================================== --- trunk/syn/xilinx/run/t80debug_leo.bat (nonexistent) +++ trunk/syn/xilinx/run/t80debug_leo.bat (revision 13) @@ -0,0 +1,10 @@ +cd ..\out + +hex2rom -b ..\..\..\sw\sine.bin MonZ80 11b8s > ..\src\MonZ80_Sine_leo.vhd + +spectrum -file ..\bin\t80debug.tcl +move exemplar.log ..\log\t80debug_leo.srp + +cd ..\run + +t80debug t80debug_leo.edf xc2s200-pq208-5

trunk/syn/xilinx/run/t80debug_leo.bat Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/xilinx/run/t80debug.bat =================================================================== --- trunk/syn/xilinx/run/t80debug.bat (nonexistent) +++ trunk/syn/xilinx/run/t80debug.bat (revision 13) @@ -0,0 +1,46 @@ +set name=t80debug +rem set target=xc2v250-cs144-6 +rem set target=xcv300e-pq240-8 +set target=xc2s200-pq208-5 + +if "%2" == "" goto default +set target=%2 +:default + +cd ..\out + +if "%1" == "" goto xst + +set name=t80debug_leo + +copy ..\bin\t80debug.pin %name%.ucf + +ngdbuild -p %target% %1 %name%.ngd + +goto builddone + +:xst + +xrom MonZ80 11 8 > ..\src\MonZ80_Sine.vhd +hex2rom -b ..\..\..\sw\sine.bin MonZ80 11b8u > MonZ80_sine.ini +copy ..\out\MonZ80_sine.ini + ..\bin\%name%.pin %name%.ucf + +xst -ifn ../bin/%name%.scr -ofn ../log/%name%.srp +ngdbuild -p %target% %name%.ngc + +:builddone + +move %name%.bld ..\log + +map -p %target% -cm speed -c 100 -pr b -timing -tx on -o %name%_map %name% +move %name%_map.mrp ..\log\%name%.mrp + +par -ol 3 -t 1 -c 0 %name%_map -w %name% +move %name%.par ..\log + +trce %name%.ncd -o ../log/%name%.twr %name%_map.pcf + +bitgen -w %name% +move %name%.bgn ..\log + +cd ..\run

trunk/syn/xilinx/run/t80debug.bat Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/xilinx/bin/t80_leo.pin =================================================================== --- trunk/syn/xilinx/bin/t80_leo.pin (nonexistent) +++ trunk/syn/xilinx/bin/t80_leo.pin (revision 13) @@ -0,0 +1,14 @@ +#NET "clk" TNM_NET = "clk"; +#TIMESPEC "TS_clk" = PERIOD "clk" 20 ns HIGH 50%; + +# Leonardo +#NET "Clk" LOC = "P77"; +#NET "Reset_n" LOC = "P133"; +#NET "Port_D(0)" LOC = "P98"; +#NET "Port_D(1)" LOC = "P96"; + +# XST +#NET "clk" LOC = "P77"; +#NET "reset_n" LOC = "P133"; +#NET "port_d<0>" LOC = "P98"; +#NET "port_d<1>" LOC = "P96"; Index: trunk/syn/xilinx/bin/t80.pin =================================================================== --- trunk/syn/xilinx/bin/t80.pin (nonexistent) +++ trunk/syn/xilinx/bin/t80.pin (revision 13) @@ -0,0 +1,14 @@ +#NET "clk" TNM_NET = "clk"; +#TIMESPEC "TS_clk" = PERIOD "clk" 20 ns HIGH 50%; + +# Leonardo +#NET "Clk" LOC = "P77"; +#NET "Reset_n" LOC = "P133"; +#NET "Port_D(0)" LOC = "P98"; +#NET "Port_D(1)" LOC = "P96"; + +# XST +#NET "clk" LOC = "P77"; +#NET "reset_n" LOC = "P133"; +#NET "port_d<0>" LOC = "P98"; +#NET "port_d<1>" LOC = "P96"; Index: trunk/syn/xilinx/bin/t80.scr =================================================================== --- trunk/syn/xilinx/bin/t80.scr (nonexistent) +++ trunk/syn/xilinx/bin/t80.scr (revision 13) @@ -0,0 +1,7 @@ +run +-ifn ../bin/t80.prj +-ifmt VHDL +-ofn ../out/t80.ngc +-ofmt NGC -p xc2s200-pq208-5 +-opt_mode Speed +-opt_level 2 Index: trunk/syn/xilinx/bin/t80debug.tcl =================================================================== --- trunk/syn/xilinx/bin/t80debug.tcl (nonexistent) +++ trunk/syn/xilinx/bin/t80debug.tcl (revision 13) @@ -0,0 +1,43 @@ +set process "5" +set part "2s200pq208" +set tristate_map "FALSE" +set opt_auto_mode "TRUE" +set opt_best_result "29223.458000" +set dont_lock_lcells "auto" +set input2output "20.000000" +set input2register "20.000000" +set register2output "20.000000" +set register2register "20.000000" +set wire_table "xis215-5_avg" +set encoding "auto" +set edifin_ground_port_names "GND" +set edifin_power_port_names "VCC" +set edif_array_range_extraction_style "%s\[%d:%d\]" + +set_xilinx_eqn + +load_library xis2 + +read -technology xis2 { +../../../rtl/vhdl/T80_Pack.vhd +../../../rtl/vhdl/T80_MCode.vhd +../../../rtl/vhdl/T80_ALU.vhd +../../../rtl/vhdl/T80.vhd +../../../rtl/vhdl/T80s.vhd +../../../rtl/vhdl/T16450.vhd +../src/MonZ80_Sine_leo.vhd +../../../rtl/vhdl/SSRAM.vhd +../../../rtl/vhdl/DebugSystem.vhd +} + +pre_optimize + +optimize -hierarchy=auto + +optimize_timing + +report_area + +report_delay + +write t80debug_leo.edf Index: trunk/syn/xilinx/bin/t80.prj =================================================================== --- trunk/syn/xilinx/bin/t80.prj (nonexistent) +++ trunk/syn/xilinx/bin/t80.prj (revision 13) @@ -0,0 +1,5 @@ +../../../rtl/vhdl/T80_Pack.vhd +../../../rtl/vhdl/T80_MCode.vhd +../../../rtl/vhdl/T80_ALU.vhd +../../../rtl/vhdl/T80.vhd +../../../rtl/vhdl/T80s.vhd Index: trunk/syn/xilinx/bin/t80debug.pin =================================================================== --- trunk/syn/xilinx/bin/t80debug.pin (nonexistent) +++ trunk/syn/xilinx/bin/t80debug.pin (revision 13) @@ -0,0 +1,7 @@ +#NET "clk" TNM_NET = "clk"; +#TIMESPEC "TS_clk" = PERIOD "clk" 20 ns HIGH 50%; + +#NET "clk" LOC = "P77"; +#NET "reset_n" LOC = "P133"; +#NET "rxd" LOC = "P98"; +#NET "txd" LOC = "P96"; Index: trunk/syn/xilinx/bin/t80debug.scr =================================================================== --- trunk/syn/xilinx/bin/t80debug.scr (nonexistent) +++ trunk/syn/xilinx/bin/t80debug.scr (revision 13) @@ -0,0 +1,7 @@ +run +-ifn ../bin/t80debug.prj +-ifmt VHDL +-ofn ../out/t80debug.ngc +-ofmt NGC -p xc2s200-pq208-5 +-opt_mode Speed +-opt_level 2 Index: trunk/syn/xilinx/bin/t80.tcl =================================================================== --- trunk/syn/xilinx/bin/t80.tcl (nonexistent) +++ trunk/syn/xilinx/bin/t80.tcl (revision 13) @@ -0,0 +1,39 @@ +set process "5" +set part "2s200pq208" +set tristate_map "FALSE" +set opt_auto_mode "TRUE" +set opt_best_result "29223.458000" +set dont_lock_lcells "auto" +set input2output "20.000000" +set input2register "20.000000" +set register2output "20.000000" +set register2register "20.000000" +set wire_table "xis215-5_avg" +set encoding "auto" +set edifin_ground_port_names "GND" +set edifin_power_port_names "VCC" +set edif_array_range_extraction_style "%s\[%d:%d\]" + +set_xilinx_eqn + +load_library xis2 + +read -technology xis2 { +../../../rtl/vhdl/T80_Pack.vhd +../../../rtl/vhdl/T80_MCode.vhd +../../../rtl/vhdl/T80_ALU.vhd +../../../rtl/vhdl/T80.vhd +../../../rtl/vhdl/T80s.vhd +} + +pre_optimize + +optimize -hierarchy=auto + +optimize_timing + +report_area + +report_delay + +write t80_leo.edf Index: trunk/syn/xilinx/bin/t80debug.prj =================================================================== --- trunk/syn/xilinx/bin/t80debug.prj (nonexistent) +++ trunk/syn/xilinx/bin/t80debug.prj (revision 13) @@ -0,0 +1,9 @@ +../../../rtl/vhdl/T80_Pack.vhd +../../../rtl/vhdl/T80_MCode.vhd +../../../rtl/vhdl/T80_ALU.vhd +../../../rtl/vhdl/T80.vhd +../../../rtl/vhdl/T80s.vhd +../../../rtl/vhdl/T16450.vhd +../src/MonZ80_Sine_leo.vhd +../../../rtl/vhdl/SSRAM.vhd +../../../rtl/vhdl/DebugSystem.vhd