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Rev 12 → Rev 13

/trunk/rtl/verilog/usbf_crc5.v
11,8 → 11,9
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// Copyright (C) 2000-2003 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
37,10 → 38,10
 
// CVS Log
//
// $Id: usbf_crc5.v,v 1.1 2001-08-03 05:30:09 rudi Exp $
// $Id: usbf_crc5.v,v 1.2 2003-10-17 02:36:57 rudi Exp $
//
// $Date: 2001-08-03 05:30:09 $
// $Revision: 1.1 $
// $Date: 2003-10-17 02:36:57 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 48,11
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/08/03 05:30:09 rudi
//
//
// 1) Reorganized directory structure
//
// Revision 1.0 2001/03/07 09:17:12 rudi
//
//
/trunk/rtl/verilog/usbf_utmi_if.v
11,8 → 11,9
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// Copyright (C) 2000-2003 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
37,10 → 38,10
 
// CVS Log
//
// $Id: usbf_utmi_if.v,v 1.3 2001-11-04 12:22:45 rudi Exp $
// $Id: usbf_utmi_if.v,v 1.4 2003-10-17 02:36:57 rudi Exp $
//
// $Date: 2001-11-04 12:22:45 $
// $Revision: 1.3 $
// $Date: 2003-10-17 02:36:57 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 48,11
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/11/04 12:22:45 rudi
//
// - Fixed previous fix (brocke something else ...)
// - Majore Synthesis cleanup
//
// Revision 1.2 2001/09/24 01:15:28 rudi
//
// Changed reset to be active high async.
83,7 → 89,7
`include "usbf_defines.v"
 
module usbf_utmi_if( // UTMI Interface (EXTERNAL)
phy_clk, wclk, rst,
phy_clk, rst,
DataOut, TxValid, TxReady,
RxValid, RxActive, RxError, DataIn,
XcvSelect, TermSel, SuspendM, LineState,
96,11 → 102,11
 
// Misc Interfaces
mode_hs, usb_reset, usb_suspend, usb_attached,
resume_req
resume_req, suspend_clr
);
 
input phy_clk;
input wclk;
//input wclk;
input rst;
 
output [7:0] DataOut;
133,6 → 139,8
output usb_attached; // Attached to USB
input resume_req;
 
output suspend_clr;
 
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
156,20 → 164,32
// RX Interface Input registers
//
 
`ifdef USBF_ASYNC_RESET
always @(posedge phy_clk or negedge rst)
if(!rst) rx_valid <= #1 1'b0;
else rx_valid <= #1 RxValid;
`else
always @(posedge phy_clk)
`endif
if(!rst) rx_valid <= 1'b0;
else rx_valid <= RxValid;
 
`ifdef USBF_ASYNC_RESET
always @(posedge phy_clk or negedge rst)
if(!rst) rx_active <= #1 1'b0;
else rx_active <= #1 RxActive;
`else
always @(posedge phy_clk)
`endif
if(!rst) rx_active <= 1'b0;
else rx_active <= RxActive;
 
`ifdef USBF_ASYNC_RESET
always @(posedge phy_clk or negedge rst)
if(!rst) rx_err <= #1 1'b0;
else rx_err <= #1 RxError;
`else
always @(posedge phy_clk)
`endif
if(!rst) rx_err <= 1'b0;
else rx_err <= RxError;
 
always @(posedge phy_clk)
rx_data <= #1 DataIn;
rx_data <= DataIn;
 
///////////////////////////////////////////////////////////////////
//
177,21 → 197,25
//
 
always @(posedge phy_clk)
if(TxReady | tx_first) DataOut <= #1 tx_data;
if(TxReady || tx_first) DataOut <= tx_data;
else
if(drive_k) DataOut <= #1 8'hff;
if(drive_k) DataOut <= 8'hff;
 
always @(posedge phy_clk)
tx_ready <= #1 TxReady;
tx_ready <= TxReady;
 
always @(posedge phy_clk)
drive_k_r <= #1 drive_k;
drive_k_r <= drive_k;
 
 
`ifdef USBF_ASYNC_RESET
always @(posedge phy_clk or negedge rst)
if(!rst) TxValid <= #1 1'b0;
`else
always @(posedge phy_clk)
`endif
if(!rst) TxValid <= 1'b0;
else
TxValid <= #1 tx_valid | drive_k | tx_valid_last | (TxValid & !(TxReady | drive_k_r));
TxValid <= tx_valid | drive_k | tx_valid_last | (TxValid & !(TxReady | drive_k_r));
 
///////////////////////////////////////////////////////////////////
//
200,7 → 224,6
 
usbf_utmi_ls u0(
.clk( phy_clk ),
.wclk( wclk ),
.rst( rst ),
.resume_req( resume_req ),
.rx_active( rx_active ),
215,7 → 238,8
.mode_hs( mode_hs ),
.usb_reset( usb_reset ),
.usb_suspend( usb_suspend ),
.usb_attached( usb_attached )
.usb_attached( usb_attached ),
.suspend_clr( suspend_clr )
);
 
endmodule
/trunk/rtl/verilog/usbf_pa.v
11,8 → 11,9
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// Copyright (C) 2000-2003 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
37,10 → 38,10
 
// CVS Log
//
// $Id: usbf_pa.v,v 1.5 2001-11-04 12:22:45 rudi Exp $
// $Id: usbf_pa.v,v 1.6 2003-10-17 02:36:57 rudi Exp $
//
// $Date: 2001-11-04 12:22:45 $
// $Revision: 1.5 $
// $Date: 2003-10-17 02:36:57 $
// $Revision: 1.6 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 48,11
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.5 2001/11/04 12:22:45 rudi
//
// - Fixed previous fix (brocke something else ...)
// - Majore Synthesis cleanup
//
// Revision 1.4 2001/09/24 01:15:28 rudi
//
// Changed reset to be active high async.
87,6 → 93,7
// Protocol Engine Interface
send_token, token_pid_sel,
send_data, data_pid_sel,
send_zero_length,
 
// IDMA Interface
tx_data_st, rd_next
106,6 → 113,7
input [1:0] token_pid_sel;
input send_data;
input [1:0] data_pid_sel;
input send_zero_length;
 
// IDMA Interface
input [7:0] tx_data_st;
116,13 → 124,14
// Local Wires and Registers
//
 
parameter [3:0] // synopsys enum state
IDLE = 4'b0001,
DATA = 4'b0010,
CRC1 = 4'b0100,
CRC2 = 4'b1000;
parameter [4:0] // synopsys enum state
IDLE = 5'b00001,
DATA = 5'b00010,
CRC1 = 5'b00100,
CRC2 = 5'b01000,
WAIT = 5'b10000;
 
reg [3:0] /* synopsys enum state */ state, next_state;
reg [4:0] /* synopsys enum state */ state, next_state;
// synopsys state_vector state
 
reg last;
146,6 → 155,8
reg send_data_r2;
reg tx_valid_r;
reg tx_valid_r1;
reg zero_length_r;
reg send_zero_length_r;
 
///////////////////////////////////////////////////////////////////
//
153,17 → 164,35
//
 
always @(posedge clk)
tx_valid_r1 <= #1 tx_valid;
send_zero_length_r <= send_zero_length;
 
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
tx_valid_r <= #1 tx_valid_r1;
`endif
if(!rst) zero_length_r <= 1'b0;
else
if(last) zero_length_r <= 1'b0;
else
if(crc16_clr) zero_length_r <= send_zero_length_r;
 
always @(posedge clk)
tx_valid_r1 <= tx_valid;
 
always @(posedge clk)
tx_valid_r <= tx_valid_r1;
 
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
if(!rst) send_token_r <= #1 1'b0;
`else
always @(posedge clk)
`endif
if(!rst) send_token_r <= 1'b0;
else
if(send_token) send_token_r <= #1 1'b1;
if(send_token) send_token_r <= 1'b1;
else
if(tx_ready) send_token_r <= #1 1'b0;
if(tx_ready) send_token_r <= 1'b0;
 
// PID Select
always @(token_pid_sel)
185,7 → 214,7
// Data path Muxes
 
always @(send_token or send_token_r or token_pid or tx_data_data)
if(send_token | send_token_r) tx_data_d = token_pid;
if(send_token || send_token_r) tx_data_d = token_pid;
else tx_data_d = tx_data_data;
 
always @(dsel or tx_data_st or tx_spec_data)
193,7 → 222,7
else tx_data_data = tx_data_st;
 
always @(crc_sel1 or crc_sel2 or data_pid or crc16_rev)
if(!crc_sel1 & !crc_sel2) tx_spec_data = data_pid;
if(!crc_sel1 && !crc_sel2) tx_spec_data = data_pid;
else
if(crc_sel1) tx_spec_data = crc16_rev[15:8]; // CRC 1
else tx_spec_data = crc16_rev[7:0]; // CRC 2
205,24 → 234,25
assign tx_valid = tx_valid_d;
 
always @(posedge clk)
tx_first_r <= #1 send_token | send_data;
tx_first_r <= send_token | send_data;
 
assign tx_first = (send_token | send_data) & ! tx_first_r;
 
// CRC Logic
always @(posedge clk)
send_data_r <= #1 send_data;
send_data_r <= send_data;
 
always @(posedge clk)
send_data_r2 <= #1 send_data_r;
send_data_r2 <= send_data_r;
 
assign crc16_clr = send_data & !send_data_r;
assign crc16_add = (send_data_r & !send_data_r2) | (rd_next & !crc_sel1);
 
assign crc16_add = !zero_length_r & (send_data_r & !send_data_r2) | (rd_next & !crc_sel1);
 
always @(posedge clk)
if(crc16_clr) crc16 <= #1 16'hffff;
if(crc16_clr) crc16 <= 16'hffff;
else
if(crc16_add) crc16 <= #1 crc16_next;
if(crc16_add) crc16 <= crc16_next;
 
 
usbf_crc16 u1(
255,11 → 285,15
// Transmit/Encode state machine
//
 
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
if(!rst) state <= #1 IDLE;
else state <= #1 next_state;
`else
always @(posedge clk)
`endif
if(!rst) state <= IDLE;
else state <= next_state;
 
always @(state or send_data or tx_ready or tx_valid_r)
always @(state or send_data or tx_ready or tx_valid_r or send_zero_length_r)
begin
next_state = state; // Default don't change current state
tx_valid_d = 1'b0;
271,9 → 305,16
case(state) // synopsys full_case parallel_case
IDLE:
begin
if(send_data) // Send DATA packet
if(send_zero_length_r && send_data)
begin
tx_valid_d = 1'b1;
next_state = WAIT;
dsel = 1'b1;
end
else
if(send_data) // Send DATA packet
begin
tx_valid_d = 1'b1;
next_state = DATA;
dsel = 1'b1;
end
280,11 → 321,11
end
DATA:
begin
if(tx_ready & tx_valid_r)
if(tx_ready && tx_valid_r)
rd_next = 1'b1;
 
tx_valid_d = 1'b1;
if(!send_data & tx_ready & tx_valid_r)
if(!send_data && tx_ready && tx_valid_r)
begin
dsel = 1'b1;
crc_sel1 = 1'b1;
291,6 → 332,13
next_state = CRC1;
end
end
WAIT: // In case of early tx_ready ...
begin
crc_sel1 = 1'b1;
dsel = 1'b1;
tx_valid_d = 1'b1;
next_state = CRC1;
end
CRC1:
begin
dsel = 1'b1;
/trunk/rtl/verilog/usbf_mem_arb.v
12,8 → 12,9
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// Copyright (C) 2000-2003 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
38,10 → 39,10
 
// CVS Log
//
// $Id: usbf_mem_arb.v,v 1.2 2001-11-04 12:22:45 rudi Exp $
// $Id: usbf_mem_arb.v,v 1.3 2003-10-17 02:36:57 rudi Exp $
//
// $Date: 2001-11-04 12:22:45 $
// $Revision: 1.2 $
// $Date: 2003-10-17 02:36:57 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 49,11
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/11/04 12:22:45 rudi
//
// - Fixed previous fix (brocke something else ...)
// - Majore Synthesis cleanup
//
// Revision 1.1 2001/08/03 05:30:09 rudi
//
//
119,8 → 125,7
reg [SSRAM_HADR:0] sram_adr;
reg [31:0] sram_dout;
reg sram_we;
reg mack;
reg mack_r;
wire mack;
wire mcyc;
reg wack_r;
 
149,7 → 154,7
else sram_adr = madr;
 
// Write Enable Path
always @(wsel or wack or wwe or wreq or mwe or mcyc)
always @(wsel or wwe or wreq or mwe or mcyc)
if(wsel) sram_we = wreq & wwe;
else sram_we = mwe & mcyc;
 
157,14 → 162,11
 
// -----------------------------------------
// IDMA specific
 
assign mdout = sram_din;
 
always @(mreq)
mack = mreq;
assign mack = mreq;
 
always @(posedge phy_clk)
mack_r <= #1 mack;
 
assign mcyc = mack; // Qualifier for writes
 
// -----------------------------------------
173,8 → 175,13
 
assign wack = wack_r & !mreq;
 
`ifdef USBF_ASYNC_RESET
always @(posedge phy_clk or negedge rst)
`else
always @(posedge phy_clk)
wack_r <= #1 wreq & !mreq & !wack;
`endif
if(!rst) wack_r <= 1'b0;
else wack_r <= wreq & !mreq & !wack;
 
endmodule
 
/trunk/rtl/verilog/usbf_top.v
11,8 → 11,9
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// Copyright (C) 2000-2003 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
37,10 → 38,10
 
// CVS Log
//
// $Id: usbf_top.v,v 1.5 2001-11-04 12:22:45 rudi Exp $
// $Id: usbf_top.v,v 1.6 2003-10-17 02:36:57 rudi Exp $
//
// $Date: 2001-11-04 12:22:45 $
// $Revision: 1.5 $
// $Date: 2003-10-17 02:36:57 $
// $Revision: 1.6 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 48,11
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.5 2001/11/04 12:22:45 rudi
//
// - Fixed previous fix (brocke something else ...)
// - Majore Synthesis cleanup
//
// Revision 1.4 2001/11/03 03:26:23 rudi
//
// - Fixed several interrupt and error condition reporting bugs
230,27 → 236,53
wire rf_resume_req; // Resume Request From main CSR
 
reg susp_o;
reg [1:0] LineState_r; // Added to make a full synchronizer
reg [7:0] VStatus_r; // Added to make a full synchronizer
 
///////////////////////////////////////////////////////////////////
//
// Misc Logic
//
assign rst = ~rst_i;
assign rst = rst_i;
assign phy_rst_pad_o = rst_i;
assign resume_req = resume_req_i;
 
always @(posedge clk_i)
susp_o <= #1 usb_suspend;
susp_o <= usb_suspend;
 
always @(posedge phy_clk_pad_i) // First Stage Synchronizer
LineState_r <= LineState_pad_i;
 
always @(posedge phy_clk_pad_i) // First Stage Synchronizer
VStatus_r <= VStatus_pad_i;
 
///////////////////////////////////////////////////////////////////
//
// Module Instantiations
//
 
reg resume_req_r;
reg suspend_clr_wr;
wire suspend_clr;
 
always @(posedge clk_i)
suspend_clr_wr <= suspend_clr;
 
`ifdef USBF_ASYNC_RESET
always @(posedge clk_i or negedge rst)
`else
always @(posedge clk_i)
`endif
if(!rst) resume_req_r <= 1'b0;
else
if(suspend_clr_wr) resume_req_r <= 1'b0;
else
if(resume_req) resume_req_r <= 1'b1;
 
 
// UTMI Interface
usbf_utmi_if u0(
.phy_clk( phy_clk_pad_i ),
.wclk( clk_i ),
.rst( rst ),
.DataOut( DataOut_pad_o ),
.TxValid( TxValid_pad_o ),
262,7 → 294,7
.XcvSelect( XcvSelect_pad_o ),
.TermSel( TermSel_pad_o ),
.SuspendM( SuspendM_pad_o ),
.LineState( LineState_pad_i ),
.LineState( LineState_r ),
.OpMode( OpMode_pad_o ),
.usb_vbus( usb_vbus_pad_i ),
.rx_data( rx_data ),
278,7 → 310,8
.usb_reset( usb_reset ),
.usb_suspend( usb_suspend ),
.usb_attached( usb_attached ),
.resume_req( resume_req )
.resume_req( resume_req_r ),
.suspend_clr( suspend_clr )
);
 
// Protocol Layer
359,25 → 392,8
.wack( ma_ack )
);
 
 
// SSRAM
/*
 
The SSRAM is now external to the USB Function core
 
ssram u3( .clk( phy_clk ),
.rst( rst ),
.adr( sram_adr ),
.din( sram_din ),
.dout( sram_dout ),
.re( sram_re ),
.we( sram_we )
);
*/
 
// Register File
usbf_rf #(SSRAM_HADR)
u4( .clk( phy_clk_pad_i ),
usbf_rf u4( .clk( phy_clk_pad_i ),
.wclk( clk_i ),
.rst( rst ),
 
413,10 → 429,10
.dma_in_buf_sz1( dma_in_buf_sz1 ),
.dma_out_buf_avail( dma_out_buf_avail ),
.frm_nat( frm_nat ),
.utmi_vend_stat( VStatus_pad_i ),
.utmi_vend_stat( VStatus_r ),
.utmi_vend_ctrl( VControl_pad_o ),
.utmi_vend_wr( VControl_Load_pad_o ),
.line_stat( LineState_pad_i ),
.line_stat( LineState_r ),
.usb_attached( usb_attached ),
.mode_hs( mode_hs ),
.suspend( usb_suspend ),
/trunk/rtl/verilog/usbf_pd.v
11,8 → 11,9
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// Copyright (C) 2000-2003 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
37,10 → 38,10
 
// CVS Log
//
// $Id: usbf_pd.v,v 1.6 2001-11-04 12:22:45 rudi Exp $
// $Id: usbf_pd.v,v 1.7 2003-10-17 02:36:57 rudi Exp $
//
// $Date: 2001-11-04 12:22:45 $
// $Revision: 1.6 $
// $Date: 2003-10-17 02:36:57 $
// $Revision: 1.7 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
180,10 → 181,10
 
reg seq_err; // State machine sequence error
 
reg pid_ack;
reg got_pid_ack;
 
reg token_valid_r1;
reg token_valid_str1, token_valid_str2;
reg token_valid_str1;
 
reg rx_active_r;
 
201,10 → 202,14
// PID Decoding Logic
assign pid_ld_en = pid_le_sm & rx_active & rx_valid;
 
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
if(!rst) pid <= #1 8'hf0;
`else
always @(posedge clk)
`endif
if(!rst) pid <= 8'hf0;
else
if(pid_ld_en) pid <= #1 rx_data;
if(pid_ld_en) pid <= rx_data;
 
assign pid_cks_err = (pid[3:0] != ~pid[7:4]);
 
231,21 → 236,17
 
// Token Decoding LOGIC
always @(posedge clk)
if(token_le_1) token0 <= #1 rx_data;
if(token_le_1) token0 <= rx_data;
 
always @(posedge clk)
if(token_le_2) token1 <= #1 rx_data;
if(token_le_2) token1 <= rx_data;
 
always @(posedge clk)
token_valid_r1 <= #1 token_le_2;
token_valid_r1 <= token_le_2;
 
always @(posedge clk)
token_valid_str1 <= #1 token_valid_r1 | pid_ack;
token_valid_str1 <= token_valid_r1 | got_pid_ack;
 
always @(posedge clk)
token_valid_str2 <= #1 token_valid_str1;
 
//assign token_valid = token_valid_str1 | token_valid_str2;
assign token_valid = token_valid_str1;
 
// CRC 5 should perform the check in one cycle (flow through logic)
252,21 → 253,8
// 11 bits and crc5 input, 1 bit output
assign crc5_err = token_valid & (crc5_out2 != token_crc5);
 
/*
always @(token_valid)
if(token_valid)
begin
#1;
$display("Got valid token: addr %b ep: %b pid: %h",
token_fadr, token_endp, pid);
$display("rx crc: %b, calc crc: %b crc5_err: %b",
token_crc5, crc5_out2, crc5_err);
$display("frnat: %h", frame_no);
end
*/
usbf_crc5 u0(
.crc_in( 5'h1f ),
.crc_in( 5'h1f ),
.din( { token_fadr[0],
token_fadr[1],
token_fadr[2],
277,8 → 265,8
token_endp[0],
token_endp[1],
token_endp[2],
token_endp[3] } ),
.crc_out( crc5_out ) );
token_endp[3] } ),
.crc_out( crc5_out ) );
 
// Invert and reverse result bits
assign crc5_out2 = ~{crc5_out[0], crc5_out[1], crc5_out[2], crc5_out[3],
291,28 → 279,36
 
// Data receiving logic
// build a delay line and stop when we are about to get crc
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
if(!rst) rxv1 <= #1 1'b0;
`else
always @(posedge clk)
`endif
if(!rst) rxv1 <= 1'b0;
else
if(data_valid_d) rxv1 <= #1 1'b1;
if(data_valid_d) rxv1 <= 1'b1;
else
if(data_done) rxv1 <= #1 1'b0;
if(data_done) rxv1 <= 1'b0;
 
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
if(!rst) rxv2 <= #1 1'b0;
`else
always @(posedge clk)
`endif
if(!rst) rxv2 <= 1'b0;
else
if(rxv1 & data_valid_d) rxv2 <= #1 1'b1;
if(rxv1 && data_valid_d)rxv2 <= 1'b1;
else
if(data_done) rxv2 <= #1 1'b0;
if(data_done) rxv2 <= 1'b0;
 
always @(posedge clk)
data_valid0 <= #1 rxv2 & data_valid_d;
data_valid0 <= rxv2 & data_valid_d;
 
always @(posedge clk)
begin
if(data_valid_d) d0 <= #1 rx_data;
if(data_valid_d) d1 <= #1 d0;
if(data_valid_d) d2 <= #1 d1;
if(data_valid_d) d0 <= rx_data;
if(data_valid_d) d1 <= d0;
if(data_valid_d) d2 <= d1;
end
 
assign rx_data_st = d2;
323,14 → 319,14
// when data_done is asserted, crc16 reports status, and resets itself
// next cycle.
always @(posedge clk)
rx_active_r <= #1 rx_active;
rx_active_r <= rx_active;
 
assign crc16_clr = rx_active & !rx_active_r;
 
always @(posedge clk)
if(crc16_clr) crc16_sum <= #1 16'hffff;
if(crc16_clr) crc16_sum <= 16'hffff;
else
if(data_valid_d) crc16_sum <= #1 crc16_out;
if(data_valid_d) crc16_sum <= crc16_out;
 
usbf_crc16 u1(
.crc_in( crc16_sum ),
341,32 → 337,18
// Verify against polynomial
assign crc16_err = data_done & (crc16_sum != 16'h800d);
 
/*
always @(posedge clk)
if(data_valid_d)
begin
#1;
$display("RX data: %h (%t)", rx_data, $time);
end
 
always @(data_done)
if(data_done)
begin
#5;
$display("crc16_out: %b (%h) (%t)",
crc16_out, crc16_out, $time);
$display("crc16_err: %b", crc16_err);
 
end
*/
///////////////////////////////////////////////////////////////////
//
// Receive/Decode State machine
//
 
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
if(!rst) state <= #1 IDLE;
else state <= #1 next_state;
`else
always @(posedge clk)
`endif
if(!rst) state <= IDLE;
else state <= next_state;
 
always @(state or rx_valid or rx_active or rx_err or pid_ACK or pid_TOKEN
or pid_DATA)
378,24 → 360,24
data_valid_d = 1'b0;
data_done = 1'b0;
seq_err = 1'b0;
pid_ack = 1'b0;
got_pid_ack = 1'b0;
case(state) // synopsys full_case parallel_case
IDLE:
begin
pid_le_sm = 1'b1;
if(rx_valid & rx_active) next_state = ACTIVE;
if(rx_valid && rx_active) next_state = ACTIVE;
end
ACTIVE:
begin
// Received a ACK from Host
if(pid_ACK & !rx_err)
if(pid_ACK && !rx_err)
begin
pid_ack = 1'b1;
got_pid_ack = 1'b1;
if(!rx_active) next_state = IDLE;
end
else
// Receiving a TOKEN
if(pid_TOKEN & rx_valid & rx_active & !rx_err)
if(pid_TOKEN && rx_valid && rx_active && !rx_err)
begin
token_le_1 = 1'b1;
next_state = TOKEN;
402,14 → 384,14
end
else
// Receiving DATA
if(pid_DATA & rx_valid & rx_active & !rx_err)
if(pid_DATA && rx_valid && rx_active && !rx_err)
begin
data_valid_d = 1'b1;
next_state = DATA;
end
else
if( !rx_active | rx_err |
(rx_valid & !(pid_TOKEN | pid_DATA)) ) // ERROR
if( !rx_active || rx_err ||
(rx_valid && !(pid_TOKEN || pid_DATA)) )
begin
seq_err = !rx_err;
if(!rx_active) next_state = IDLE;
417,14 → 399,13
end
TOKEN:
begin
if(rx_valid & rx_active & !rx_err)
if(rx_valid && rx_active && !rx_err)
begin
token_le_2 = 1'b1;
//if(!rx_active) next_state = IDLE;
next_state = IDLE;
end
else
if(!rx_active | rx_err) // ERROR
if(!rx_active || rx_err)
begin
seq_err = !rx_err;
if(!rx_active) next_state = IDLE;
432,8 → 413,8
end
DATA:
begin
if(rx_valid & rx_active & !rx_err) data_valid_d = 1'b1;
if(!rx_active | rx_err)
if(rx_valid && rx_active && !rx_err) data_valid_d = 1'b1;
if(!rx_active || rx_err)
begin
data_done = 1'b1;
if(!rx_active) next_state = IDLE;
/trunk/rtl/verilog/usbf_pe.v
11,8 → 11,9
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// Copyright (C) 2000-2003 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
37,10 → 38,10
 
// CVS Log
//
// $Id: usbf_pe.v,v 1.7 2001-11-04 12:22:45 rudi Exp $
// $Id: usbf_pe.v,v 1.8 2003-10-17 02:36:57 rudi Exp $
//
// $Date: 2001-11-04 12:22:45 $
// $Revision: 1.7 $
// $Date: 2003-10-17 02:36:57 $
// $Revision: 1.8 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 48,11
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.7 2001/11/04 12:22:45 rudi
//
// - Fixed previous fix (brocke something else ...)
// - Majore Synthesis cleanup
//
// Revision 1.6 2001/11/03 03:26:22 rudi
//
// - Fixed several interrupt and error condition reporting bugs
122,7 → 128,7
 
// Packet Assembler Interface
send_token, token_pid_sel,
data_pid_sel,
data_pid_sel, send_zero_length,
 
// IDMA Interface
rx_dma_en, tx_dma_en,
169,6 → 175,7
output send_token;
output [1:0] token_pid_sel;
output [1:0] data_pid_sel;
output send_zero_length;
 
// IDMA Interface
output rx_dma_en; // Allows the data to be stored
336,6 → 343,8
 
reg buf0_not_aloc, buf1_not_aloc;
 
reg send_zero_length;
 
///////////////////////////////////////////////////////////////////
//
// Misc Logic
370,30 → 379,30
 
// Buffers Not Available
always @(posedge clk)
buf0_na <= #1 buf0[31] | ( &buf0_adr );
buf0_na <= buf0[31] | ( &buf0_adr );
 
always @(posedge clk)
buf1_na <= #1 buf1[31] | ( &buf1_adr );
buf1_na <= buf1[31] | ( &buf1_adr );
 
// Buffer Not Allocated
always @(posedge clk)
buf0_not_aloc <= #1 &buf0_adr;
buf0_not_aloc <= &buf0_adr;
 
always @(posedge clk)
buf1_not_aloc <= #1 &buf1_adr;
buf1_not_aloc <= &buf1_adr;
 
always @(posedge clk)
match_r <= #1 match;
match_r <= match;
 
// No Such Endpoint Indicator
always @(posedge clk)
nse_err <= #1 token_valid & (pid_OUT | pid_IN | pid_SETUP) & !match;
nse_err <= token_valid & (pid_OUT | pid_IN | pid_SETUP) & !match;
 
always @(posedge clk)
send_token <= #1 send_token_d;
send_token <= send_token_d;
 
always @(posedge clk)
token_pid_sel <= #1 token_pid_sel_d;
token_pid_sel <= token_pid_sel_d;
 
///////////////////////////////////////////////////////////////////
//
404,22 → 413,22
 
always @(posedge clk) // tr/mf:ep/type:tr/type:last dpd
casex({tr_fr_d,csr[27:26],csr[25:24],uc_dpd}) // synopsys full_case parallel_case
8'b0?_01_01_??: next_dpid <= #1 2'b00; // ISO txfr. IN, 1 tr/mf
8'b0?_01_01_??: next_dpid <= 2'b00; // ISO txfr. IN, 1 tr/mf
 
8'b10_01_01_?0: next_dpid <= #1 2'b01; // ISO txfr. IN, 2 tr/mf
8'b10_01_01_?1: next_dpid <= #1 2'b00; // ISO txfr. IN, 2 tr/mf
8'b10_01_01_?0: next_dpid <= 2'b01; // ISO txfr. IN, 2 tr/mf
8'b10_01_01_?1: next_dpid <= 2'b00; // ISO txfr. IN, 2 tr/mf
 
8'b11_01_01_00: next_dpid <= #1 2'b01; // ISO txfr. IN, 3 tr/mf
8'b11_01_01_01: next_dpid <= #1 2'b10; // ISO txfr. IN, 3 tr/mf
8'b11_01_01_10: next_dpid <= #1 2'b00; // ISO txfr. IN, 3 tr/mf
8'b11_01_01_00: next_dpid <= 2'b01; // ISO txfr. IN, 3 tr/mf
8'b11_01_01_01: next_dpid <= 2'b10; // ISO txfr. IN, 3 tr/mf
8'b11_01_01_10: next_dpid <= 2'b00; // ISO txfr. IN, 3 tr/mf
 
8'b0?_10_01_??: next_dpid <= #1 2'b00; // ISO txfr. OUT, 1 tr/mf
8'b0?_10_01_??: next_dpid <= 2'b00; // ISO txfr. OUT, 1 tr/mf
 
8'b10_10_01_??: // ISO txfr. OUT, 2 tr/mf
begin // Resynchronize in case of PID error
case({pid_MDATA, pid_DATA1}) // synopsys full_case parallel_case
2'b10: next_dpid <= #1 2'b01;
2'b01: next_dpid <= #1 2'b00;
2'b10: next_dpid <= 2'b01;
2'b01: next_dpid <= 2'b00;
endcase
end
 
426,44 → 435,44
8'b11_10_01_00: // ISO txfr. OUT, 3 tr/mf
begin // Resynchronize in case of PID error
case({pid_MDATA, pid_DATA2}) // synopsys full_case parallel_case
2'b10: next_dpid <= #1 2'b01;
2'b01: next_dpid <= #1 2'b00;
2'b10: next_dpid <= 2'b01;
2'b01: next_dpid <= 2'b00;
endcase
end
8'b11_10_01_01: // ISO txfr. OUT, 3 tr/mf
begin // Resynchronize in case of PID error
case({pid_MDATA, pid_DATA2}) // synopsys full_case parallel_case
2'b10: next_dpid <= #1 2'b10;
2'b01: next_dpid <= #1 2'b00;
2'b10: next_dpid <= 2'b10;
2'b01: next_dpid <= 2'b00;
endcase
end
8'b11_10_01_10: // ISO txfr. OUT, 3 tr/mf
begin // Resynchronize in case of PID error
case({pid_MDATA, pid_DATA2}) // synopsys full_case parallel_case
2'b10: next_dpid <= #1 2'b01;
2'b01: next_dpid <= #1 2'b00;
2'b10: next_dpid <= 2'b01;
2'b01: next_dpid <= 2'b00;
endcase
end
 
8'b??_01_00_?0, // IN/OUT endpoint only
8'b??_10_00_?0: next_dpid <= #1 2'b01; // INT transfers
8'b??_10_00_?0: next_dpid <= 2'b01; // INT transfers
 
8'b??_01_00_?1, // IN/OUT endpoint only
8'b??_10_00_?1: next_dpid <= #1 2'b00; // INT transfers
8'b??_10_00_?1: next_dpid <= 2'b00; // INT transfers
 
8'b??_01_10_?0, // IN/OUT endpoint only
8'b??_10_10_?0: next_dpid <= #1 2'b01; // BULK transfers
8'b??_10_10_?0: next_dpid <= 2'b01; // BULK transfers
 
8'b??_01_10_?1, // IN/OUT endpoint only
8'b??_10_10_?1: next_dpid <= #1 2'b00; // BULK transfers
8'b??_10_10_?1: next_dpid <= 2'b00; // BULK transfers
 
8'b??_00_??_??: // CTRL Endpoint
casex({setup_token, in_op, out_op, uc_dpd}) // synopsys full_case parallel_case
5'b1_??_??: next_dpid <= #1 2'b11; // SETUP operation
5'b0_10_0?: next_dpid <= #1 2'b11; // IN operation
5'b0_10_1?: next_dpid <= #1 2'b01; // IN operation
5'b0_01_?0: next_dpid <= #1 2'b11; // OUT operation
5'b0_01_?1: next_dpid <= #1 2'b10; // OUT operation
5'b1_??_??: next_dpid <= 2'b11; // SETUP operation
5'b0_10_0?: next_dpid <= 2'b11; // IN operation
5'b0_10_1?: next_dpid <= 2'b01; // IN operation
5'b0_01_?0: next_dpid <= 2'b11; // OUT operation
5'b0_01_?1: next_dpid <= 2'b10; // OUT operation
endcase
 
endcase
481,42 → 490,42
 
always @(posedge clk) // tf/mf:ep/type:tr/type:last dpd
casex({tr_fr_d,csr[27:26],csr[25:24],uc_dpd}) // synopsys full_case parallel_case
8'b0?_01_01_??: this_dpid <= #1 2'b00; // ISO txfr. IN, 1 tr/mf
8'b0?_01_01_??: this_dpid <= 2'b00; // ISO txfr. IN, 1 tr/mf
 
8'b10_01_01_?0: this_dpid <= #1 2'b01; // ISO txfr. IN, 2 tr/mf
8'b10_01_01_?1: this_dpid <= #1 2'b00; // ISO txfr. IN, 2 tr/mf
8'b10_01_01_?0: this_dpid <= 2'b01; // ISO txfr. IN, 2 tr/mf
8'b10_01_01_?1: this_dpid <= 2'b00; // ISO txfr. IN, 2 tr/mf
 
8'b11_01_01_00: this_dpid <= #1 2'b10; // ISO txfr. IN, 3 tr/mf
8'b11_01_01_01: this_dpid <= #1 2'b01; // ISO txfr. IN, 3 tr/mf
8'b11_01_01_10: this_dpid <= #1 2'b00; // ISO txfr. IN, 3 tr/mf
8'b11_01_01_00: this_dpid <= 2'b10; // ISO txfr. IN, 3 tr/mf
8'b11_01_01_01: this_dpid <= 2'b01; // ISO txfr. IN, 3 tr/mf
8'b11_01_01_10: this_dpid <= 2'b00; // ISO txfr. IN, 3 tr/mf
 
8'b00_10_01_??: this_dpid <= #1 allow_pid; // ISO txfr. OUT, 0 tr/mf
8'b01_10_01_??: this_dpid <= #1 2'b00; // ISO txfr. OUT, 1 tr/mf
8'b00_10_01_??: this_dpid <= allow_pid; // ISO txfr. OUT, 0 tr/mf
8'b01_10_01_??: this_dpid <= 2'b00; // ISO txfr. OUT, 1 tr/mf
 
8'b10_10_01_?0: this_dpid <= #1 2'b11; // ISO txfr. OUT, 2 tr/mf
8'b10_10_01_?1: this_dpid <= #1 2'b01; // ISO txfr. OUT, 2 tr/mf
8'b10_10_01_?0: this_dpid <= 2'b11; // ISO txfr. OUT, 2 tr/mf
8'b10_10_01_?1: this_dpid <= 2'b01; // ISO txfr. OUT, 2 tr/mf
 
8'b11_10_01_00: this_dpid <= #1 2'b11; // ISO txfr. OUT, 3 tr/mf
8'b11_10_01_01: this_dpid <= #1 2'b11; // ISO txfr. OUT, 3 tr/mf
8'b11_10_01_10: this_dpid <= #1 2'b10; // ISO txfr. OUT, 3 tr/mf
8'b11_10_01_00: this_dpid <= 2'b11; // ISO txfr. OUT, 3 tr/mf
8'b11_10_01_01: this_dpid <= 2'b11; // ISO txfr. OUT, 3 tr/mf
8'b11_10_01_10: this_dpid <= 2'b10; // ISO txfr. OUT, 3 tr/mf
 
8'b??_01_00_?0, // IN/OUT endpoint only
8'b??_10_00_?0: this_dpid <= #1 2'b00; // INT transfers
8'b??_10_00_?0: this_dpid <= 2'b00; // INT transfers
8'b??_01_00_?1, // IN/OUT endpoint only
8'b??_10_00_?1: this_dpid <= #1 2'b01; // INT transfers
8'b??_10_00_?1: this_dpid <= 2'b01; // INT transfers
 
8'b??_01_10_?0, // IN/OUT endpoint only
8'b??_10_10_?0: this_dpid <= #1 2'b00; // BULK transfers
8'b??_10_10_?0: this_dpid <= 2'b00; // BULK transfers
8'b??_01_10_?1, // IN/OUT endpoint only
8'b??_10_10_?1: this_dpid <= #1 2'b01; // BULK transfers
8'b??_10_10_?1: this_dpid <= 2'b01; // BULK transfers
 
8'b??_00_??_??: // CTRL Endpoint
casex({setup_token,in_op, out_op, uc_dpd}) // synopsys full_case parallel_case
5'b1_??_??: this_dpid <= #1 2'b00; // SETUP operation
5'b0_10_0?: this_dpid <= #1 2'b00; // IN operation
5'b0_10_1?: this_dpid <= #1 2'b01; // IN operation
5'b0_01_?0: this_dpid <= #1 2'b00; // OUT operation
5'b0_01_?1: this_dpid <= #1 2'b01; // OUT operation
5'b1_??_??: this_dpid <= 2'b00; // SETUP operation
5'b0_10_0?: this_dpid <= 2'b00; // IN operation
5'b0_10_1?: this_dpid <= 2'b01; // IN operation
5'b0_01_?0: this_dpid <= 2'b00; // OUT operation
5'b0_01_?1: this_dpid <= 2'b01; // OUT operation
endcase
endcase
 
525,7 → 534,7
 
// Verify PID for incoming data packets
always @(posedge clk)
pid_seq_err <= #1 !( (this_dpid==2'b00 & pid_DATA0) |
pid_seq_err <= !( (this_dpid==2'b00 & pid_DATA0) |
(this_dpid==2'b01 & pid_DATA1) |
(this_dpid==2'b10 & pid_DATA2) |
(this_dpid==2'b11 & pid_MDATA) );
540,26 → 549,38
// buffer1 is used for IN (outgoing) data packets
 
// Keep track of last token for control endpoints
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
if(!rst) in_token <= #1 1'b0;
`else
always @(posedge clk)
`endif
if(!rst) in_token <= 1'b0;
else
if(pid_IN) in_token <= #1 1'b1;
if(pid_IN) in_token <= 1'b1;
else
if(pid_OUT | pid_SETUP) in_token <= #1 1'b0;
if(pid_OUT || pid_SETUP) in_token <= 1'b0;
 
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
if(!rst) out_token <= #1 1'b0;
`else
always @(posedge clk)
`endif
if(!rst) out_token <= 1'b0;
else
if(pid_OUT | pid_SETUP) out_token <= #1 1'b1;
if(pid_OUT || pid_SETUP) out_token <= 1'b1;
else
if(pid_IN) out_token <= #1 1'b0;
if(pid_IN) out_token <= 1'b0;
 
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
if(!rst) setup_token <= #1 1'b0;
`else
always @(posedge clk)
`endif
if(!rst) setup_token <= 1'b0;
else
if(pid_SETUP) setup_token <= #1 1'b1;
if(pid_SETUP) setup_token <= 1'b1;
else
if(pid_OUT | pid_IN) setup_token <= #1 1'b0;
if(pid_OUT || pid_IN) setup_token <= 1'b0;
 
// Indicates if we are performing an IN operation
assign in_op = IN_ep | (CTRL_ep & in_token);
572,7 → 593,7
 
// Select Address for IDMA
always @(posedge clk)
adr <= #1 buf_sel ? buf1_adr : buf0_adr;
adr <= buf_sel ? buf1_adr : buf0_adr;
 
// Size from Buffer
assign buf_size = buf_sel ? buf1_sz : buf0_sz;
589,67 → 610,67
// Indicates that there is not enough space in the buffer for one
// more max_pl_sz packet
always @(posedge clk)
buffer_full <= #1 new_size < {3'h0, max_pl_sz};
buffer_full <= new_size < {3'h0, max_pl_sz};
 
// Buffer Empty (only for IN endpoints)
// Indicates that there are zero bytes left in the buffer
always @(posedge clk)
buffer_empty <= #1 (new_size == 14'h0);
buffer_empty <= (new_size == 14'h0);
 
// Joint buffer full/empty flag This is the "USED" flag
always @(posedge clk)
buffer_done <= #1 in_op ? buffer_empty : buffer_full;
buffer_done <= in_op ? buffer_empty : buffer_full;
 
//No More buffer space at all (For high speed out - issue NYET)
// No More buffer space at all (For high speed out - issue NYET)
assign no_buf0_dma = dma_en &
((IN_ep & !dma_in_buf_sz1) | (OUT_ep & !dma_out_buf_avail));
 
always @(posedge clk)
buf0_st_max <= #1 (buf0_sz < {3'h0, max_pl_sz});
buf0_st_max <= (buf0_sz < {3'h0, max_pl_sz});
 
always @(posedge clk)
buf1_st_max <= #1 (buf1_sz < {3'h0, max_pl_sz});
buf1_st_max <= (buf1_sz < {3'h0, max_pl_sz});
 
always @(posedge clk)
no_bufs0 <= #1 buf0_na | no_buf0_dma |
no_bufs0 <= buf0_na | no_buf0_dma |
(buf_sel ? buf0_st_max : (buffer_full & !dma_en));
 
always @(posedge clk)
no_bufs1 <= #1 buf1_na | (buf_sel ? buffer_full : buf1_st_max);
no_bufs1 <= buf1_na | (buf_sel ? buffer_full : buf1_st_max);
 
assign no_bufs = no_bufs0 & no_bufs1;
 
// New Size (to be written to register file)
always @(posedge clk)
new_sizeb <= #1 (out_op & dma_en) ? max_pl_sz : (in_op ? size_next : sizu_c);
new_sizeb <= (out_op && dma_en) ? max_pl_sz : (in_op ? size_next : sizu_c);
 
always @(posedge clk)
new_size <= #1 buf_size - new_sizeb;
new_size <= buf_size - new_sizeb;
 
 
// New Buffer Address (to be written to register file)
always @(posedge clk)
adr_r <= #1 adr;
adr_r <= adr;
 
always @(posedge clk)
size_next_r <= #1 size_next;
size_next_r <= size_next;
 
assign new_adr = adr_r[SSRAM_HADR + 2:0] +
((out_op & dma_en) ? {{SSRAM_HADR + 2-10{1'b0}}, max_pl_sz[10:0]} :
((out_op && dma_en) ? {{SSRAM_HADR + 2-10{1'b0}}, max_pl_sz[10:0]} :
(in_op ? {{SSRAM_HADR + 2-13{1'b0}}, size_next_r[13:0] } :
{ {SSRAM_HADR + 2-10{1'b0}}, sizu_c[10:0]}));
 
// Buffer Overflow
always @(posedge clk)
buffer_overflow <= #1 ( {3'h0, sizu_c} > buf_size) & rx_data_valid;
buffer_overflow <= ( {3'h0, sizu_c} > buf_size) & rx_data_valid;
 
 
// OUT packet smaller than MAX_PL_SZ in DMA operation
always @(posedge clk)
out_to_small_r <= #1 uc_stat_set_d & out_op & dma_en & (sizu_c != max_pl_sz);
out_to_small_r <= uc_stat_set_d & out_op & dma_en & (sizu_c != max_pl_sz);
 
always @(posedge clk)
out_to_small <= #1 out_to_small_r;
out_to_small <= out_to_small_r;
 
///////////////////////////////////////////////////////////////////
//
658,10 → 679,10
//
 
always @(posedge clk)
to_small <= #1 !sml_ok & (sizu_c < max_pl_sz);
to_small <= !sml_ok & (sizu_c < max_pl_sz);
 
always @(posedge clk)
to_large <= #1 !lrg_ok & (sizu_c > max_pl_sz);
to_large <= !lrg_ok & (sizu_c > max_pl_sz);
 
///////////////////////////////////////////////////////////////////
//
671,36 → 692,36
assign next_bsel = dma_en ? 2'h0 : buffer_done ? uc_bsel + 2'h1 : uc_bsel; // FIX_ME
 
always @(posedge clk)
idin[31:17] <= #1 out_to_small_r ? {4'h0,sizu_c} : {buffer_done,new_size};
idin[31:17] <= out_to_small_r ? {4'h0,sizu_c} : {buffer_done,new_size};
 
always @(posedge clk)
idin[SSRAM_HADR + 2:4] <= #1 out_to_small_r ? buf0_adr[SSRAM_HADR + 2:4] :
idin[SSRAM_HADR + 2:4] <= out_to_small_r ? buf0_adr[SSRAM_HADR + 2:4] :
new_adr[SSRAM_HADR + 2:4];
 
always @(posedge clk)
if(buf_set_d) idin[3:0] <= #1 new_adr[3:0];
if(buf_set_d) idin[3:0] <= new_adr[3:0];
else
if(out_to_small_r) idin[3:0] <= #1 buf0_adr[3:0];
else idin[3:0] <= #1 {next_dpid, next_bsel};
if(out_to_small_r) idin[3:0] <= buf0_adr[3:0];
else idin[3:0] <= {next_dpid, next_bsel};
 
always @(posedge clk)
buf0_set <= #1 !buf_sel & buf_set_d;
buf0_set <= !buf_sel & buf_set_d;
 
always @(posedge clk)
buf1_set <= #1 buf_sel & buf_set_d;
buf1_set <= buf_sel & buf_set_d;
 
always @(posedge clk)
uc_bsel_set <= #1 uc_stat_set_d;
uc_bsel_set <= uc_stat_set_d;
 
always @(posedge clk)
uc_dpd_set <= #1 uc_stat_set_d;
uc_dpd_set <= uc_stat_set_d;
 
always @(posedge clk)
buf0_rl <= #1 buf0_rl_d;
buf0_rl <= buf0_rl_d;
 
// Abort signal
always @(posedge clk)
abort <= #1 buffer_overflow | (match & (state != IDLE) ) | (match_r & to_large);
abort <= buffer_overflow | (match & (state != IDLE) ) | (match_r & to_large);
 
///////////////////////////////////////////////////////////////////
//
714,14 → 735,14
// rx_ack_to_clr, clears the timer
 
always @(posedge clk)
rx_ack_to_clr <= #1 tx_valid | rx_ack_to_clr_d;
rx_ack_to_clr <= tx_valid | rx_ack_to_clr_d;
 
always @(posedge clk)
if(rx_ack_to_clr) rx_ack_to_cnt <= #1 8'h0;
else rx_ack_to_cnt <= #1 rx_ack_to_cnt + 8'h1;
if(rx_ack_to_clr) rx_ack_to_cnt <= 8'h0;
else rx_ack_to_cnt <= rx_ack_to_cnt + 8'h1;
 
always @(posedge clk)
rx_ack_to <= #1 (rx_ack_to_cnt == rx_ack_to_val);
rx_ack_to <= (rx_ack_to_cnt == rx_ack_to_val);
 
assign rx_ack_to_val = mode_hs ? `USBF_RX_ACK_TO_VAL_HS : `USBF_RX_ACK_TO_VAL_FS;
 
734,11 → 755,11
assign tx_data_to_clr = rx_active;
 
always @(posedge clk)
if(tx_data_to_clr) tx_data_to_cnt <= #1 8'h0;
else tx_data_to_cnt <= #1 tx_data_to_cnt + 8'h1;
if(tx_data_to_clr) tx_data_to_cnt <= 8'h0;
else tx_data_to_cnt <= tx_data_to_cnt + 8'h1;
 
always @(posedge clk)
tx_data_to <= #1 (tx_data_to_cnt == tx_data_to_val);
tx_data_to <= (tx_data_to_cnt == tx_data_to_val);
 
assign tx_data_to_val = mode_hs ? `USBF_TX_DATA_TO_VAL_HS : `USBF_TX_DATA_TO_VAL_FS;
 
752,31 → 773,30
assign int_buf0_set = buf_sel & buffer_done & int_set_en & !buf0_not_aloc;
 
always @(posedge clk)
pid_OUT_r <= #1 pid_OUT;
pid_OUT_r <= pid_OUT;
 
always @(posedge clk)
pid_IN_r <= #1 pid_IN;
pid_IN_r <= pid_IN;
 
always @(posedge clk)
pid_PING_r <= #1 pid_PING;
pid_PING_r <= pid_PING;
 
always @(posedge clk)
pid_SETUP_r <= #1 pid_SETUP;
pid_SETUP_r <= pid_SETUP;
 
always @(posedge clk)
int_upid_set <= #1 match_r & !pid_SOF & (
int_upid_set <= match_r & !pid_SOF & (
( OUT_ep & !(pid_OUT_r | pid_PING_r)) |
( IN_ep & !pid_IN_r) |
(CTRL_ep & !(pid_IN_r | pid_OUT_r | pid_PING_r | pid_SETUP_r))
);
 
 
assign int_to_set = ((state == IN2) & rx_ack_to) | ((state == OUT) & tx_data_to);
 
assign int_crc16_set = rx_data_done & crc16_err;
 
always @(posedge clk)
int_seqerr_set <= #1 int_seqerr_set_d;
int_seqerr_set <= int_seqerr_set_d;
 
///////////////////////////////////////////////////////////////////
//
783,11 → 803,15
// Main Protocol State Machine
//
 
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
if(!rst) state <= #1 IDLE;
`else
always @(posedge clk)
`endif
if(!rst) state <= IDLE;
else
if(match) state <= #1 IDLE;
else state <= #1 next_state;
if(match) state <= IDLE;
else state <= next_state;
 
always @(state or ep_stall or buf0_na or buf1_na or
pid_seq_err or idma_done or token_valid or pid_ACK or rx_data_done or
794,7 → 818,7
tx_data_to or crc16_err or ep_disabled or no_bufs or mode_hs
or dma_en or rx_ack_to or pid_PING or txfr_iso or to_small or to_large or
CTRL_ep or pid_IN or pid_OUT or IN_ep or OUT_ep or pid_SETUP or pid_SOF
or match_r or abort or buffer_done or no_buf0_dma)
or match_r or abort or buffer_done or no_buf0_dma or max_pl_sz)
begin
next_state = state;
token_pid_sel_d = ACK;
807,6 → 831,7
int_set_en = 1'b0;
rx_ack_to_clr_d = 1'b1;
int_seqerr_set_d = 1'b0;
send_zero_length = 1'b0;
 
case(state) // synopsys full_case parallel_case
IDLE:
816,7 → 841,7
$display("PE: Entered state IDLE (%t)", $time);
`endif
`ifdef USBF_DEBUG
if(rst & match_r & !ep_disabled & !pid_SOF)
if(rst && match_r && !ep_disabled && !pid_SOF)
begin
if(match_r === 1'bx) $display("ERROR: IDLE: match_r is unknown. (%t)", $time);
if(ep_disabled === 1'bx)$display("ERROR: IDLE: ep_disabled is unknown. (%t)", $time);
837,7 → 862,7
`endif
// synopsys translate_on
 
if(match_r & !ep_disabled & !pid_SOF)
if(match_r && !ep_disabled && !pid_SOF)
begin
if(ep_stall) // Halt Forced send STALL
begin
846,9 → 871,9
next_state = TOKEN;
end
else
if( (buf0_na & buf1_na) | no_buf0_dma |
(CTRL_ep & pid_IN & buf1_na) |
(CTRL_ep & pid_OUT & buf0_na)
if( (buf0_na && buf1_na) || no_buf0_dma ||
(CTRL_ep && pid_IN && buf1_na) ||
(CTRL_ep && pid_OUT && buf0_na)
)
begin // No buffers send NAK
token_pid_sel_d = NACK;
856,7 → 881,7
next_state = TOKEN;
end
else
if(pid_PING & mode_hs)
if(pid_PING && mode_hs)
begin
token_pid_sel_d = ACK;
send_token_d = 1'b1;
863,13 → 888,14
next_state = TOKEN;
end
else
if(IN_ep | (CTRL_ep & pid_IN))
if(IN_ep || (CTRL_ep && pid_IN))
begin
if(max_pl_sz == 11'h0) send_zero_length = 1'b1;
tx_dma_en = 1'b1;
next_state = IN;
end
else
if(OUT_ep | (CTRL_ep & (pid_OUT | pid_SETUP)))
if(OUT_ep || (CTRL_ep && (pid_OUT || pid_SETUP)))
begin
rx_dma_en = 1'b1;
next_state = OUT;
922,7 → 948,7
// Wait for ACK from HOST or Timeout
if(rx_ack_to) next_state = IDLE;
else
if(token_valid & pid_ACK)
if(token_valid && pid_ACK)
begin
next_state = UPDATE;
end
943,7 → 969,7
if(pid_seq_err === 1'bx)$display("ERROR: OUT: rx_data_done is unknown. (%t)", $time);
`endif
// synopsys translate_on
if(tx_data_to | crc16_err | abort )
if(tx_data_to || crc16_err || abort )
next_state = IDLE;
else
if(rx_data_done)
988,7 → 1014,7
// synopsys translate_on
if(abort) next_state = IDLE;
else
if(to_small | to_large)
if(to_small || to_large)
begin
token_pid_sel_d = NACK;
next_state = IDLE;
1002,7 → 1028,7
end
else
begin
if(mode_hs & no_bufs) token_pid_sel_d = NYET;
if(mode_hs && no_bufs) token_pid_sel_d = NYET;
else token_pid_sel_d = ACK;
send_token_d = 1'b1;
next_state = UPDATE;
1032,7 → 1058,7
// Interrupts
int_set_en = 1'b1;
// Buffer (used, size, adr) set or reload
if(buffer_done & dma_en)
if(buffer_done && dma_en)
begin
buf0_rl_d = 1'b1;
end
/trunk/rtl/verilog/usbf_ep_rf_dummy.v
13,8 → 13,9
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// Copyright (C) 2000-2003 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
39,10 → 40,10
 
// CVS Log
//
// $Id: usbf_ep_rf_dummy.v,v 1.1 2001-08-03 05:30:09 rudi Exp $
// $Id: usbf_ep_rf_dummy.v,v 1.2 2003-10-17 02:36:57 rudi Exp $
//
// $Date: 2001-08-03 05:30:09 $
// $Revision: 1.1 $
// $Date: 2003-10-17 02:36:57 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
49,6 → 50,11
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/08/03 05:30:09 rudi
//
//
// 1) Reorganized directory structure
//
// Revision 1.1 2001/03/31 12:45:13 rudi
//
// This is the endpoint register file for non existing endpoints. It will be used for
122,16 → 128,16
// Internal Access
//
 
assign dout = 0;
assign inta = 0;
assign intb = 0;
assign dma_req = 0;
assign ep_match = 0;
assign dout = 32'h0;
assign inta = 1'b0;
assign intb = 1'b0;
assign dma_req = 1'b0;
assign ep_match = 1'b0;
assign csr = 32'h0;
assign buf0 = 32'hffff_ffff;
assign buf1 = 32'hffff_ffff;
assign dma_in_buf_sz1 = 0;
assign dma_out_buf_avail = 0;
assign dma_in_buf_sz1 = 1'b0;
assign dma_out_buf_avail = 1'b0;
 
endmodule
 
/trunk/rtl/verilog/usbf_rf.v
12,8 → 12,9
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// Copyright (C) 2000-2003 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
38,10 → 39,10
 
// CVS Log
//
// $Id: usbf_rf.v,v 1.5 2001-11-04 12:22:45 rudi Exp $
// $Id: usbf_rf.v,v 1.6 2003-10-17 02:36:57 rudi Exp $
//
// $Date: 2001-11-04 12:22:45 $
// $Revision: 1.5 $
// $Date: 2003-10-17 02:36:57 $
// $Revision: 1.6 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 49,11
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.5 2001/11/04 12:22:45 rudi
//
// - Fixed previous fix (brocke something else ...)
// - Majore Synthesis cleanup
//
// Revision 1.4 2001/11/03 03:26:23 rudi
//
// - Fixed several interrupt and error condition reporting bugs
121,8 → 127,6
crc5_err, rx_err, rf_resume_req
);
 
parameter SSRAM_HADR = 14;
 
input clk, wclk, rst;
input [6:0] adr;
input re;
252,7 → 256,7
reg [6:0] funct_adr;
reg [8:0] intb_msk, inta_msk;
 
reg match_r1, match_r2;
reg match_r1;
reg [31:0] csr;
reg [31:0] buf0;
reg [31:0] buf1;
286,7 → 290,7
//
 
// Main CSR Alias
assign main_csr = {28'h0, line_stat, usb_attached, mode_hs, suspend};
assign main_csr = {27'h0, line_stat, usb_attached, mode_hs, suspend};
 
// Read Registers Logic
always @(adr or main_csr or funct_adr or inta_msk or intb_msk or int_srca
302,71 → 306,100
 
// Interrupt Source Read Register
always @(posedge wclk)
int_src_re <= #1 adr[6:0] == 7'h3 & re;
int_src_re <= adr[6:0] == 7'h3 & re;
 
// UTMI Vendor Control Stuff
always @(posedge wclk)
utmi_vend_stat_r <= #1 utmi_vend_stat;
utmi_vend_stat_r <= utmi_vend_stat;
 
reg utmi_vend_wr_r;
`ifdef USBF_ASYNC_RESET
always @(posedge wclk or negedge rst)
`else
always @(posedge wclk)
utmi_vend_wr <= #1 adr[6:0] == 7'h5 & we;
`endif
if(!rst) utmi_vend_wr_r <= 1'b0;
else
if(adr[6:0] == 7'h5 && we) utmi_vend_wr_r <= 1'b1;
else
if(utmi_vend_wr) utmi_vend_wr_r <= 1'b0;
 
always @(posedge clk) // Second Stage sync
utmi_vend_wr <= utmi_vend_wr_r;
 
 
reg [3:0] utmi_vend_ctrl_r;
always @(posedge wclk)
if(adr[6:0] == 7'h5 & we) utmi_vend_ctrl <= #1 din[3:0];
if(adr[6:0] == 7'h5 && we) utmi_vend_ctrl_r <= din[3:0];
 
always @(posedge clk) // Second Stage sync
utmi_vend_ctrl <= utmi_vend_ctrl_r;
 
// Resume Request
`ifdef USBF_ASYNC_RESET
always @(posedge wclk or negedge rst)
if(!rst) rf_resume_req_r <= #1 1'b0;
`else
always @(posedge wclk)
`endif
if(!rst) rf_resume_req_r <= 1'b0;
else
if(adr[6:0] == 7'h0 & we) rf_resume_req_r <= #1 din[5];
if(adr[6:0] == 7'h0 && we) rf_resume_req_r <= din[5];
else
if(rf_resume_req) rf_resume_req_r <= #1 1'b0;
if(rf_resume_req) rf_resume_req_r <= 1'b0;
 
always @(posedge clk)
rf_resume_req <= #1 rf_resume_req_r;
always @(posedge clk) // Second Stage sync
rf_resume_req <= rf_resume_req_r;
 
// Function Address Register
`ifdef USBF_ASYNC_RESET
always @(posedge wclk or negedge rst)
if(!rst) funct_adr <= #1 7'h0;
`else
always @(posedge wclk)
`endif
if(!rst) funct_adr <= 7'h0;
else
if(adr[6:0] == 7'h1 & we) funct_adr <= #1 din[6:0];
if(adr[6:0] == 7'h1 && we) funct_adr <= din[6:0];
 
// Interrup Mask Register
`ifdef USBF_ASYNC_RESET
always @(posedge wclk or negedge rst)
`else
always @(posedge wclk)
`endif
if(!rst)
begin
inta_msk <= #1 9'h0;
intb_msk <= #1 9'h0;
inta_msk <= 9'h0;
intb_msk <= 9'h0;
end
else
if(adr[6:0] == 7'h2 & we)
if(adr[6:0] == 7'h2 && we)
begin
intb_msk <= #1 din[24:16];
inta_msk <= #1 din[08:00];
intb_msk <= din[24:16];
inta_msk <= din[08:00];
end
 
always @(posedge wclk)
case(adr[6:2]) // synopsys full_case parallel_case
5'h00: dout <= #1 dtmp; // Addr: 0h
5'h01: dout <= #1 dtmp;
5'h02: dout <= #1 32'h0;
5'h03: dout <= #1 32'h0;
5'h04: dout <= #1 ep0_dout;
5'h05: dout <= #1 ep1_dout;
5'h06: dout <= #1 ep2_dout;
5'h07: dout <= #1 ep3_dout;
5'h08: dout <= #1 ep4_dout;
5'h09: dout <= #1 ep5_dout;
5'h10: dout <= #1 ep6_dout;
5'h11: dout <= #1 ep7_dout;
5'h12: dout <= #1 ep8_dout;
5'h13: dout <= #1 ep9_dout;
5'h14: dout <= #1 ep10_dout;
5'h15: dout <= #1 ep11_dout;
5'h16: dout <= #1 ep12_dout;
5'h17: dout <= #1 ep13_dout;
5'h18: dout <= #1 ep14_dout;
5'h19: dout <= #1 ep15_dout;
5'h00: dout <= dtmp; // Addr: 0h
5'h01: dout <= dtmp;
5'h02: dout <= 32'h0;
5'h03: dout <= 32'h0;
5'h04: dout <= ep0_dout;
5'h05: dout <= ep1_dout;
5'h06: dout <= ep2_dout;
5'h07: dout <= ep3_dout;
5'h08: dout <= ep4_dout;
5'h09: dout <= ep5_dout;
5'h0a: dout <= ep6_dout;
5'h0b: dout <= ep7_dout;
5'h0c: dout <= ep8_dout;
5'h0d: dout <= ep9_dout;
5'h0e: dout <= ep10_dout;
5'h0f: dout <= ep11_dout;
5'h10: dout <= ep12_dout;
5'h11: dout <= ep13_dout;
5'h12: dout <= ep14_dout;
5'h13: dout <= ep15_dout;
endcase
 
assign ep0_re = (adr[6:2] == 5'h04) & re;
375,16 → 408,16
assign ep3_re = (adr[6:2] == 5'h07) & re;
assign ep4_re = (adr[6:2] == 5'h08) & re;
assign ep5_re = (adr[6:2] == 5'h09) & re;
assign ep6_re = (adr[6:2] == 5'h10) & re;
assign ep7_re = (adr[6:2] == 5'h11) & re;
assign ep8_re = (adr[6:2] == 5'h12) & re;
assign ep9_re = (adr[6:2] == 5'h13) & re;
assign ep10_re = (adr[6:2] == 5'h14) & re;
assign ep11_re = (adr[6:2] == 5'h15) & re;
assign ep12_re = (adr[6:2] == 5'h16) & re;
assign ep13_re = (adr[6:2] == 5'h17) & re;
assign ep14_re = (adr[6:2] == 5'h18) & re;
assign ep15_re = (adr[6:2] == 5'h19) & re;
assign ep6_re = (adr[6:2] == 5'h0a) & re;
assign ep7_re = (adr[6:2] == 5'h0b) & re;
assign ep8_re = (adr[6:2] == 5'h0c) & re;
assign ep9_re = (adr[6:2] == 5'h0d) & re;
assign ep10_re = (adr[6:2] == 5'h0e) & re;
assign ep11_re = (adr[6:2] == 5'h0f) & re;
assign ep12_re = (adr[6:2] == 5'h10) & re;
assign ep13_re = (adr[6:2] == 5'h11) & re;
assign ep14_re = (adr[6:2] == 5'h12) & re;
assign ep15_re = (adr[6:2] == 5'h13) & re;
 
assign ep0_we = (adr[6:2] == 5'h04) & we;
assign ep1_we = (adr[6:2] == 5'h05) & we;
392,16 → 425,16
assign ep3_we = (adr[6:2] == 5'h07) & we;
assign ep4_we = (adr[6:2] == 5'h08) & we;
assign ep5_we = (adr[6:2] == 5'h09) & we;
assign ep6_we = (adr[6:2] == 5'h10) & we;
assign ep7_we = (adr[6:2] == 5'h11) & we;
assign ep8_we = (adr[6:2] == 5'h12) & we;
assign ep9_we = (adr[6:2] == 5'h13) & we;
assign ep10_we = (adr[6:2] == 5'h14) & we;
assign ep11_we = (adr[6:2] == 5'h15) & we;
assign ep12_we = (adr[6:2] == 5'h16) & we;
assign ep13_we = (adr[6:2] == 5'h17) & we;
assign ep14_we = (adr[6:2] == 5'h18) & we;
assign ep15_we = (adr[6:2] == 5'h19) & we;
assign ep6_we = (adr[6:2] == 5'h0a) & we;
assign ep7_we = (adr[6:2] == 5'h0b) & we;
assign ep8_we = (adr[6:2] == 5'h0c) & we;
assign ep9_we = (adr[6:2] == 5'h0d) & we;
assign ep10_we = (adr[6:2] == 5'h0e) & we;
assign ep11_we = (adr[6:2] == 5'h0f) & we;
assign ep12_we = (adr[6:2] == 5'h10) & we;
assign ep13_we = (adr[6:2] == 5'h11) & we;
assign ep14_we = (adr[6:2] == 5'h12) & we;
assign ep15_we = (adr[6:2] == 5'h13) & we;
 
///////////////////////////////////////////////////////////////////
//
411,178 → 444,175
assign match = match_r1;
 
always @(posedge clk)
match_r2 <= #1 match_r1;
 
always @(posedge clk)
match_r1 <= #1 ep0_match | ep1_match | ep2_match | ep3_match |
match_r1 <= ep0_match | ep1_match | ep2_match | ep3_match |
ep4_match | ep5_match | ep6_match | ep7_match |
ep8_match | ep9_match | ep10_match | ep11_match |
ep12_match | ep13_match | ep14_match | ep15_match;
 
always @(posedge clk)
if(ep0_match) csr <= #1 ep0_csr;
if(ep0_match) csr <= ep0_csr;
else
if(ep1_match) csr <= #1 ep1_csr;
if(ep1_match) csr <= ep1_csr;
else
if(ep2_match) csr <= #1 ep2_csr;
if(ep2_match) csr <= ep2_csr;
else
if(ep3_match) csr <= #1 ep3_csr;
if(ep3_match) csr <= ep3_csr;
else
if(ep4_match) csr <= #1 ep4_csr;
if(ep4_match) csr <= ep4_csr;
else
if(ep5_match) csr <= #1 ep5_csr;
if(ep5_match) csr <= ep5_csr;
else
if(ep6_match) csr <= #1 ep6_csr;
if(ep6_match) csr <= ep6_csr;
else
if(ep7_match) csr <= #1 ep7_csr;
if(ep7_match) csr <= ep7_csr;
else
if(ep8_match) csr <= #1 ep8_csr;
if(ep8_match) csr <= ep8_csr;
else
if(ep9_match) csr <= #1 ep9_csr;
if(ep9_match) csr <= ep9_csr;
else
if(ep10_match) csr <= #1 ep10_csr;
if(ep10_match) csr <= ep10_csr;
else
if(ep11_match) csr <= #1 ep11_csr;
if(ep11_match) csr <= ep11_csr;
else
if(ep12_match) csr <= #1 ep12_csr;
if(ep12_match) csr <= ep12_csr;
else
if(ep13_match) csr <= #1 ep13_csr;
if(ep13_match) csr <= ep13_csr;
else
if(ep14_match) csr <= #1 ep14_csr;
if(ep14_match) csr <= ep14_csr;
else
if(ep15_match) csr <= #1 ep15_csr;
if(ep15_match) csr <= ep15_csr;
 
always @(posedge clk)
if(ep0_match) buf0 <= #1 ep0_buf0;
if(ep0_match) buf0 <= ep0_buf0;
else
if(ep1_match) buf0 <= #1 ep1_buf0;
if(ep1_match) buf0 <= ep1_buf0;
else
if(ep2_match) buf0 <= #1 ep2_buf0;
if(ep2_match) buf0 <= ep2_buf0;
else
if(ep3_match) buf0 <= #1 ep3_buf0;
if(ep3_match) buf0 <= ep3_buf0;
else
if(ep4_match) buf0 <= #1 ep4_buf0;
if(ep4_match) buf0 <= ep4_buf0;
else
if(ep5_match) buf0 <= #1 ep5_buf0;
if(ep5_match) buf0 <= ep5_buf0;
else
if(ep6_match) buf0 <= #1 ep6_buf0;
if(ep6_match) buf0 <= ep6_buf0;
else
if(ep7_match) buf0 <= #1 ep7_buf0;
if(ep7_match) buf0 <= ep7_buf0;
else
if(ep8_match) buf0 <= #1 ep8_buf0;
if(ep8_match) buf0 <= ep8_buf0;
else
if(ep9_match) buf0 <= #1 ep9_buf0;
if(ep9_match) buf0 <= ep9_buf0;
else
if(ep10_match) buf0 <= #1 ep10_buf0;
if(ep10_match) buf0 <= ep10_buf0;
else
if(ep11_match) buf0 <= #1 ep11_buf0;
if(ep11_match) buf0 <= ep11_buf0;
else
if(ep12_match) buf0 <= #1 ep12_buf0;
if(ep12_match) buf0 <= ep12_buf0;
else
if(ep13_match) buf0 <= #1 ep13_buf0;
if(ep13_match) buf0 <= ep13_buf0;
else
if(ep14_match) buf0 <= #1 ep14_buf0;
if(ep14_match) buf0 <= ep14_buf0;
else
if(ep15_match) buf0 <= #1 ep15_buf0;
if(ep15_match) buf0 <= ep15_buf0;
 
always @(posedge clk)
if(ep0_match) buf1 <= #1 ep0_buf1;
if(ep0_match) buf1 <= ep0_buf1;
else
if(ep1_match) buf1 <= #1 ep1_buf1;
if(ep1_match) buf1 <= ep1_buf1;
else
if(ep2_match) buf1 <= #1 ep2_buf1;
if(ep2_match) buf1 <= ep2_buf1;
else
if(ep3_match) buf1 <= #1 ep3_buf1;
if(ep3_match) buf1 <= ep3_buf1;
else
if(ep4_match) buf1 <= #1 ep4_buf1;
if(ep4_match) buf1 <= ep4_buf1;
else
if(ep5_match) buf1 <= #1 ep5_buf1;
if(ep5_match) buf1 <= ep5_buf1;
else
if(ep6_match) buf1 <= #1 ep6_buf1;
if(ep6_match) buf1 <= ep6_buf1;
else
if(ep7_match) buf1 <= #1 ep7_buf1;
if(ep7_match) buf1 <= ep7_buf1;
else
if(ep8_match) buf1 <= #1 ep8_buf1;
if(ep8_match) buf1 <= ep8_buf1;
else
if(ep9_match) buf1 <= #1 ep9_buf1;
if(ep9_match) buf1 <= ep9_buf1;
else
if(ep10_match) buf1 <= #1 ep10_buf1;
if(ep10_match) buf1 <= ep10_buf1;
else
if(ep11_match) buf1 <= #1 ep11_buf1;
if(ep11_match) buf1 <= ep11_buf1;
else
if(ep12_match) buf1 <= #1 ep12_buf1;
if(ep12_match) buf1 <= ep12_buf1;
else
if(ep13_match) buf1 <= #1 ep13_buf1;
if(ep13_match) buf1 <= ep13_buf1;
else
if(ep14_match) buf1 <= #1 ep14_buf1;
if(ep14_match) buf1 <= ep14_buf1;
else
if(ep15_match) buf1 <= #1 ep15_buf1;
if(ep15_match) buf1 <= ep15_buf1;
 
always @(posedge clk)
if(ep0_match) dma_in_buf_sz1 <= #1 ep0_dma_in_buf_sz1;
if(ep0_match) dma_in_buf_sz1 <= ep0_dma_in_buf_sz1;
else
if(ep1_match) dma_in_buf_sz1 <= #1 ep1_dma_in_buf_sz1;
if(ep1_match) dma_in_buf_sz1 <= ep1_dma_in_buf_sz1;
else
if(ep2_match) dma_in_buf_sz1 <= #1 ep2_dma_in_buf_sz1;
if(ep2_match) dma_in_buf_sz1 <= ep2_dma_in_buf_sz1;
else
if(ep3_match) dma_in_buf_sz1 <= #1 ep3_dma_in_buf_sz1;
if(ep3_match) dma_in_buf_sz1 <= ep3_dma_in_buf_sz1;
else
if(ep4_match) dma_in_buf_sz1 <= #1 ep4_dma_in_buf_sz1;
if(ep4_match) dma_in_buf_sz1 <= ep4_dma_in_buf_sz1;
else
if(ep5_match) dma_in_buf_sz1 <= #1 ep5_dma_in_buf_sz1;
if(ep5_match) dma_in_buf_sz1 <= ep5_dma_in_buf_sz1;
else
if(ep6_match) dma_in_buf_sz1 <= #1 ep6_dma_in_buf_sz1;
if(ep6_match) dma_in_buf_sz1 <= ep6_dma_in_buf_sz1;
else
if(ep7_match) dma_in_buf_sz1 <= #1 ep7_dma_in_buf_sz1;
if(ep7_match) dma_in_buf_sz1 <= ep7_dma_in_buf_sz1;
else
if(ep8_match) dma_in_buf_sz1 <= #1 ep8_dma_in_buf_sz1;
if(ep8_match) dma_in_buf_sz1 <= ep8_dma_in_buf_sz1;
else
if(ep9_match) dma_in_buf_sz1 <= #1 ep9_dma_in_buf_sz1;
if(ep9_match) dma_in_buf_sz1 <= ep9_dma_in_buf_sz1;
else
if(ep10_match) dma_in_buf_sz1 <= #1 ep10_dma_in_buf_sz1;
if(ep10_match) dma_in_buf_sz1 <= ep10_dma_in_buf_sz1;
else
if(ep11_match) dma_in_buf_sz1 <= #1 ep11_dma_in_buf_sz1;
if(ep11_match) dma_in_buf_sz1 <= ep11_dma_in_buf_sz1;
else
if(ep12_match) dma_in_buf_sz1 <= #1 ep12_dma_in_buf_sz1;
if(ep12_match) dma_in_buf_sz1 <= ep12_dma_in_buf_sz1;
else
if(ep13_match) dma_in_buf_sz1 <= #1 ep13_dma_in_buf_sz1;
if(ep13_match) dma_in_buf_sz1 <= ep13_dma_in_buf_sz1;
else
if(ep14_match) dma_in_buf_sz1 <= #1 ep14_dma_in_buf_sz1;
if(ep14_match) dma_in_buf_sz1 <= ep14_dma_in_buf_sz1;
else
if(ep15_match) dma_in_buf_sz1 <= #1 ep15_dma_in_buf_sz1;
if(ep15_match) dma_in_buf_sz1 <= ep15_dma_in_buf_sz1;
 
always @(posedge clk)
if(ep0_match) dma_out_buf_avail <= #1 ep0_dma_out_buf_avail;
if(ep0_match) dma_out_buf_avail <= ep0_dma_out_buf_avail;
else
if(ep1_match) dma_out_buf_avail <= #1 ep1_dma_out_buf_avail;
if(ep1_match) dma_out_buf_avail <= ep1_dma_out_buf_avail;
else
if(ep2_match) dma_out_buf_avail <= #1 ep2_dma_out_buf_avail;
if(ep2_match) dma_out_buf_avail <= ep2_dma_out_buf_avail;
else
if(ep3_match) dma_out_buf_avail <= #1 ep3_dma_out_buf_avail;
if(ep3_match) dma_out_buf_avail <= ep3_dma_out_buf_avail;
else
if(ep4_match) dma_out_buf_avail <= #1 ep4_dma_out_buf_avail;
if(ep4_match) dma_out_buf_avail <= ep4_dma_out_buf_avail;
else
if(ep5_match) dma_out_buf_avail <= #1 ep5_dma_out_buf_avail;
if(ep5_match) dma_out_buf_avail <= ep5_dma_out_buf_avail;
else
if(ep6_match) dma_out_buf_avail <= #1 ep6_dma_out_buf_avail;
if(ep6_match) dma_out_buf_avail <= ep6_dma_out_buf_avail;
else
if(ep7_match) dma_out_buf_avail <= #1 ep7_dma_out_buf_avail;
if(ep7_match) dma_out_buf_avail <= ep7_dma_out_buf_avail;
else
if(ep8_match) dma_out_buf_avail <= #1 ep8_dma_out_buf_avail;
if(ep8_match) dma_out_buf_avail <= ep8_dma_out_buf_avail;
else
if(ep9_match) dma_out_buf_avail <= #1 ep9_dma_out_buf_avail;
if(ep9_match) dma_out_buf_avail <= ep9_dma_out_buf_avail;
else
if(ep10_match) dma_out_buf_avail <= #1 ep10_dma_out_buf_avail;
if(ep10_match) dma_out_buf_avail <= ep10_dma_out_buf_avail;
else
if(ep11_match) dma_out_buf_avail <= #1 ep11_dma_out_buf_avail;
if(ep11_match) dma_out_buf_avail <= ep11_dma_out_buf_avail;
else
if(ep12_match) dma_out_buf_avail <= #1 ep12_dma_out_buf_avail;
if(ep12_match) dma_out_buf_avail <= ep12_dma_out_buf_avail;
else
if(ep13_match) dma_out_buf_avail <= #1 ep13_dma_out_buf_avail;
if(ep13_match) dma_out_buf_avail <= ep13_dma_out_buf_avail;
else
if(ep14_match) dma_out_buf_avail <= #1 ep14_dma_out_buf_avail;
if(ep14_match) dma_out_buf_avail <= ep14_dma_out_buf_avail;
else
if(ep15_match) dma_out_buf_avail <= #1 ep15_dma_out_buf_avail;
if(ep15_match) dma_out_buf_avail <= ep15_dma_out_buf_avail;
 
 
///////////////////////////////////////////////////////////////////
603,19 → 633,19
suspend_r1 <= suspend_r;
 
always @(posedge wclk)
usb_reset_r <= #1 usb_reset;
usb_reset_r <= usb_reset;
 
always @(posedge wclk)
rx_err_r <= #1 rx_err;
rx_err_r <= rx_err;
 
always @(posedge wclk)
nse_err_r <= #1 nse_err;
nse_err_r <= nse_err;
 
always @(posedge wclk)
pid_cs_err_r <= #1 pid_cs_err;
pid_cs_err_r <= pid_cs_err;
 
always @(posedge wclk)
crc5_err_r <= #1 crc5_err;
crc5_err_r <= crc5_err;
 
assign attach = !attach_r1 & attach_r;
assign deattach = attach_r1 & !attach_r;
622,87 → 652,123
assign suspend_start = !suspend_r1 & suspend_r;
assign suspend_end = suspend_r1 & !suspend_r;
 
`ifdef USBF_ASYNC_RESET
always @(posedge wclk or negedge rst)
if(!rst) int_srcb[8] <= #1 1'b0;
`else
always @(posedge wclk)
`endif
if(!rst) int_srcb[8] <= 1'b0;
else
if(int_src_re) int_srcb[8] <= #1 1'b0;
if(int_src_re) int_srcb[8] <= 1'b0;
else
if(usb_reset_r) int_srcb[8] <= #1 1'b1;
if(usb_reset_r) int_srcb[8] <= 1'b1;
 
`ifdef USBF_ASYNC_RESET
always @(posedge wclk or negedge rst)
if(!rst) int_srcb[7] <= #1 1'b0;
`else
always @(posedge wclk)
`endif
if(!rst) int_srcb[7] <= 1'b0;
else
if(int_src_re) int_srcb[7] <= #1 1'b0;
if(int_src_re) int_srcb[7] <= 1'b0;
else
if(rx_err_r) int_srcb[7] <= #1 1'b1;
if(rx_err_r) int_srcb[7] <= 1'b1;
 
`ifdef USBF_ASYNC_RESET
always @(posedge wclk or negedge rst)
if(!rst) int_srcb[6] <= #1 1'b0;
`else
always @(posedge wclk)
`endif
if(!rst) int_srcb[6] <= 1'b0;
else
if(int_src_re) int_srcb[6] <= #1 1'b0;
if(int_src_re) int_srcb[6] <= 1'b0;
else
if(deattach) int_srcb[6] <= #1 1'b1;
if(deattach) int_srcb[6] <= 1'b1;
 
`ifdef USBF_ASYNC_RESET
always @(posedge wclk or negedge rst)
if(!rst) int_srcb[5] <= #1 1'b0;
`else
always @(posedge wclk)
`endif
if(!rst) int_srcb[5] <= 1'b0;
else
if(int_src_re) int_srcb[5] <= #1 1'b0;
if(int_src_re) int_srcb[5] <= 1'b0;
else
if(attach) int_srcb[5] <= #1 1'b1;
if(attach) int_srcb[5] <= 1'b1;
 
`ifdef USBF_ASYNC_RESET
always @(posedge wclk or negedge rst)
if(!rst) int_srcb[4] <= #1 1'b0;
`else
always @(posedge wclk)
`endif
if(!rst) int_srcb[4] <= 1'b0;
else
if(int_src_re) int_srcb[4] <= #1 1'b0;
if(int_src_re) int_srcb[4] <= 1'b0;
else
if(suspend_end) int_srcb[4] <= #1 1'b1;
if(suspend_end) int_srcb[4] <= 1'b1;
 
`ifdef USBF_ASYNC_RESET
always @(posedge wclk or negedge rst)
if(!rst) int_srcb[3] <= #1 1'b0;
`else
always @(posedge wclk)
`endif
if(!rst) int_srcb[3] <= 1'b0;
else
if(int_src_re) int_srcb[3] <= #1 1'b0;
if(int_src_re) int_srcb[3] <= 1'b0;
else
if(suspend_start) int_srcb[3] <= #1 1'b1;
if(suspend_start) int_srcb[3] <= 1'b1;
 
`ifdef USBF_ASYNC_RESET
always @(posedge wclk or negedge rst)
if(!rst) int_srcb[2] <= #1 1'b0;
`else
always @(posedge wclk)
`endif
if(!rst) int_srcb[2] <= 1'b0;
else
if(int_src_re) int_srcb[2] <= #1 1'b0;
if(int_src_re) int_srcb[2] <= 1'b0;
else
if(nse_err_r) int_srcb[2] <= #1 1'b1;
if(nse_err_r) int_srcb[2] <= 1'b1;
 
`ifdef USBF_ASYNC_RESET
always @(posedge wclk or negedge rst)
if(!rst) int_srcb[1] <= #1 1'b0;
`else
always @(posedge wclk)
`endif
if(!rst) int_srcb[1] <= 1'b0;
else
if(int_src_re) int_srcb[1] <= #1 1'b0;
if(int_src_re) int_srcb[1] <= 1'b0;
else
if(pid_cs_err_r) int_srcb[1] <= #1 1'b1;
if(pid_cs_err_r) int_srcb[1] <= 1'b1;
 
`ifdef USBF_ASYNC_RESET
always @(posedge wclk or negedge rst)
if(!rst) int_srcb[0] <= #1 1'b0;
`else
always @(posedge wclk)
`endif
if(!rst) int_srcb[0] <= 1'b0;
else
if(int_src_re) int_srcb[0] <= #1 1'b0;
if(int_src_re) int_srcb[0] <= 1'b0;
else
if(crc5_err_r) int_srcb[0] <= #1 1'b1;
if(crc5_err_r) int_srcb[0] <= 1'b1;
 
always @(posedge wclk)
begin
int_srca[15] <= #1 ep15_inta | ep15_intb;
int_srca[14] <= #1 ep14_inta | ep14_intb;
int_srca[13] <= #1 ep13_inta | ep13_intb;
int_srca[12] <= #1 ep12_inta | ep12_intb;
int_srca[11] <= #1 ep11_inta | ep11_intb;
int_srca[10] <= #1 ep10_inta | ep10_intb;
int_srca[09] <= #1 ep9_inta | ep9_intb;
int_srca[08] <= #1 ep8_inta | ep8_intb;
int_srca[07] <= #1 ep7_inta | ep7_intb;
int_srca[06] <= #1 ep6_inta | ep6_intb;
int_srca[05] <= #1 ep5_inta | ep5_intb;
int_srca[04] <= #1 ep4_inta | ep4_intb;
int_srca[03] <= #1 ep3_inta | ep3_intb;
int_srca[02] <= #1 ep2_inta | ep2_intb;
int_srca[01] <= #1 ep1_inta | ep1_intb;
int_srca[00] <= #1 ep0_inta | ep0_intb;
int_srca[15] <= ep15_inta | ep15_intb;
int_srca[14] <= ep14_inta | ep14_intb;
int_srca[13] <= ep13_inta | ep13_intb;
int_srca[12] <= ep12_inta | ep12_intb;
int_srca[11] <= ep11_inta | ep11_intb;
int_srca[10] <= ep10_inta | ep10_intb;
int_srca[09] <= ep9_inta | ep9_intb;
int_srca[08] <= ep8_inta | ep8_intb;
int_srca[07] <= ep7_inta | ep7_intb;
int_srca[06] <= ep6_inta | ep6_intb;
int_srca[05] <= ep5_inta | ep5_intb;
int_srca[04] <= ep4_inta | ep4_intb;
int_srca[03] <= ep3_inta | ep3_intb;
int_srca[02] <= ep2_inta | ep2_intb;
int_srca[01] <= ep1_inta | ep1_intb;
int_srca[00] <= ep0_inta | ep0_intb;
end
 
assign inta_ep =ep0_inta | ep1_inta | ep2_inta | ep3_inta |
719,10 → 785,10
assign intb_rf = |(int_srcb & intb_msk);
 
always @(posedge wclk)
inta <= #1 inta_ep | inta_rf;
inta <= inta_ep | inta_rf;
 
always @(posedge wclk)
intb <= #1 intb_ep | intb_rf;
intb <= intb_ep | intb_rf;
 
///////////////////////////////////////////////////////////////////
//
765,7 → 831,8
);
 
`ifdef USBF_HAVE_EP1
usbf_ep_rf u1( .clk( clk ),
usbf_ep_rf u1(
.clk( clk ),
.wclk( wclk ),
.rst( rst ),
.adr( adr[1:0] ),
/trunk/rtl/verilog/usbf_wb.v
13,8 → 13,9
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// Copyright (C) 2000-2003 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
39,10 → 40,10
 
// CVS Log
//
// $Id: usbf_wb.v,v 1.3 2001-09-24 01:15:28 rudi Exp $
// $Id: usbf_wb.v,v 1.4 2003-10-17 02:36:57 rudi Exp $
//
// $Date: 2001-09-24 01:15:28 $
// $Revision: 1.3 $
// $Date: 2003-10-17 02:36:57 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
49,6 → 50,10
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/09/24 01:15:28 rudi
//
// Changed reset to be active high async.
//
// Revision 1.2 2001/08/10 08:48:33 rudi
//
// - Changed IO names to be more clear.
114,7 → 119,6
input [31:0] rf_din;
output [31:0] rf_dout;
 
 
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
131,10 → 135,10
reg [5:0] /* synopsys enum state */ state, next_state;
// synopsys state_vector state
 
reg wb_req_s1, wb_req_s2;
reg wb_req_s1;
reg wb_ack_d, wb_ack_s1, wb_ack_s1a, wb_ack_s2;
reg ma_we;
reg rf_re, rf_we;
reg rf_re, rf_we_d;
reg ma_req;
reg wb_ack_o;
reg [31:0] wb_data_o;
149,69 → 153,72
assign rf_dout = wb_data_i;
 
always @(posedge wb_clk)
if( `USBF_RF_SEL ) wb_data_o <= #1 rf_din;
else wb_data_o <= #1 ma_din;
if( `USBF_RF_SEL ) wb_data_o <= rf_din;
else wb_data_o <= ma_din;
 
// Sync WISHBONE Request
always @(posedge phy_clk)
wb_req_s1 <= #1 wb_stb_i & wb_cyc_i;
wb_req_s1 <= wb_stb_i & wb_cyc_i;
 
always @(posedge phy_clk)
wb_req_s2 <= #1 wb_req_s1;
 
// Sync WISHBONE Ack
always @(posedge wb_clk)
wb_ack_s1 <= #1 wb_ack_d;
wb_ack_s1 <= wb_ack_d;
 
always @(posedge wb_clk)
wb_ack_o <= #1 wb_ack_s1 & !wb_ack_s2 & !wb_ack_o;
wb_ack_o <= wb_ack_s1 & !wb_ack_s2 & !wb_ack_o;
 
always @(posedge wb_clk)
wb_ack_s1a <= #1 wb_ack_s1;
wb_ack_s1a <= wb_ack_s1;
 
always @(posedge wb_clk)
wb_ack_s2 <= #1 wb_ack_s1a;
wb_ack_s2 <= wb_ack_s1a;
 
assign rf_we = rf_we_d;
 
///////////////////////////////////////////////////////////////////
//
// Interface State Machine
//
 
`ifdef USBF_ASYNC_RESET
always @(posedge phy_clk or negedge rst)
if(!rst) state <= #1 IDLE;
else state <= #1 next_state;
`else
always @(posedge phy_clk)
`endif
if(!rst) state <= IDLE;
else state <= next_state;
 
always @(state or wb_req_s1 or wb_addr_i or ma_ack or wb_we_i)
begin
next_state = state;
ma_req = 0;
ma_we = 0;
wb_ack_d = 0;
rf_re = 0;
rf_we = 0;
ma_req = 1'b0;
ma_we = 1'b0;
wb_ack_d = 1'b0;
rf_re = 1'b0;
rf_we_d = 1'b0;
 
case(state) // synopsys full_case parallel_case
IDLE:
begin
if(wb_req_s1 & `USBF_MEM_SEL & wb_we_i)
if(wb_req_s1 && `USBF_MEM_SEL && wb_we_i)
begin
ma_req = 1;
ma_we = 1;
ma_req = 1'b1;
ma_we = 1'b1;
next_state = MA_WR;
end
if(wb_req_s1 & `USBF_MEM_SEL & !wb_we_i)
if(wb_req_s1 && `USBF_MEM_SEL && !wb_we_i)
begin
ma_req = 1;
ma_req = 1'b1;
next_state = MA_RD;
end
if(wb_req_s1 & `USBF_RF_SEL & wb_we_i)
if(wb_req_s1 && `USBF_RF_SEL && wb_we_i)
begin
rf_we = 1;
rf_we_d = 1'b1;
next_state = W0;
end
if(wb_req_s1 & `USBF_RF_SEL & !wb_we_i)
if(wb_req_s1 && `USBF_RF_SEL && !wb_we_i)
begin
rf_re = 1;
rf_re = 1'b1;
next_state = W0;
end
end
220,12 → 227,12
begin
if(!ma_ack)
begin
ma_req = 1;
ma_we = 1;
ma_req = 1'b1;
ma_we = 1'b1;
end
else
begin
wb_ack_d = 1;
wb_ack_d = 1'b1;
next_state = W1;
end
end
234,11 → 241,11
begin
if(!ma_ack)
begin
ma_req = 1;
ma_req = 1'b1;
end
else
begin
wb_ack_d = 1;
wb_ack_d = 1'b1;
next_state = W1;
end
end
245,7 → 252,7
 
W0:
begin
wb_ack_d = 1;
wb_ack_d = 1'b1;
next_state = W1;
end
 
/trunk/rtl/verilog/usbf_idma.v
11,8 → 11,9
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// Copyright (C) 2000-2003 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
37,10 → 38,10
 
// CVS Log
//
// $Id: usbf_idma.v,v 1.7 2001-11-04 12:22:45 rudi Exp $
// $Id: usbf_idma.v,v 1.8 2003-10-17 02:36:57 rudi Exp $
//
// $Date: 2001-11-04 12:22:45 $
// $Revision: 1.7 $
// $Date: 2003-10-17 02:36:57 $
// $Revision: 1.8 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 48,11
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.7 2001/11/04 12:22:45 rudi
//
// - Fixed previous fix (brocke something else ...)
// - Majore Synthesis cleanup
//
// Revision 1.6 2001/11/03 03:26:22 rudi
//
// - Fixed several interrupt and error condition reporting bugs
104,6 → 110,7
rx_dma_en, tx_dma_en,
abort, idma_done,
buf_size, dma_en,
send_zero_length,
 
// Register File Manager Interface
adr, size, sizu_c,
130,6 → 137,7
output idma_done; // DMA is done
input [13:0] buf_size; // Actual buffer size
input dma_en; // External DMA enabled
input send_zero_length;
 
// Register File Manager Interface
input [SSRAM_HADR + 2:0] adr; // Byte Address
191,13 → 199,13
 
reg [7:0] tx_data_st; // Data output to packet assembler
reg [31:0] rd_buf0, rd_buf1; // Mem Rd. buffers for TX
reg rd_buf_full; // Indicates buffers are full
reg rd_first; // Indicates initial fill of buffers
 
reg idma_done; // DMA transfer is done
 
reg mack_r;
reg send_data; // Enable UTMI Transmitter
wire send_data; // Enable UTMI Transmitter
reg send_data_r;
 
reg word_done_r;
reg wr_last;
214,6 → 222,8
reg rx_data_valid_r;
reg [7:0] rx_data_st_r;
 
reg send_zero_length_r;
 
///////////////////////////////////////////////////////////////////
//
// Memory Arb interface
229,10 → 239,10
assign madr = adr_cw;
 
always @(posedge clk)
mwe <= #1 mwe_d;
mwe <= mwe_d;
 
always @(posedge clk)
mack_r <= #1 mreq & mack;
mack_r <= mreq & mack;
 
///////////////////////////////////////////////////////////////////
//
240,34 → 250,37
//
 
always @(posedge clk)
rx_data_valid_r <= #1 rx_data_valid;
rx_data_valid_r <= rx_data_valid;
 
always @(posedge clk)
rx_data_st_r <= #1 rx_data_st;
rx_data_st_r <= rx_data_st;
 
always @(posedge clk)
rx_data_done_r <= #1 rx_data_done;
rx_data_done_r <= rx_data_done;
 
always @(posedge clk)
rx_data_done_r2 <= #1 rx_data_done_r;
rx_data_done_r2 <= rx_data_done_r;
 
// Generate one cycle pulses for tx and rx dma enable
always @(posedge clk)
tx_dma_en_r <= #1 tx_dma_en;
tx_dma_en_r <= tx_dma_en;
 
always @(posedge clk)
rx_dma_en_r <= #1 rx_dma_en;
rx_dma_en_r <= rx_dma_en;
 
always @(posedge clk)
send_zero_length_r <= send_zero_length;
 
// address counter
always @(posedge clk)
if(rx_dma_en_r | tx_dma_en_r) adr_cw <= #1 adr[SSRAM_HADR + 2:2];
else adr_cw <= #1 adrw_next1;
if(rx_dma_en_r || tx_dma_en_r) adr_cw <= adr[SSRAM_HADR + 2:2];
else adr_cw <= adrw_next1;
 
always @(posedge clk)
last_buf_adr <= #1 adr + { {SSRAM_HADR+2-13{1'b0}}, buf_size };
last_buf_adr <= adr + { {SSRAM_HADR+2-13{1'b0}}, buf_size };
 
always @(dma_en or adrw_next or last_buf_adr)
if(adrw_next == last_buf_adr & dma_en) adrw_next1 = {SSRAM_HADR+1{1'b0}};
if(adrw_next == last_buf_adr && dma_en) adrw_next1 = {SSRAM_HADR+1{1'b0}};
else adrw_next1 = adrw_next;
 
always @(adr_incw or adr_cw)
274,11 → 287,15
if(adr_incw) adrw_next = adr_cw + {{SSRAM_HADR{1'b0}}, 1'b1};
else adrw_next = adr_cw;
 
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
if(!rst) adr_cb <= #1 3'h0;
`else
always @(posedge clk)
`endif
if(!rst) adr_cb <= 3'h0;
else
if(rx_dma_en_r | tx_dma_en_r) adr_cb <= #1 adr[2:0];
else adr_cb <= #1 adrb_next;
if(rx_dma_en_r || tx_dma_en_r) adr_cb <= adr[2:0];
else adr_cb <= adrb_next;
 
always @(adr_incb or adr_cb)
if(adr_incb) adrb_next = adr_cb + 3'h1;
288,33 → 305,42
assign adr_incw = !dtmp_sel_r & mack_r;
 
// Size Counter (counting backward from input size)
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
if(!rst) sizd_c <= #1 14'h3fff;
`else
always @(posedge clk)
`endif
if(!rst) sizd_c <= 14'h3fff;
else
if(tx_dma_en | tx_dma_en_r) sizd_c <= #1 size;
if(tx_dma_en || tx_dma_en_r) sizd_c <= size;
else
if(siz_dec) sizd_c <= #1 sizd_c - 14'h1;
if(siz_dec) sizd_c <= sizd_c - 14'h1;
 
assign siz_dec = (rd_first & mack_r) | (rd_next & (sizd_c != 14'h0) );
assign siz_dec = (rd_first & mack_r) | (rd_next & (sizd_c != 14'h0));
 
assign sizd_is_zero_d = sizd_c == 14'h0;
 
always @(posedge clk)
sizd_is_zero <= #1 sizd_is_zero_d;
sizd_is_zero <= sizd_is_zero_d;
 
// Size Counter (counting up from zero)
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
if(!rst) sizu_c <= #1 11'h0;
`else
always @(posedge clk)
`endif
if(!rst) sizu_c <= 11'h0;
else
if(rx_dma_en_r) sizu_c <= #1 11'h0;
// Do I need to add "abort" in the next line ???
if(rx_dma_en_r) sizu_c <= 11'h0;
else
if(siz_inc) sizu_c <= #1 sizu_c + 11'h1;
if(siz_inc) sizu_c <= sizu_c + 11'h1;
 
assign siz_inc = rx_data_valid_r;
 
// DMA Done Indicator
always @(posedge clk)
idma_done <= #1 (rx_data_done_r | sizd_is_zero_d); // & !tx_dma_en;
idma_done <= (rx_data_done_r | sizd_is_zero_d); // & !tx_dma_en;
 
///////////////////////////////////////////////////////////////////
//
322,38 → 348,38
//
 
always @(posedge clk)
dtmp_sel_r <= #1 dtmp_sel;
dtmp_sel_r <= dtmp_sel;
 
// Memory data input
always @(posedge clk)
if(dtmp_sel_r) dtmp_r <= #1 mdin;
if(dtmp_sel_r) dtmp_r <= mdin;
else
if(rx_data_valid_r)
begin
if(adr_cb[1:0] == 2'h0) dtmp_r[07:00] <= #1 rx_data_st_r;
if(adr_cb[1:0] == 2'h1) dtmp_r[15:08] <= #1 rx_data_st_r;
if(adr_cb[1:0] == 2'h2) dtmp_r[23:16] <= #1 rx_data_st_r;
if(adr_cb[1:0] == 2'h3) dtmp_r[31:24] <= #1 rx_data_st_r;
if(adr_cb[1:0] == 2'h0) dtmp_r[07:00] <= rx_data_st_r;
if(adr_cb[1:0] == 2'h1) dtmp_r[15:08] <= rx_data_st_r;
if(adr_cb[1:0] == 2'h2) dtmp_r[23:16] <= rx_data_st_r;
if(adr_cb[1:0] == 2'h3) dtmp_r[31:24] <= rx_data_st_r;
end
 
always @(posedge clk)
word_done <= #1 ((adr_cb[1:0] == 2'h3) & rx_data_valid_r) | wr_last;
word_done <= ((adr_cb[1:0] == 2'h3) & rx_data_valid_r) | wr_last;
 
always @(posedge clk)
word_done_r <= #1 word_done & !word_done_r;
word_done_r <= word_done & !word_done_r;
 
// Store output data and address when we got a word
always @(posedge clk)
if(word_done) dout_r <= #1 dtmp_r;
if(word_done) dout_r <= dtmp_r;
 
always @(posedge clk)
wr_last <= #1 (adr_cb[1:0] != 2'h0) & !rx_data_valid_r & wr_last_en;
wr_last <= (adr_cb[1:0] != 2'h0) & !rx_data_valid_r & wr_last_en;
 
always @(posedge clk)
wr_done_r <= #1 rx_data_done_r;
wr_done_r <= rx_data_done_r;
 
always @(posedge clk)
wr_done <= #1 wr_done_r;
wr_done <= wr_done_r;
 
///////////////////////////////////////////////////////////////////
//
362,10 → 388,10
 
// Fill TX Buffers
always @(posedge clk)
if(fill_buf0) rd_buf0 <= #1 mdin;
if(fill_buf0) rd_buf0 <= mdin;
 
always @(posedge clk)
if(fill_buf1) rd_buf1 <= #1 mdin;
if(fill_buf1) rd_buf1 <= mdin;
 
always @(adrb_next or rd_buf0 or rd_buf1)
case(adrb_next[2:0]) // synopsys full_case parallel_case
384,14 → 410,19
 
assign adrb_is_3 = adr_cb[1:0] == 2'h3;
 
 
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
if(!rst) send_data <= #1 1'b0;
`else
always @(posedge clk)
`endif
if(!rst) send_data_r <= 1'b0;
else
if(rd_first) send_data <= #1 1'b1;
if(rd_first) send_data_r <= 1'b1;
else
if(((sizd_c==14'h1) & rd_next) | sizd_is_zero_d) send_data <= #1 1'b0;
if(((sizd_c==14'h1) && rd_next) || sizd_is_zero_d) send_data_r <= 1'b0;
 
assign send_data = send_data_r | send_zero_length_r;
 
///////////////////////////////////////////////////////////////////
//
// IDMA Load/Store State Machine
400,13 → 431,17
// store incoming data to memory until rx_data done
// First pre-fetch data from memory, so that bytes can be stuffed properly
 
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
if(!rst) state <= #1 IDLE;
else state <= #1 next_state;
`else
always @(posedge clk)
`endif
if(!rst) state <= IDLE;
else state <= next_state;
 
always @(state or mack_r or abort or rx_dma_en_r or tx_dma_en_r or
sizd_is_zero or wr_last or wr_done or rx_data_done_r2 or
rd_next or adrb_is_3)
rd_next or adrb_is_3 or send_zero_length_r)
begin
next_state = state; // Default do not change state
mreq_d = 1'b0;
433,11 → 468,11
`endif
// synopsys translate_on
 
if(rx_dma_en_r & !abort)
if(rx_dma_en_r && !abort)
begin
next_state = WAIT_MRD;
end
if(tx_dma_en_r & !abort)
if(tx_dma_en_r && !abort && !send_zero_length_r)
begin
next_state = MEM_RD1;
end
580,9 → 615,9
`endif
// synopsys translate_on
 
if(sizd_is_zero | abort) next_state = IDLE;
if(sizd_is_zero || abort) next_state = IDLE;
else
if(adrb_is_3 & rd_next) next_state = MEM_RD2;
if(adrb_is_3 && rd_next) next_state = MEM_RD2;
end
endcase
 
/trunk/rtl/verilog/usbf_pl.v
13,8 → 13,9
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// Copyright (C) 2000-2003 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
39,10 → 40,10
 
// CVS Log
//
// $Id: usbf_pl.v,v 1.4 2001-11-04 12:22:45 rudi Exp $
// $Id: usbf_pl.v,v 1.5 2003-10-17 02:36:57 rudi Exp $
//
// $Date: 2001-11-04 12:22:45 $
// $Revision: 1.4 $
// $Date: 2003-10-17 02:36:57 $
// $Revision: 1.5 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
49,6 → 50,11
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.4 2001/11/04 12:22:45 rudi
//
// - Fixed previous fix (brocke something else ...)
// - Majore Synthesis cleanup
//
// Revision 1.3 2001/09/24 01:15:28 rudi
//
// Changed reset to be active high async.
250,51 → 256,63
// All bad pids
assign pid_bad = pid_bad1 | pid_bad2;
 
assign match_o = !pid_bad & match & token_valid & !crc5_err;
assign match_o = !pid_bad & fsel & match & token_valid & !crc5_err;
 
// Frame Number (from SOF token)
assign frame_no_we = token_valid & !crc5_err & pid_SOF;
 
always @(posedge clk)
frame_no_we_r <= #1 frame_no_we;
frame_no_we_r <= frame_no_we;
 
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
if(!rst) frame_no_r <= #1 11'h0;
`else
always @(posedge clk)
`endif
if(!rst) frame_no_r <= 11'h0;
else
if(frame_no_we_r) frame_no_r <= #1 frame_no;
if(frame_no_we_r) frame_no_r <= frame_no;
 
// Micro Frame Counter
always @(posedge clk)
frame_no_same <= #1 frame_no_we & (frame_no_r == frame_no);
frame_no_same <= frame_no_we & (frame_no_r == frame_no);
 
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
if(!rst) mfm_cnt <= #1 4'h0;
`else
always @(posedge clk)
`endif
if(!rst) mfm_cnt <= 4'h0;
else
if(frame_no_we_r & !frame_no_same)
mfm_cnt <= #1 4'h0;
if(frame_no_we_r && !frame_no_same)
mfm_cnt <= 4'h0;
else
if(frame_no_same) mfm_cnt <= #1 mfm_cnt + 4'h1;
if(frame_no_same) mfm_cnt <= mfm_cnt + 4'h1;
 
//SOF delay counter
always @(posedge clk)
clr_sof_time <= #1 frame_no_we;
clr_sof_time <= frame_no_we;
 
always @(posedge clk)
if(clr_sof_time) sof_time <= #1 12'h0;
if(clr_sof_time) sof_time <= 12'h0;
else
if(hms_clk) sof_time <= #1 sof_time + 12'h1;
if(hms_clk) sof_time <= sof_time + 12'h1;
 
assign frm_nat = {mfm_cnt, 1'b0, frame_no_r, 4'h0, sof_time};
 
// 0.5 Micro Seconds Clock Generator
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
if(!rst) hms_cnt <= #1 5'h0;
`else
always @(posedge clk)
`endif
if(!rst) hms_cnt <= 5'h0;
else
if(hms_clk | frame_no_we_r) hms_cnt <= #1 5'h0;
else hms_cnt <= #1 hms_cnt + 5'h1;
if(hms_clk || frame_no_we_r) hms_cnt <= 5'h0;
else hms_cnt <= hms_cnt + 5'h1;
 
always @(posedge clk)
hms_clk <= #1 (hms_cnt == `USBF_HMS_DEL);
hms_clk <= (hms_cnt == `USBF_HMS_DEL);
 
///////////////////////////////////////////////////////////////////
 
307,82 → 325,84
//
 
//Packet Decoder
usbf_pd u0( .clk( clk ),
.rst( rst ),
.rx_data( rx_data ),
.rx_valid( rx_valid ),
.rx_active( rx_active ),
.rx_err( rx_err ),
.pid_OUT( pid_OUT ),
.pid_IN( pid_IN ),
.pid_SOF( pid_SOF ),
.pid_SETUP( pid_SETUP ),
.pid_DATA0( pid_DATA0 ),
.pid_DATA1( pid_DATA1 ),
.pid_DATA2( pid_DATA2 ),
.pid_MDATA( pid_MDATA ),
.pid_ACK( pid_ACK ),
.pid_NACK( pid_NACK ),
.pid_STALL( pid_STALL ),
.pid_NYET( pid_NYET ),
.pid_PRE( pid_PRE ),
.pid_ERR( pid_ERR ),
.pid_SPLIT( pid_SPLIT ),
.pid_PING( pid_PING ),
.pid_cks_err( pid_cs_err ),
.token_fadr( token_fadr ),
.token_endp( ep_sel ),
.token_valid( token_valid ),
.crc5_err( crc5_err ),
.frame_no( frame_no ),
.rx_data_st( rx_data_st ),
.rx_data_valid( rx_data_valid ),
.rx_data_done( rx_data_done ),
.crc16_err( crc16_err ),
.seq_err( rx_seq_err )
usbf_pd u0( .clk( clk ),
.rst( rst ),
.rx_data( rx_data ),
.rx_valid( rx_valid ),
.rx_active( rx_active ),
.rx_err( rx_err ),
.pid_OUT( pid_OUT ),
.pid_IN( pid_IN ),
.pid_SOF( pid_SOF ),
.pid_SETUP( pid_SETUP ),
.pid_DATA0( pid_DATA0 ),
.pid_DATA1( pid_DATA1 ),
.pid_DATA2( pid_DATA2 ),
.pid_MDATA( pid_MDATA ),
.pid_ACK( pid_ACK ),
.pid_NACK( pid_NACK ),
.pid_STALL( pid_STALL ),
.pid_NYET( pid_NYET ),
.pid_PRE( pid_PRE ),
.pid_ERR( pid_ERR ),
.pid_SPLIT( pid_SPLIT ),
.pid_PING( pid_PING ),
.pid_cks_err( pid_cs_err ),
.token_fadr( token_fadr ),
.token_endp( ep_sel ),
.token_valid( token_valid ),
.crc5_err( crc5_err ),
.frame_no( frame_no ),
.rx_data_st( rx_data_st ),
.rx_data_valid( rx_data_valid ),
.rx_data_done( rx_data_done ),
.crc16_err( crc16_err ),
.seq_err( rx_seq_err )
);
 
// Packet Assembler
usbf_pa u1( .clk( clk ),
.rst( rst ),
.tx_data( tx_data ),
.tx_valid( tx_valid ),
.tx_valid_last( tx_valid_last ),
.tx_ready( tx_ready ),
.tx_first( tx_first ),
.send_token( send_token ),
.token_pid_sel( token_pid_sel ),
.send_data( send_data ),
.data_pid_sel( data_pid_sel ),
.tx_data_st( tx_data_st ),
.rd_next( rd_next )
usbf_pa u1( .clk( clk ),
.rst( rst ),
.tx_data( tx_data ),
.tx_valid( tx_valid ),
.tx_valid_last( tx_valid_last ),
.tx_ready( tx_ready ),
.tx_first( tx_first ),
.send_token( send_token ),
.token_pid_sel( token_pid_sel ),
.send_data( send_data ),
.data_pid_sel( data_pid_sel ),
.send_zero_length( send_zero_length ),
.tx_data_st( tx_data_st ),
.rd_next( rd_next )
);
 
// Internal DMA / Memory Arbiter Interface
usbf_idma #(SSRAM_HADR)
u2( .clk( clk ),
.rst( rst ),
.rx_data_st( rx_data_st ),
.rx_data_valid( rx_data_valid ),
.rx_data_done( rx_data_done ),
.send_data( send_data ),
.tx_data_st( tx_data_st ),
.rd_next( rd_next ),
.rx_dma_en( rx_dma_en ),
.tx_dma_en( tx_dma_en ),
.abort( abort ),
.idma_done( idma_done ),
.adr( adr ),
.size( size ),
.buf_size( buf_size ),
.dma_en( dma_en ),
.madr( madr ),
.sizu_c( sizu_c ),
.mdout( mdout ),
.mdin( mdin ),
.mwe( mwe ),
.mreq( mreq ),
.mack( mack )
u2( .clk( clk ),
.rst( rst ),
.rx_data_st( rx_data_st ),
.rx_data_valid( rx_data_valid ),
.rx_data_done( rx_data_done ),
.send_data( send_data ),
.tx_data_st( tx_data_st ),
.rd_next( rd_next ),
.rx_dma_en( rx_dma_en ),
.tx_dma_en( tx_dma_en ),
.abort( abort ),
.idma_done( idma_done ),
.adr( adr ),
.size( size ),
.buf_size( buf_size ),
.dma_en( dma_en ),
.send_zero_length( send_zero_length ),
.madr( madr ),
.sizu_c( sizu_c ),
.mdout( mdout ),
.mdin( mdin ),
.mwe( mwe ),
.mreq( mreq ),
.mack( mack )
);
 
// Protocol Engine
416,6 → 436,7
.send_token( send_token ),
.token_pid_sel( token_pid_sel ),
.data_pid_sel( data_pid_sel ),
.send_zero_length( send_zero_length ),
.rx_dma_en( rx_dma_en ),
.tx_dma_en( tx_dma_en ),
.abort( abort ),
/trunk/rtl/verilog/usbf_utmi_ls.v
11,8 → 11,9
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// Copyright (C) 2000-2003 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
37,10 → 38,10
 
// CVS Log
//
// $Id: usbf_utmi_ls.v,v 1.4 2001-11-04 12:22:45 rudi Exp $
// $Id: usbf_utmi_ls.v,v 1.5 2003-10-17 02:36:57 rudi Exp $
//
// $Date: 2001-11-04 12:22:45 $
// $Revision: 1.4 $
// $Date: 2003-10-17 02:36:57 $
// $Revision: 1.5 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 48,11
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.4 2001/11/04 12:22:45 rudi
//
// - Fixed previous fix (brocke something else ...)
// - Majore Synthesis cleanup
//
// Revision 1.3 2001/09/24 01:15:28 rudi
//
// Changed reset to be active high async.
80,7 → 86,7
 
`include "usbf_defines.v"
 
module usbf_utmi_ls( clk, wclk, rst,
module usbf_utmi_ls( clk, rst,
 
resume_req,
 
90,11 → 96,12
usb_vbus,
 
// Misc Interfaces
mode_hs, usb_reset, usb_suspend, usb_attached
mode_hs, usb_reset, usb_suspend, usb_attached,
suspend_clr
);
 
input clk;
input wclk;
//input wclk;
input rst;
 
input resume_req;
113,6 → 120,8
output usb_suspend; // USB Suspend
output usb_attached; // Attached to USB
 
output suspend_clr;
 
///////////////////////////////////////////////////////////////////
//
// Parameters
123,7 → 132,7
RES_SUSP = 15'b000_0000_0000_0100,
SUSPEND = 15'b000_0000_0000_1000,
RESUME = 15'b000_0000_0001_0000,
RESUME_REQ = 15'b000_0000_0010_0000,
RESUME_REQUEST = 15'b000_0000_0010_0000,
RESUME_WAIT = 15'b000_0000_0100_0000,
RESUME_SIG = 15'b000_0000_1000_0000,
ATTACH = 15'b000_0001_0000_0000,
155,7 → 164,7
 
wire ls_se0, ls_j, ls_k, ls_se1;
reg ls_k_r, ls_j_r, ls_se0_r;
reg ls_idle_r, ls_idle_r1;
reg ls_idle_r;
wire ls_idle;
reg idle_long;
wire idle_long_set, idle_long_clr;
169,7 → 178,7
reg idle_cnt1_clr;
reg [7:0] idle_cnt1, idle_cnt1_next;
reg [5:0] idle_cnt2;
reg T1_gt_2_5_uS, T1_gt_100_uS, T1_st_3_0_mS, T1_gt_3_0_mS;
reg T1_gt_2_5_uS, T1_st_3_0_mS, T1_gt_3_0_mS;
reg T1_gt_3_125_mS, T1_gt_5_0_mS;
reg [7:0] me_ps;
reg me_cnt_clr;
184,8 → 193,6
reg chirp_cnt_clr, chirp_cnt_inc;
reg chirp_cnt_is_6;
 
reg suspend_clr_wr;
reg resume_req_r;
reg resume_req_s1;
reg resume_req_s;
 
195,66 → 202,56
//
 
always @(posedge clk)
drive_k <= #1 drive_k_d;
drive_k <= drive_k_d;
 
assign SuspendM = (usb_suspend & !resume_req_s) | (LineState == 2'b10);
 
always @(posedge wclk)
suspend_clr_wr <= #1 suspend_clr;
 
always @(posedge wclk)
if(!rst) resume_req_r <= #1 1'b0;
else
if(suspend_clr_wr) resume_req_r <= #1 1'b0;
else
if(resume_req) resume_req_r <= #1 1'b1;
 
always @(posedge clk)
resume_req_s1 <= #1 resume_req_r;
resume_req_s1 <= resume_req;
 
always @(posedge clk)
resume_req_s <= #1 resume_req_s1;
resume_req_s <= resume_req_s1;
 
// ---------------------------------------------------------
// USB State/Operation Mode JK Flops
always @(posedge clk)
if(mode_set_fs) mode_hs <= #1 1'b0;
if(mode_set_fs) mode_hs <= 1'b0;
else
if(mode_set_hs) mode_hs <= #1 1'b1;
if(mode_set_hs) mode_hs <= 1'b1;
 
always @(posedge clk)
if(suspend_clr) usb_suspend <= #1 1'b0;
if(suspend_clr) usb_suspend <= 1'b0;
else
if(suspend_set) usb_suspend <= #1 1'b1;
if(suspend_set) usb_suspend <= 1'b1;
 
always @(posedge clk)
if(attached_clr) usb_attached <= #1 1'b0;
if(attached_clr) usb_attached <= 1'b0;
else
if(attached_set) usb_attached <= #1 1'b1;
if(attached_set) usb_attached <= 1'b1;
 
always @(posedge clk)
if(fs_term_off) TermSel <= #1 1'b0;
if(fs_term_off) TermSel <= 1'b0;
else
if(fs_term_on) TermSel <= #1 1'b1;
if(fs_term_on) TermSel <= 1'b1;
 
always @(posedge clk)
if(xcv_set_fs) XcvSelect <= #1 1'b1;
if(xcv_set_fs) XcvSelect <= 1'b1;
else
if(xcv_set_hs) XcvSelect <= #1 1'b0;
if(xcv_set_hs) XcvSelect <= 1'b0;
 
always @(posedge clk)
if(bit_stuff_off) OpMode <= #1 2'b10;
if(bit_stuff_off) OpMode <= 2'b10;
else
if(bit_stuff_on) OpMode <= #1 2'b00;
if(bit_stuff_on) OpMode <= 2'b00;
 
always @(posedge clk)
usb_reset <= #1 usb_reset_d;
usb_reset <= usb_reset_d;
 
// ---------------------------------------------------------
// Line State Detector
 
always @(posedge clk)
line_state_r <= #1 LineState;
line_state_r <= LineState;
 
assign ls_se0 = (line_state_r == 2'b00);
assign ls_j = (line_state_r == 2'b01);
267,27 → 264,31
// Idle Has to persist for at least two cycles in a roe in the
// same state to recognized
always @(posedge clk)
ls_idle_r <= #1 ls_idle;
ls_idle_r <= ls_idle;
 
assign idle_long_set = ls_idle & ls_idle_r;
assign idle_long_clr = !ls_idle & !ls_idle_r;
 
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
if(!rst) idle_long <= #1 1'b0;
`else
always @(posedge clk)
`endif
if(!rst) idle_long <= 1'b0;
else
if(idle_long_clr) idle_long <= #1 1'b0;
if(idle_long_clr) idle_long <= 1'b0;
else
if(idle_long_set) idle_long <= #1 1'b1;
if(idle_long_set) idle_long <= 1'b1;
 
// Detect Signals for two cycles ina row before making a transaction ...
always @(posedge clk)
ls_k_r <= #1 ls_k;
ls_k_r <= ls_k;
 
always @(posedge clk)
ls_j_r <= #1 ls_j;
ls_j_r <= ls_j;
 
always @(posedge clk)
ls_se0_r <= #1 ls_se0;
ls_se0_r <= ls_se0;
 
assign k_long = ls_k & ls_k_r;
assign j_long = ls_j & ls_j_r;
304,47 → 305,44
// Pre-Scaler
// Generates a 0.25 uS Count Enable (ps_cnt_clr)
always @(posedge clk)
if(!idle_long | idle_cnt_clr | ps_cnt_clr) ps_cnt <= #1 4'd0;
else ps_cnt <= #1 ps_cnt + 4'd1;
if(!idle_long || idle_cnt_clr || ps_cnt_clr) ps_cnt <= 4'd0;
else ps_cnt <= ps_cnt + 4'd1;
 
always @(posedge clk) // Clear the pre-scaler in 250 nS intervals
ps_cnt_clr <= #1 (ps_cnt == `USBF_T1_PS_250_NS);
ps_cnt_clr <= (ps_cnt == `USBF_T1_PS_250_NS);
 
// Count uS
always @(posedge clk)
if(!idle_long | idle_cnt1_clr | idle_cnt_clr) idle_cnt1 <= #1 8'h0;
if(!idle_long || idle_cnt1_clr || idle_cnt_clr) idle_cnt1 <= 8'h0;
else
if(!T1_gt_3_125_mS & ps_cnt_clr) idle_cnt1 <= #1 idle_cnt1_next;
if(!T1_gt_3_125_mS && ps_cnt_clr) idle_cnt1 <= idle_cnt1_next;
 
always @(posedge clk)
idle_cnt1_next <= #1 idle_cnt1 + 8'h1;
idle_cnt1_next <= idle_cnt1 + 8'h1;
 
always @(posedge clk) // Clear the uS counter every 62.5 uS
idle_cnt1_clr <= #1 idle_cnt1 == `USBF_T1_C_62_5_US;
idle_cnt1_clr <= idle_cnt1 == `USBF_T1_C_62_5_US;
 
// Count mS
always @(posedge clk)
if(!idle_long | idle_cnt_clr) idle_cnt2 <= #1 6'h0;
if(!idle_long || idle_cnt_clr) idle_cnt2 <= 6'h0;
else
if(!T1_gt_5_0_mS & idle_cnt1_clr) idle_cnt2 <= #1 idle_cnt2 + 6'h1;
if(!T1_gt_5_0_mS && idle_cnt1_clr) idle_cnt2 <= idle_cnt2 + 6'h1;
 
always @(posedge clk) // Greater Than 2.5uS (Actual Time will be T0+2.75uS)
T1_gt_2_5_uS <= #1 !idle_cnt_clr & (idle_cnt1 > `USBF_T1_C_2_5_US);
T1_gt_2_5_uS <= !idle_cnt_clr & (idle_cnt1 > `USBF_T1_C_2_5_US);
 
always @(posedge clk) // Greater Than 100uS (Actual Time will be T0+187.5uS)
T1_gt_100_uS <= #1 !idle_cnt_clr & (`USBF_T1_C_100_US < idle_cnt2);
 
always @(posedge clk) // Smaller Than 3 mS (Actual Time will be 0-2.9375mS)
T1_st_3_0_mS <= #1 !idle_cnt_clr & (idle_cnt1 < `USBF_T1_C_3_0_MS);
T1_st_3_0_mS <= !idle_cnt_clr & (idle_cnt1 < `USBF_T1_C_3_0_MS);
 
always @(posedge clk) // Greater Than 3 mS (Actual Time will be T0+3.0625mS)
T1_gt_3_0_mS <= #1 !idle_cnt_clr & (idle_cnt1 > `USBF_T1_C_3_0_MS);
T1_gt_3_0_mS <= !idle_cnt_clr & (idle_cnt1 > `USBF_T1_C_3_0_MS);
 
always @(posedge clk) // Greater Than 3.125 mS (Actual Time will be T0+3.1875uS)
T1_gt_3_125_mS <= #1 !idle_cnt_clr & (idle_cnt1 > `USBF_T1_C_3_125_MS);
T1_gt_3_125_mS <= !idle_cnt_clr & (idle_cnt1 > `USBF_T1_C_3_125_MS);
 
always @(posedge clk) // Greater Than 3.125 mS (Actual Time will be T0+3.1875uS)
T1_gt_5_0_mS <= #1 !idle_cnt_clr & (idle_cnt1 > `USBF_T1_C_5_MS);
T1_gt_5_0_mS <= !idle_cnt_clr & (idle_cnt1 > `USBF_T1_C_5_MS);
 
// ---------------------------------------------------------
// Misc Events Counter
351,52 → 349,52
 
// Pre-scaler - 2.5uS
always @(posedge clk)
if(me_cnt_clr | me_ps_2_5_us) me_ps <= #1 8'h0;
else me_ps <= #1 me_ps + 8'h1;
if(me_cnt_clr || me_ps_2_5_us) me_ps <= 8'h0;
else me_ps <= me_ps + 8'h1;
 
always @(posedge clk) // Generate a pulse every 2.5 uS
me_ps_2_5_us <= #1 (me_ps == `USBF_T2_C_2_5_US);
me_ps_2_5_us <= (me_ps == `USBF_T2_C_2_5_US);
 
// Second Pre-scaler - 0.5mS
always @(posedge clk)
if(me_cnt_clr | me_ps2_0_5_ms ) me_ps2 <= #1 8'h0;
if(me_cnt_clr || me_ps2_0_5_ms ) me_ps2 <= 8'h0;
else
if(me_ps_2_5_us) me_ps2 <= #1 me_ps2 + 8'h1;
if(me_ps_2_5_us) me_ps2 <= me_ps2 + 8'h1;
 
always @(posedge clk) // Generate a pulse every 0.5 mS
me_ps2_0_5_ms <= #1 (me_ps2 == `USBF_T2_C_0_5_MS) & !me_ps2_0_5_ms;
me_ps2_0_5_ms <= (me_ps2 == `USBF_T2_C_0_5_MS) & !me_ps2_0_5_ms;
 
// final misc Counter
always @(posedge clk)
if(me_cnt_clr) me_cnt <= #1 8'h0;
if(me_cnt_clr) me_cnt <= 8'h0;
else
if(!me_cnt_100_ms & me_ps2_0_5_ms) me_cnt <= #1 me_cnt + 8'h1;
if(!me_cnt_100_ms && me_ps2_0_5_ms) me_cnt <= me_cnt + 8'h1;
 
always @(posedge clk) // Indicate when 100uS have passed
T2_gt_100_uS <= #1 !me_cnt_clr & (me_ps2 > `USBF_T2_C_100_US); // Actual Time: 102.5 uS
T2_gt_100_uS <= !me_cnt_clr & (me_ps2 > `USBF_T2_C_100_US); // Actual Time: 102.5 uS
 
always @(posedge clk) // Indicate when wakeup period has passed
T2_wakeup <= #1 !me_cnt_clr & (me_cnt > `USBF_T2_C_WAKEUP);
T2_wakeup <= !me_cnt_clr & (me_cnt > `USBF_T2_C_WAKEUP);
 
always @(posedge clk) // Indicate when 1 mS has passed
T2_gt_1_0_mS <= #1 !me_cnt_clr & (me_cnt > `USBF_T2_C_1_0_MS); // Actual Time: 1.5 mS
T2_gt_1_0_mS <= !me_cnt_clr & (me_cnt > `USBF_T2_C_1_0_MS); // Actual Time: 1.5 mS
 
always @(posedge clk) // Indicate when 1.2 mS has passed
T2_gt_1_2_mS <= #1 !me_cnt_clr & (me_cnt > `USBF_T2_C_1_2_MS); // Actual Time: 1.5 mS
T2_gt_1_2_mS <= !me_cnt_clr & (me_cnt > `USBF_T2_C_1_2_MS); // Actual Time: 1.5 mS
 
always @(posedge clk) // Generate a pulse after 100 mS
me_cnt_100_ms <= #1 !me_cnt_clr & (me_cnt == `USBF_T2_C_100_MS); // Actual Time: 100 mS
me_cnt_100_ms <= !me_cnt_clr & (me_cnt == `USBF_T2_C_100_MS); // Actual Time: 100 mS
 
// ---------------------------------------------------------
// Chirp Counter
 
always @(posedge clk)
if(chirp_cnt_clr) chirp_cnt <= #1 3'h0;
if(chirp_cnt_clr) chirp_cnt <= 3'h0;
else
if(chirp_cnt_inc) chirp_cnt <= #1 chirp_cnt + 3'h1;
if(chirp_cnt_inc) chirp_cnt <= chirp_cnt + 3'h1;
 
always @(posedge clk)
chirp_cnt_is_6 <= #1 (chirp_cnt == 3'h6);
chirp_cnt_is_6 <= (chirp_cnt == 3'h6);
 
///////////////////////////////////////////////////////////////////
//
403,17 → 401,21
// Main State Machine
//
 
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
if(!rst) state <= #1 POR;
`else
always @(posedge clk)
`endif
if(!rst) state <= POR;
else
if(usb_vbus) state <= #1 POR;
else state <= #1 next_state;
if(usb_vbus) state <= POR;
else state <= next_state;
 
always @(state or mode_hs or idle_long or resume_req_s or me_cnt_100_ms or
j_long or k_long or se0_long or ls_se0 or
T1_gt_2_5_uS or T1_gt_100_uS or T1_st_3_0_mS or T1_gt_3_0_mS or T1_gt_5_0_mS or
T2_gt_100_uS or T2_wakeup or T2_gt_1_0_mS or T2_gt_1_2_mS or
chirp_cnt_is_6)
T1_gt_2_5_uS or T1_st_3_0_mS or T1_gt_3_0_mS or
T1_gt_5_0_mS or T2_gt_100_uS or T2_wakeup or T2_gt_1_0_mS or
T2_gt_1_2_mS or chirp_cnt_is_6)
begin
next_state = state; // Default don't change state
 
446,7 → 448,7
fs_term_on = 1'b1;
mode_set_fs = 1'b1;
attached_clr = 1'b1;
bit_stuff_on = 1'b1;
bit_stuff_on = 1'b0;
suspend_clr = 1'b1;
next_state = ATTACH;
end
453,13 → 455,13
 
NORMAL: // Normal Operation
begin
if(!mode_hs & T1_gt_2_5_uS & T1_st_3_0_mS & !idle_long)
if(!mode_hs && T1_gt_2_5_uS && T1_st_3_0_mS && !idle_long)
begin
me_cnt_clr = 1'b1;
next_state = RESET;
end
else
if(!mode_hs & T1_gt_3_0_mS)
if(!mode_hs && T1_gt_3_0_mS)
begin
idle_cnt_clr = 1'b1;
suspend_set = 1'b1;
466,7 → 468,7
next_state = SUSPEND;
end
else
if(mode_hs & T1_gt_3_0_mS)
if(mode_hs && T1_gt_3_0_mS)
begin // Switch to FS mode, and decide
// if it's a RESET or SUSPEND
me_cnt_clr = 1'b1;
478,13 → 480,13
 
RES_SUSP: // Decide if it's a Reset or Suspend Signaling
begin // We are now in FS mode, wait 100uS first
if(T2_gt_100_uS & se0_long)
if(T2_gt_100_uS && se0_long)
begin
me_cnt_clr = 1'b1;
next_state = RESET;
end
else
if(T2_gt_100_uS & j_long)
if(T2_gt_100_uS && j_long)
begin
idle_cnt_clr = 1'b1;
suspend_set = 1'b1;
494,7 → 496,7
 
SUSPEND: // In Suspend
begin
if(T1_gt_2_5_uS & se0_long)
if(T1_gt_2_5_uS && se0_long)
begin
suspend_clr = 1'b1;
me_cnt_clr = 1'b1;
506,8 → 508,8
next_state = RESUME;
end
else
if(T1_gt_5_0_mS & resume_req_s)
next_state = RESUME_REQ;
if(T1_gt_5_0_mS && resume_req_s)
next_state = RESUME_REQUEST;
end
 
RESUME:
530,7 → 532,7
if(T2_gt_100_uS) next_state = NORMAL;
end
 
RESUME_REQ: // Function Resume Request
RESUME_REQUEST: // Function Resume Request
begin
suspend_clr = 1'b1;
// Wait for internal wake up
552,12 → 554,12
ATTACH: // Attach To USB Detected
begin
idle_cnt_clr = 1'b1;
if(me_cnt_100_ms & j_long)
if(me_cnt_100_ms && j_long)
begin
attached_set = 1'b1;
next_state = NORMAL;
end
if(me_cnt_100_ms & se0_long)
if(me_cnt_100_ms && se0_long)
begin
attached_set = 1'b1;
me_cnt_clr = 1'b1;
568,9 → 570,10
RESET: // In Reset
begin
usb_reset_d = 1'b1; // Assert Internal USB Reset
xcv_set_hs = 1'b1; // Switch xcvr to HS mode
fs_term_on = 1'b1; // Turn FS termination On
xcv_set_hs = 1'b1; // Switch xcvr to HS mode
fs_term_on = 1'b1; // Turn FS termination On
mode_set_fs = 1'b1; // Change mode to FS
bit_stuff_off = 1'b1; // disable Bit Stuffing and NRZI encoding
// Get out of reset after 1.5 mS
if(T2_gt_1_0_mS)
begin
619,14 → 622,16
 
SPEED_NEG_HS:
begin
bit_stuff_on = 1'b1; // Enable Bit Stuffing and NRZI encoding
xcv_set_hs = 1'b1; // Switch xcvr to HS mode
fs_term_off = 1'b1; // Turn FS termination Off
mode_set_hs = 1'b1; // Change mode to FS
mode_set_hs = 1'b1; // Change mode to HS
if(se0_long) next_state = NORMAL;
end
 
SPEED_NEG_FS:
begin
bit_stuff_on = 1'b1; // Enable Bit Stuffing and NRZI encoding
xcv_set_fs = 1'b1; // Switch xcvr to FS mode
fs_term_on = 1'b1; // Turn FS termination On
mode_set_fs = 1'b1; // Change mode to FS
/trunk/rtl/verilog/usbf_defines.v
11,8 → 11,9
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// Copyright (C) 2000-2003 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
37,10 → 38,10
 
// CVS Log
//
// $Id: usbf_defines.v,v 1.5 2001-11-04 12:22:43 rudi Exp $
// $Id: usbf_defines.v,v 1.6 2003-10-17 02:36:57 rudi Exp $
//
// $Date: 2001-11-04 12:22:43 $
// $Revision: 1.5 $
// $Date: 2003-10-17 02:36:57 $
// $Revision: 1.6 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 48,11
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.5 2001/11/04 12:22:43 rudi
//
// - Fixed previous fix (brocke something else ...)
// - Majore Synthesis cleanup
//
// Revision 1.4 2001/09/23 08:39:33 rudi
//
// Renamed DEBUG and VERBOSE_DEBUG to USBF_DEBUG and USBF_VERBOSE_DEBUG ...
92,9 → 98,15
 
`timescale 1ns / 10ps
 
// Uncomment the lines below to get various levels of debugging
// verbosity ...
`define USBF_DEBUG
//`define USBF_VERBOSE_DEBUG
 
// Uncomment the line below to run the test bench
// Comment it out to use your own address parameters ...
`define USBF_TEST_IMPL
 
// For each endpoint that should actually be instantiated,
// set the below define value to a one. Uncomment the define
// statement for unused endpoints. The endpoints should be
103,22 → 115,32
// Actual (logical) endpoint IDs are set by the software. There
// is no correlation between the physical endpoint number (below)
// and the actual (logical) endpoint number.
`define USBF_HAVE_EP1 1
`define USBF_HAVE_EP2 1
`define USBF_HAVE_EP3 1
//`define USBF_HAVE_EP4 1
//`define USBF_HAVE_EP5 1
//`define USBF_HAVE_EP6 1
//`define USBF_HAVE_EP7 1
//`define USBF_HAVE_EP8 1
//`define USBF_HAVE_EP9 1
//`define USBF_HAVE_EP10 1
//`define USBF_HAVE_EP11 1
//`define USBF_HAVE_EP12 1
//`define USBF_HAVE_EP13 1
//`define USBF_HAVE_EP14 1
//`define USBF_HAVE_EP15 1
`ifdef USBF_TEST_IMPL
// Do not modify this section
// this is to run the test bench
`define USBF_HAVE_EP1 1
`define USBF_HAVE_EP2 1
`define USBF_HAVE_EP3 1
`else
// Modify this section to suit your implementation
`define USBF_HAVE_EP1 1
`define USBF_HAVE_EP2 1
`define USBF_HAVE_EP3 1
//`define USBF_HAVE_EP4 1
//`define USBF_HAVE_EP5 1
//`define USBF_HAVE_EP6 1
//`define USBF_HAVE_EP7 1
//`define USBF_HAVE_EP8 1
//`define USBF_HAVE_EP9 1
//`define USBF_HAVE_EP10 1
//`define USBF_HAVE_EP11 1
//`define USBF_HAVE_EP12 1
//`define USBF_HAVE_EP13 1
//`define USBF_HAVE_EP14 1
//`define USBF_HAVE_EP15 1
`endif
 
 
// Highest address line number that goes to the USB core
// Typically only A0 through A17 are needed, where A17
// selects between the internal buffer memory and the
125,14 → 147,28
// register file.
// Implementations may choose to have a more complex address
// decoding ....
`define USBF_UFC_HADR 17
 
// Address Decoding for Register File select
`define USBF_RF_SEL (!wb_addr_i[17])
// Address Decoding for Buffer Memory select
`define USBF_MEM_SEL (wb_addr_i[17])
`ifdef USBF_TEST_IMPL
// Do not modify this section
// this is to run the test bench
`define USBF_UFC_HADR 17
`define USBF_RF_SEL (!wb_addr_i[17])
`define USBF_MEM_SEL (wb_addr_i[17])
`define USBF_SSRAM_HADR 14
//`define USBF_ASYNC_RESET
 
`define USBF_SSRAM_HADR 14
`else
// Modify this section to suit your implementation
`define USBF_UFC_HADR 12
// Address Decoding for Register File select
`define USBF_RF_SEL (!wb_addr_i[12])
// Address Decoding for Buffer Memory select
`define USBF_MEM_SEL (wb_addr_i[12])
`define USBF_SSRAM_HADR 9
// The next statement determines if reset is async or sync.
// If the define is uncommented the reset will be ASYNC.
//`define USBF_ASYNC_RESET
`endif
 
 
/////////////////////////////////////////////////////////////////////
167,7 → 203,7
// Phy clocks there are between two hms_clock pulses. This
// constant plus 2 represents the actual delay.
// Example: For a 60 Mhz (16.667 nS period) Phy Clock, the
// delay must be 30 phy clock: 500ns / 16.667nS = 30 clocks
// delay must be 30 phy clocks: 500ns / 16.667nS = 30 clocks
`define USBF_HMS_DEL 5'h1c
 
// After sending Data in response to an IN token from host, the
179,7 → 215,7
`define USBF_RX_ACK_TO_VAL_HS 8'd22
 
 
// After sending a OUT token the host must send a data packet.
// After sending an OUT token the host must send a data packet.
// The host has 622nS in Full Speed mode and 400nS in High Speed
// mode to send the data packet.
// TX_DATA_TO_VAL_FS and TX_DATA_TO_VAL_HS are is the numbers of
209,17 → 245,14
// The clear value is 62.5uS/0.25uS=250 cycles.
`define USBF_T1_C_62_5_US 8'd250
 
// mS counter representation of 100uS (100/62.5=1.6 -> 2)
`define USBF_T1_C_100_US 7'd2
 
// mS counter representation of 3.0mS (3.0/0.0625=48)
`define USBF_T1_C_3_0_MS 7'd48
`define USBF_T1_C_3_0_MS 8'd48
 
// mS counter representation of 3.125mS (3.125/0.0625=50)
`define USBF_T1_C_3_125_MS 7'd50
`define USBF_T1_C_3_125_MS 8'd50
 
// mS counter representation of 5mS (5/0.0625=80)
`define USBF_T1_C_5_MS 7'd50
`define USBF_T1_C_5_MS 8'd80
 
// Multi purpose Counter Prescaler, generate 2.5 uS period
// 2500/16.667ns=150 (minus 2 for pipeline)
232,21 → 265,21
// Indicate when internal wakeup has completed
// me_cnt counts 0.5 mS intervals. E.g.: 5.0mS are (5/0.5) 10 ticks
// Must be 0 =< 10 mS
`define USBF_T2_C_WAKEUP 10
`define USBF_T2_C_WAKEUP 8'd10
 
// Indicate when 100uS have passed
// me_ps2 counts 2.5uS intervals. 100uS are (100/2.5) 40 ticks
`define USBF_T2_C_100_US 40
`define USBF_T2_C_100_US 8'd40
 
// Indicate when 1.0 mS have passed
// me_cnt counts 0.5 mS intervals. 1.0mS are (1/0.5) 2 ticks
`define USBF_T2_C_1_0_MS 2
`define USBF_T2_C_1_0_MS 8'd2
 
// Indicate when 1.2 mS have passed
// me_cnt counts 0.5 mS intervals. 1.2mS are (1.2/0.5) 2 ticks
`define USBF_T2_C_1_2_MS 2
`define USBF_T2_C_1_2_MS 8'd2
 
// Indicate when 100 mS have passed
// me_cnt counts 0.5 mS intervals. 100mS are (100/0.5) 200 ticks
`define USBF_T2_C_100_MS 200
`define USBF_T2_C_100_MS 8'd200
 
/trunk/rtl/verilog/usbf_crc16.v
11,8 → 11,9
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// Copyright (C) 2000-2003 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
37,10 → 38,10
 
// CVS Log
//
// $Id: usbf_crc16.v,v 1.1 2001-08-03 05:30:09 rudi Exp $
// $Id: usbf_crc16.v,v 1.2 2003-10-17 02:36:57 rudi Exp $
//
// $Date: 2001-08-03 05:30:09 $
// $Revision: 1.1 $
// $Date: 2003-10-17 02:36:57 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 48,11
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/08/03 05:30:09 rudi
//
//
// 1) Reorganized directory structure
//
// Revision 1.0 2001/03/07 09:17:12 rudi
//
//
/trunk/rtl/verilog/usbf_ep_rf.v
11,8 → 11,9
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// Copyright (C) 2000-2003 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
37,10 → 38,10
 
// CVS Log
//
// $Id: usbf_ep_rf.v,v 1.3 2001-11-04 12:22:44 rudi Exp $
// $Id: usbf_ep_rf.v,v 1.4 2003-10-17 02:36:57 rudi Exp $
//
// $Date: 2001-11-04 12:22:44 $
// $Revision: 1.3 $
// $Date: 2003-10-17 02:36:57 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 48,11
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/11/04 12:22:44 rudi
//
// - Fixed previous fix (brocke something else ...)
// - Majore Synthesis cleanup
//
// Revision 1.2 2001/11/03 03:26:22 rudi
//
// - Fixed several interrupt and error condition reporting bugs
147,7 → 153,7
reg [1:0] uc_bsel, uc_dpd;
 
reg [5:0] iena, ienb; // Interrupt enables
reg [6:0] is; // Interrupt status
reg [6:0] int_stat; // Interrupt status
 
wire we0, we1, we2, we3;
reg [31:0] buf0;
170,7 → 176,6
wire dma_req_in_d;
wire dma_req_out_d;
reg r1, r2, r4, r5;
wire r3;
wire dma_ack_i;
reg dma_req_out_hold, dma_req_in_hold ;
reg [11:0] buf0_orig_m3;
188,7 → 193,7
wire ep_out;
 
assign csr = {uc_bsel, uc_dpd, csr1, 1'h0, ots_stop, csr0};
assign int = { 2'h0, iena, 2'h0,ienb, 9'h0, is};
assign int = {2'h0, iena, 2'h0,ienb, 9'h0, int_stat};
assign dma_en = csr[15];
assign max_pl_sz = csr[10:0];
assign ep_in = csr[27:26]==2'b01;
213,60 → 218,80
assign we3 = (adr==2'h3) & we;
 
// Endpoint CSR Register
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst)
begin
csr0 <= #1 13'h0;
csr1 <= #1 13'h0;
ots_stop <= #1 1'b0;
csr0 <= 13'h0;
csr1 <= 13'h0;
ots_stop <= 1'b0;
end
else
if(we0)
begin
csr0 <= #1 din[12:0];
ots_stop <= #1 din[13];
csr1 <= #1 din[27:15];
csr0 <= din[12:0];
ots_stop <= din[13];
csr1 <= din[27:15];
end
else
if(ots_stop & out_to_small)
csr1[8:7] <= #1 2'b01;
if(ots_stop && out_to_small)
csr1[8:7] <= 2'b01;
 
// Endpoint Interrupt Register
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst)
begin
ienb <= #1 6'h0;
iena <= #1 6'h0;
ienb <= 6'h0;
iena <= 6'h0;
end
else
if(we1)
begin
ienb <= #1 din[21:16];
iena <= #1 din[29:24];
ienb <= din[21:16];
iena <= din[29:24];
end
 
// Endpoint Buffer Registers
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
if(!rst) buf0 <= #1 32'hffff_ffff;
`endif
if(!rst) buf0 <= 32'hffff_ffff;
else
if(we2) buf0 <= #1 din;
if(we2) buf0 <= din;
else
if(ep_match_r & buf0_rl) buf0 <= #1 buf0_orig;
if(ep_match_r && buf0_rl) buf0 <= buf0_orig;
else
if(ep_match_r & buf0_set) buf0 <= #1 idin;
if(ep_match_r && buf0_set) buf0 <= idin;
 
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
if(!rst) buf1 <= #1 32'hffff_ffff;
`endif
if(!rst) buf1 <= 32'hffff_ffff;
else
if(we3) buf1 <= #1 din;
if(we3) buf1 <= din;
else
if(ep_match_r &
(buf1_set | out_to_small)) buf1 <= #1 idin;
if(ep_match_r &&
(buf1_set || out_to_small)) buf1 <= idin;
 
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
if(!rst) buf0_orig <= #1 32'hffff_ffff;
`endif
if(!rst) buf0_orig <= 32'hffff_ffff;
else
if(we2) buf0_orig <= #1 din;
if(we2) buf0_orig <= din;
 
///////////////////////////////////////////////////////////////////
//
279,39 → 304,51
assign ep_match = (ep_sel == csr[21:18]);
 
always @(posedge clk)
ep_match_r <= #1 ep_match;
ep_match_r <= ep_match;
 
always @(posedge clk)
int_re <= #1 re & (adr == 2'h1);
int_re <= re & (adr == 2'h1);
 
// Interrupt Sources
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
if(!rst) is <= #1 7'h0;
`endif
if(!rst) int_stat <= 7'h0;
else
if(int_re) is <= #1 7'h0;
if(int_re) int_stat <= 7'h0;
else
if(ep_match_r)
begin
if(out_to_small) is[6] <= #1 1'b1;
if(int_seqerr_set) is[5] <= #1 1'b1;
if(int_buf1_set) is[4] <= #1 1'b1;
if(int_buf0_set) is[3] <= #1 1'b1;
if(int_upid_set) is[2] <= #1 1'b1;
if(int_crc16_set) is[1] <= #1 1'b1;
if(int_to_set) is[0] <= #1 1'b1;
if(out_to_small) int_stat[6] <= 1'b1;
if(int_seqerr_set) int_stat[5] <= 1'b1;
if(int_buf1_set) int_stat[4] <= 1'b1;
if(int_buf0_set) int_stat[3] <= 1'b1;
if(int_upid_set) int_stat[2] <= 1'b1;
if(int_crc16_set) int_stat[1] <= 1'b1;
if(int_to_set) int_stat[0] <= 1'b1;
end
 
// PID toggle track bits
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
if(!rst) uc_dpd <= #1 2'h0;
`endif
if(!rst) uc_dpd <= 2'h0;
else
if(ep_match_r & uc_dpd_set) uc_dpd <= #1 idin[3:2];
if(ep_match_r && uc_dpd_set) uc_dpd <= idin[3:2];
 
// Buffer toggle track bits
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
if(!rst) uc_bsel <= #1 2'h0;
`endif
if(!rst) uc_bsel <= 2'h0;
else
if(ep_match_r & uc_bsel_set) uc_bsel <= #1 idin[1:0];
if(ep_match_r && uc_bsel_set) uc_bsel <= idin[1:0];
 
///////////////////////////////////////////////////////////////////
//
319,22 → 356,22
//
 
always @(posedge wclk)
inta <= #1 (is[0] & iena[0]) |
(is[1] & iena[1]) |
(is[2] & iena[2]) |
(is[3] & iena[3]) |
(is[4] & iena[3]) |
(is[5] & iena[4]) |
(is[6] & iena[5]);
inta <= (int_stat[0] & iena[0]) |
(int_stat[1] & iena[1]) |
(int_stat[2] & iena[2]) |
(int_stat[3] & iena[3]) |
(int_stat[4] & iena[3]) |
(int_stat[5] & iena[4]) |
(int_stat[6] & iena[5]);
 
always @(posedge wclk)
intb <= #1 (is[0] & ienb[0]) |
(is[1] & ienb[1]) |
(is[2] & ienb[2]) |
(is[3] & ienb[3]) |
(is[4] & ienb[3]) |
(is[5] & ienb[4]) |
(is[6] & ienb[5]);
intb <= (int_stat[0] & ienb[0]) |
(int_stat[1] & ienb[1]) |
(int_stat[2] & ienb[2]) |
(int_stat[3] & ienb[3]) |
(int_stat[4] & ienb[3]) |
(int_stat[5] & ienb[4]) |
(int_stat[6] & ienb[5]);
 
///////////////////////////////////////////////////////////////////
//
343,16 → 380,17
 
// DMA OUT endpoint counter
always @(posedge clk)
if(!dma_en) dma_out_cnt <= #1 12'h0;
if(!dma_en) dma_out_cnt <= 12'h0;
else
if(dma_ack_i) dma_out_cnt <= #1 dma_out_cnt - 12'h1;
if(dma_ack_i) dma_out_cnt <= dma_out_cnt - 12'h1;
else
if(set_r | buf0_set | buf0_rl) dma_out_cnt <= #1 dma_out_cnt + {3'h0, max_pl_sz[10:2]};
if(ep_match_r && (set_r || buf0_set || buf0_rl))
dma_out_cnt <= dma_out_cnt + {3'h0, max_pl_sz[10:2]};
 
// If buf0_set or buf0_rl was asserted at the same time as dma_ack_i
// remember it and perform the add next cycle ...
always @(posedge clk)
set_r <= #1 dma_ack_i & (buf0_set | buf0_rl);
set_r <= dma_ack_i & (buf0_set | buf0_rl);
 
// This signal is used to keep dma_req asserted when we know there is
// plenty of data in the buffer.
361,31 → 399,32
// This is because of the sync logic - it has to propagate first
// before we can determine that the buffer is really empty.
always @(posedge wclk)
dma_req_out_hold <= #1 |dma_out_cnt[11:2] & ep_out;
dma_req_out_hold <= |dma_out_cnt[11:2] & ep_out;
 
assign dma_out_cnt_is_zero = dma_out_cnt == 12'h0;
 
// DMA IN endpoint counter
always @(posedge clk)
if(!dma_en) dma_in_cnt <= #1 12'h0;
if(!dma_en) dma_in_cnt <= 12'h0;
else
if(dma_ack_i) dma_in_cnt <= #1 dma_in_cnt + 12'h1;
if(dma_ack_i) dma_in_cnt <= dma_in_cnt + 12'h1;
else
if(set_r | buf0_set | buf0_rl) dma_in_cnt <= #1 dma_in_cnt - {3'h0, max_pl_sz[10:2]};
if(ep_match_r && (set_r || buf0_set || buf0_rl))
dma_in_cnt <= dma_in_cnt - {3'h0, max_pl_sz[10:2]};
 
// Indicates to Protocol Engine when we have gotten at least one packet in to buffer
// This is for IN transfers only
always @(posedge clk)
dma_in_buf_sz1 <= #1 (dma_in_cnt >= {3'h0,max_pl_sz[10:2]}) &
dma_in_buf_sz1 <= (dma_in_cnt >= {3'h0,max_pl_sz[10:2]}) &
(max_pl_sz[10:0] != 11'h0);
 
// Indicates to Protocol Engine that there is space for at least one MAX_PL_SZ
// packet in buffer. OUT transfers only.
always @(posedge clk)
dma_out_left <= #1 (buf0_orig[30:19] - dma_out_cnt);
dma_out_left <= (buf0_orig[30:19] - dma_out_cnt);
 
always @(posedge clk)
dma_out_buf_avail <= #1 (dma_out_left >= {3'h0, max_pl_sz[10:2]});
dma_out_buf_avail <= (dma_out_left >= {3'h0, max_pl_sz[10:2]});
 
// DMA Request Generation
assign dma_req_d = dma_en & (dma_req_in_d | dma_req_out_d);
398,52 → 437,69
 
 
always @(posedge wclk)
buf0_orig_m3 <= #1 buf0_orig[30:19] - 12'h3;
buf0_orig_m3 <= buf0_orig[30:19] - 12'h3;
 
reg dma_req_in_hold2;
 
always @(posedge wclk)
dma_req_in_hold <= #1 ep_in & |buf0_orig[30:21] & (dma_in_cnt < buf0_orig_m3);
dma_req_in_hold2 <= (dma_in_cnt < buf0_orig_m3);
 
assign dma_req_hold = ep_out ? dma_req_out_hold : dma_req_in_hold;
always @(posedge wclk)
dma_req_in_hold <= ep_in & |buf0_orig[30:21];
 
assign dma_req_hold = ep_out ? dma_req_out_hold : (dma_req_in_hold & dma_req_in_hold2);
 
// Generate a Sync. Request
assign dma_req = dma_req_r;
 
`ifdef USBF_ASYNC_RESET
always @(posedge wclk or negedge rst)
`else
always @(posedge wclk)
if(!rst) dma_req_r <= #1 1'b0;
`endif
if(!rst) dma_req_r <= 1'b0;
else
if(r1 & !r2) dma_req_r <= #1 1'b1;
if(r1 && !r2) dma_req_r <= 1'b1;
else
if(dma_ack & !dma_req_hold) dma_req_r <= #1 1'b0;
if(dma_ack && !dma_req_hold) dma_req_r <= 1'b0;
 
always @(posedge wclk)
r1 <= #1 dma_req_d & !r2 & !r4 & !r5;
r1 <= dma_req_d & !r2 & !r4 & !r5;
 
`ifdef USBF_ASYNC_RESET
always @(posedge wclk or negedge rst)
`else
always @(posedge wclk)
if(!rst) r2 <= #1 1'b0;
`endif
if(!rst) r2 <= 1'b0;
else
if(r1) r2 <= #1 1'b1;
if(r1) r2 <= 1'b1;
else
if(r4) r2 <= #1 1'b0;
if(r4) r2 <= 1'b0;
 
// Synchronize ACK
reg dma_ack_wr1;
reg dma_ack_clr1;
 
`ifdef USBF_ASYNC_RESET
always @(posedge wclk or negedge rst)
`else
always @(posedge wclk)
if(!rst) dma_ack_wr1 <= #1 1'b0;
`endif
if(!rst) dma_ack_wr1 <= 1'b0;
else
if(dma_ack) dma_ack_wr1 <= #1 1'b1;
if(dma_ack) dma_ack_wr1 <= 1'b1;
else
if(dma_ack_clr1) dma_ack_wr1 <= #1 1'b0;
if(dma_ack_clr1) dma_ack_wr1 <= 1'b0;
 
always @(posedge wclk)
dma_ack_clr1 <= #1 r4;
dma_ack_clr1 <= r4;
 
always @(posedge clk)
r4 <= #1 dma_ack_wr1;
r4 <= dma_ack_wr1;
 
always @(posedge clk)
r5 <= #1 r4;
r5 <= r4;
 
assign dma_ack_i = r5;
 

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