URL
https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk
Subversion Repositories usbhostslave
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 12 to Rev 13
- ↔ Reverse comparison
Rev 12 → Rev 13
/tags/rel_00_06_alpha/doc/html/src/hostController/USBHostControlBI.v/index.htm
0,0 → 1,276
<html> |
<head> |
<title>USBHostControlBI.v</title> |
<link rel="stylesheet" href="./../../../css/hde.css"> |
<meta name="Author" content="Steve, Base2Designs"> |
|
</head> |
<body> |
<pre> |
<span id=t_com>//////////////////////////////////////////////////////////////////////</span> |
<span id=t_com>//// ////</span> |
<span id=t_com>//// USBHostControlBI.v ////</span> |
<span id=t_com>//// ////</span> |
<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span> |
<span id=t_com>//// <http://www.opencores.org/cores//> ////</span> |
<span id=t_com>//// ////</span> |
<span id=t_com>//// Module Description: ////</span> |
<span id=t_com>//// </span> |
<span id=t_com>//// ////</span> |
<span id=t_com>//// To Do: ////</span> |
<span id=t_com>//// </span> |
<span id=t_com>//// ////</span> |
<span id=t_com>//// Author(s): ////</span> |
<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com ////</span> |
<span id=t_com>//// ////</span> |
<span id=t_com>//////////////////////////////////////////////////////////////////////</span> |
<span id=t_com>//// ////</span> |
<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////</span> |
<span id=t_com>//// ////</span> |
<span id=t_com>//// This source file may be used and distributed without ////</span> |
<span id=t_com>//// restriction provided that this copyright statement is not ////</span> |
<span id=t_com>//// removed from the file and that any derivative work contains ////</span> |
<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span> |
<span id=t_com>//// ////</span> |
<span id=t_com>//// This source file is free software; you can redistribute it ////</span> |
<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General ////</span> |
<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span> |
<span id=t_com>//// either version 2.1 of the License, or (at your option) any ////</span> |
<span id=t_com>//// later version. ////</span> |
<span id=t_com>//// ////</span> |
<span id=t_com>//// This source is distributed in the hope that it will be ////</span> |
<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied ////</span> |
<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////</span> |
<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more ////</span> |
<span id=t_com>//// details. ////</span> |
<span id=t_com>//// ////</span> |
<span id=t_com>//// You should have received a copy of the GNU Lesser General ////</span> |
<span id=t_com>//// Public License along with this source; if not, download it ////</span> |
<span id=t_com>//// from <http://www.opencores.org/lgpl.shtml> ////</span> |
<span id=t_com>//// ////</span> |
<span id=t_com>//////////////////////////////////////////////////////////////////////</span> |
<span id=t_com>//</span> |
<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:11 sfielding Exp $</span> |
<span id=t_com>//</span> |
<span id=t_com>// CVS Revision History</span> |
<span id=t_com>//</span> |
<span id=t_com>// $Log: not supported by cvs2svn $</span> |
<span id=t_com>//</span> |
|
<span id=t_dir>`include</span> <span id=t_cns>"usbHostControl_h.v"</span> |
|
<span id=t_kwd>module</span> <span id=t_idt>USBHostControlBI</span> (<span id=t_idt>address</span>, <span id=t_idt>dataIn</span>, <span id=t_idt>dataOut</span>, <span id=t_idt>writeEn</span>, |
<span id=t_idt>strobe_i</span>, |
<span id=t_idt>clk</span>, <span id=t_idt>rst</span>, |
<span id=t_idt>SOFSentIntOut</span>, <span id=t_idt>connEventIntOut</span>, <span id=t_idt>resumeIntOut</span>, <span id=t_idt>transDoneIntOut</span>, |
<span id=t_idt>TxTransTypeReg</span>, <span id=t_idt>TxSOFEnableReg</span>, |
<span id=t_idt>TxAddrReg</span>, <span id=t_idt>TxEndPReg</span>, <span id=t_idt>frameNumIn</span>, |
<span id=t_idt>RxPktStatusIn</span>, <span id=t_idt>RxPIDIn</span>, |
<span id=t_idt>connectStateIn</span>, |
<span id=t_idt>SOFSentIn</span>, <span id=t_idt>connEventIn</span>, <span id=t_idt>resumeIntIn</span>, <span id=t_idt>transDoneIn</span>, |
<span id=t_idt>hostControlSelect</span>, |
<span id=t_idt>clrTransReq</span>, |
<span id=t_idt>preambleEn</span>, |
<span id=t_idt>SOFSync</span>, |
<span id=t_idt>TxLineState</span>, |
<span id=t_idt>LineDirectControlEn</span>, |
<span id=t_idt>fullSpeedPol</span>, |
<span id=t_idt>fullSpeedRate</span>, |
<span id=t_idt>transReq</span> |
); |
<span id=t_kwd>input</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>address</span>; |
<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>; |
<span id=t_kwd>input</span> <span id=t_idt>writeEn</span>; |
<span id=t_kwd>input</span> <span id=t_idt>strobe_i</span>; |
<span id=t_kwd>input</span> <span id=t_idt>clk</span>; |
<span id=t_kwd>input</span> <span id=t_idt>rst</span>; |
<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>; |
<span id=t_kwd>output</span> <span id=t_idt>SOFSentIntOut</span>; |
<span id=t_kwd>output</span> <span id=t_idt>connEventIntOut</span>; |
<span id=t_kwd>output</span> <span id=t_idt>resumeIntOut</span>; |
<span id=t_kwd>output</span> <span id=t_idt>transDoneIntOut</span>; |
|
<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxTransTypeReg</span>; |
<span id=t_kwd>output</span> <span id=t_idt>TxSOFEnableReg</span>; |
<span id=t_kwd>output</span> [<span id=t_cns>6</span>:<span id=t_cns>0</span>] <span id=t_idt>TxAddrReg</span>; |
<span id=t_kwd>output</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>TxEndPReg</span>; |
<span id=t_kwd>input</span> [<span id=t_cns>10</span>:<span id=t_cns>0</span>] <span id=t_idt>frameNumIn</span>; |
<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPktStatusIn</span>; |
<span id=t_kwd>input</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPIDIn</span>; |
<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>; |
<span id=t_kwd>input</span> <span id=t_idt>SOFSentIn</span>; |
<span id=t_kwd>input</span> <span id=t_idt>connEventIn</span>; |
<span id=t_kwd>input</span> <span id=t_idt>resumeIntIn</span>; |
<span id=t_kwd>input</span> <span id=t_idt>transDoneIn</span>; |
<span id=t_kwd>input</span> <span id=t_idt>hostControlSelect</span>; |
<span id=t_kwd>input</span> <span id=t_idt>clrTransReq</span>; |
<span id=t_kwd>output</span> <span id=t_idt>preambleEn</span>; |
<span id=t_kwd>output</span> <span id=t_idt>SOFSync</span>; |
<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxLineState</span>; |
<span id=t_kwd>output</span> <span id=t_idt>LineDirectControlEn</span>; |
<span id=t_kwd>output</span> <span id=t_idt>fullSpeedPol</span>; |
<span id=t_kwd>output</span> <span id=t_idt>fullSpeedRate</span>; |
<span id=t_kwd>output</span> <span id=t_idt>transReq</span>; |
|
<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>address</span>; |
<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>; |
<span id=t_kwd>wire</span> <span id=t_idt>writeEn</span>; |
<span id=t_kwd>wire</span> <span id=t_idt>strobe_i</span>; |
<span id=t_kwd>wire</span> <span id=t_idt>clk</span>; |
<span id=t_kwd>wire</span> <span id=t_idt>rst</span>; |
<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>; |
|
<span id=t_kwd>reg</span> <span id=t_idt>SOFSentIntOut</span>; |
<span id=t_kwd>reg</span> <span id=t_idt>connEventIntOut</span>; |
<span id=t_kwd>reg</span> <span id=t_idt>resumeIntOut</span>; |
<span id=t_kwd>reg</span> <span id=t_idt>transDoneIntOut</span>; |
|
<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxTransTypeReg</span>; |
<span id=t_kwd>reg</span> <span id=t_idt>TxSOFEnableReg</span>; |
<span id=t_kwd>reg</span> [<span id=t_cns>6</span>:<span id=t_cns>0</span>] <span id=t_idt>TxAddrReg</span>; |
<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>TxEndPReg</span>; |
<span id=t_kwd>wire</span> [<span id=t_cns>10</span>:<span id=t_cns>0</span>] <span id=t_idt>frameNumIn</span>; |
<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPktStatusIn</span>; |
<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPIDIn</span>; |
<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>; |
|
<span id=t_kwd>wire</span> <span id=t_idt>SOFSentIn</span>; |
<span id=t_kwd>wire</span> <span id=t_idt>connEventIn</span>; |
<span id=t_kwd>wire</span> <span id=t_idt>resumeIntIn</span>; |
<span id=t_kwd>wire</span> <span id=t_idt>transDoneIn</span>; |
<span id=t_kwd>wire</span> <span id=t_idt>hostControlSelect</span>; |
<span id=t_kwd>wire</span> <span id=t_idt>clrTransReq</span>; |
<span id=t_kwd>reg</span> <span id=t_idt>preambleEn</span>; |
<span id=t_kwd>reg</span> <span id=t_idt>SOFSync</span>; |
<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxLineState</span>; |
<span id=t_kwd>reg</span> <span id=t_idt>LineDirectControlEn</span>; |
<span id=t_kwd>reg</span> <span id=t_idt>fullSpeedPol</span>; |
<span id=t_kwd>reg</span> <span id=t_idt>fullSpeedRate</span>; |
<span id=t_kwd>reg</span> <span id=t_idt>transReq</span>; |
|
<span id=t_com>//internal wire and regs</span> |
<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxControlReg</span>; |
<span id=t_kwd>reg</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>TxLineControlReg</span>; |
<span id=t_kwd>reg</span> <span id=t_idt>clrSOFReq</span>; |
<span id=t_kwd>reg</span> <span id=t_idt>clrConnEvtReq</span>; |
<span id=t_kwd>reg</span> <span id=t_idt>clrResInReq</span>; |
<span id=t_kwd>reg</span> <span id=t_idt>clrTransDoneReq</span>; |
<span id=t_kwd>reg</span> <span id=t_idt>SOFSentInt</span>; |
<span id=t_kwd>reg</span> <span id=t_idt>connEventInt</span>; |
<span id=t_kwd>reg</span> <span id=t_idt>resumeInt</span>; |
<span id=t_kwd>reg</span> <span id=t_idt>transDoneInt</span>; |
<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>interruptMaskReg</span>; |
<span id=t_kwd>reg</span> <span id=t_idt>setTransReq</span>; |
|
<span id=t_com>//sync write demux</span> |
<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>) |
<span id=t_kwd>begin</span> |
<span id=t_idt>clrSOFReq</span> <= <span id=t_cns>1'b0</span>; |
<span id=t_idt>clrConnEvtReq</span> <= <span id=t_cns>1'b0</span>; |
<span id=t_idt>clrResInReq</span> <= <span id=t_cns>1'b0</span>; |
<span id=t_idt>clrTransDoneReq</span> <= <span id=t_cns>1'b0</span>; |
<span id=t_idt>setTransReq</span> <= <span id=t_cns>1'b0</span>; |
<span id=t_kwd>if</span> (<span id=t_idt>writeEn</span> == <span id=t_cns>1'b1</span> && <span id=t_idt>strobe_i</span> == <span id=t_cns>1'b1</span> && <span id=t_idt>hostControlSelect</span> == <span id=t_cns>1'b1</span>) |
<span id=t_kwd>begin</span> |
<span id=t_kwd>case</span> (<span id=t_idt>address</span>) |
`<span id=t_idt>TX_CONTROL_REG</span> : <span id=t_kwd>begin</span> |
<span id=t_idt>preambleEn</span> <= <span id=t_idt>dataIn</span>[<span id=t_cns>2</span>]; |
<span id=t_idt>SOFSync</span> <= <span id=t_idt>dataIn</span>[<span id=t_cns>1</span>]; |
<span id=t_idt>setTransReq</span> <= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>]; |
<span id=t_kwd>end</span> |
`<span id=t_idt>TX_TRANS_TYPE_REG</span> : <span id=t_idt>TxTransTypeReg</span> <= <span id=t_idt>dataIn</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>]; |
`<span id=t_idt>TX_LINE_CONTROL_REG</span> : <span id=t_idt>TxLineControlReg</span> <= <span id=t_idt>dataIn</span>[<span id=t_cns>4</span>:<span id=t_cns>0</span>]; |
`<span id=t_idt>TX_SOF_ENABLE_REG</span> : <span id=t_idt>TxSOFEnableReg</span> <= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>]; |
`<span id=t_idt>TX_ADDR_REG</span> : <span id=t_idt>TxAddrReg</span> <= <span id=t_idt>dataIn</span>[<span id=t_cns>6</span>:<span id=t_cns>0</span>]; |
`<span id=t_idt>TX_ENDP_REG</span> : <span id=t_idt>TxEndPReg</span> <= <span id=t_idt>dataIn</span>[<span id=t_cns>3</span>:<span id=t_cns>0</span>]; |
`<span id=t_idt>INTERRUPT_STATUS_REG</span> : <span id=t_kwd>begin</span> |
<span id=t_idt>clrSOFReq</span> <= <span id=t_idt>dataIn</span>[<span id=t_cns>3</span>]; |
<span id=t_idt>clrConnEvtReq</span> <= <span id=t_idt>dataIn</span>[<span id=t_cns>2</span>]; |
<span id=t_idt>clrResInReq</span> <= <span id=t_idt>dataIn</span>[<span id=t_cns>1</span>]; |
<span id=t_idt>clrTransDoneReq</span> <= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>]; |
<span id=t_kwd>end</span> |
`<span id=t_idt>INTERRUPT_MASK_REG</span> : <span id=t_idt>interruptMaskReg</span> <= <span id=t_idt>dataIn</span>[<span id=t_cns>3</span>:<span id=t_cns>0</span>]; |
<span id=t_kwd>endcase</span> |
<span id=t_kwd>end</span> |
<span id=t_kwd>end</span> |
|
<span id=t_com>//interrupt control</span> |
<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>) |
<span id=t_kwd>begin</span> |
<span id=t_kwd>if</span> (<span id=t_idt>SOFSentIn</span> == <span id=t_cns>1'b1</span>) |
<span id=t_idt>SOFSentInt</span> <= <span id=t_cns>1'b1</span>; |
<span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrSOFReq</span> == <span id=t_cns>1'b1</span>) |
<span id=t_idt>SOFSentInt</span> <= <span id=t_cns>1'b0</span>; |
|
<span id=t_kwd>if</span> (<span id=t_idt>connEventIn</span> == <span id=t_cns>1'b1</span>) |
<span id=t_idt>connEventInt</span> <= <span id=t_cns>1'b1</span>; |
<span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrConnEvtReq</span> == <span id=t_cns>1'b1</span>) |
<span id=t_idt>connEventInt</span> <= <span id=t_cns>1'b0</span>; |
|
<span id=t_kwd>if</span> (<span id=t_idt>resumeIntIn</span> == <span id=t_cns>1'b1</span>) |
<span id=t_idt>resumeInt</span> <= <span id=t_cns>1'b1</span>; |
<span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrResInReq</span> == <span id=t_cns>1'b1</span>) |
<span id=t_idt>resumeInt</span> <= <span id=t_cns>1'b0</span>; |
|
<span id=t_kwd>if</span> (<span id=t_idt>transDoneIn</span> == <span id=t_cns>1'b1</span>) |
<span id=t_idt>transDoneInt</span> <= <span id=t_cns>1'b1</span>; |
<span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrTransDoneReq</span> == <span id=t_cns>1'b1</span>) |
<span id=t_idt>transDoneInt</span> <= <span id=t_cns>1'b0</span>; |
<span id=t_kwd>end</span> |
|
<span id=t_com>//mask interrupts</span> |
<span id=t_kwd>always</span> @(<span id=t_idt>interruptMaskReg</span> <span id=t_kwd>or</span> <span id=t_idt>transDoneInt</span> <span id=t_kwd>or</span> <span id=t_idt>resumeInt</span> <span id=t_kwd>or</span> <span id=t_idt>connEventInt</span> <span id=t_kwd>or</span> <span id=t_idt>SOFSentInt</span>) <span id=t_kwd>begin</span> |
<span id=t_idt>transDoneIntOut</span> <= <span id=t_idt>transDoneInt</span> & <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>TRANS_DONE_BIT</span>]; |
<span id=t_idt>resumeIntOut</span> <= <span id=t_idt>resumeInt</span> & <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>RESUME_INT_BIT</span>]; |
<span id=t_idt>connEventIntOut</span> <= <span id=t_idt>connEventInt</span> & <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>CONNECTION_EVENT_BIT</span>]; |
<span id=t_idt>SOFSentIntOut</span> <= <span id=t_idt>SOFSentInt</span> & <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>SOF_SENT_BIT</span>]; |
<span id=t_kwd>end</span> |
|
<span id=t_com>//transaction request set/clear</span> |
<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>) |
<span id=t_kwd>begin</span> |
<span id=t_kwd>if</span> (<span id=t_idt>setTransReq</span> == <span id=t_cns>1'b1</span>) |
<span id=t_idt>transReq</span> <= <span id=t_cns>1'b1</span>; |
<span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrTransReq</span> == <span id=t_cns>1'b1</span>) |
<span id=t_idt>transReq</span> <= <span id=t_cns>1'b0</span>; |
<span id=t_kwd>end</span> |
|
<span id=t_com>//break out control signals</span> |
<span id=t_kwd>always</span> @(<span id=t_idt>TxControlReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxLineControlReg</span>) <span id=t_kwd>begin</span> |
<span id=t_idt>TxLineState</span> <= <span id=t_idt>TxLineControlReg</span>[`<span id=t_idt>TX_LINE_STATE_MSBIT</span>:`<span id=t_idt>TX_LINE_STATE_LSBIT</span>]; |
<span id=t_idt>LineDirectControlEn</span> <= <span id=t_idt>TxLineControlReg</span>[`<span id=t_idt>DIRECT_CONTROL_BIT</span>]; |
<span id=t_idt>fullSpeedPol</span> <= <span id=t_idt>TxLineControlReg</span>[`<span id=t_idt>FULL_SPEED_LINE_POLARITY_BIT</span>]; |
<span id=t_idt>fullSpeedRate</span> <= <span id=t_idt>TxLineControlReg</span>[`<span id=t_idt>FULL_SPEED_LINE_RATE_BIT</span>]; |
<span id=t_kwd>end</span> |
|
<span id=t_com>// async read mux</span> |
<span id=t_kwd>always</span> @(<span id=t_idt>address</span> <span id=t_kwd>or</span> |
<span id=t_idt>TxControlReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxTransTypeReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxLineControlReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxSOFEnableReg</span> <span id=t_kwd>or</span> |
<span id=t_idt>TxAddrReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxEndPReg</span> <span id=t_kwd>or</span> <span id=t_idt>frameNumIn</span> <span id=t_kwd>or</span> |
<span id=t_idt>SOFSentInt</span> <span id=t_kwd>or</span> <span id=t_idt>connEventInt</span> <span id=t_kwd>or</span> <span id=t_idt>resumeInt</span> <span id=t_kwd>or</span> <span id=t_idt>transDoneInt</span> <span id=t_kwd>or</span> |
<span id=t_idt>interruptMaskReg</span> <span id=t_kwd>or</span> <span id=t_idt>RxPktStatusIn</span> <span id=t_kwd>or</span> <span id=t_idt>RxPIDIn</span> <span id=t_kwd>or</span> <span id=t_idt>connectStateIn</span> <span id=t_kwd>or</span> |
<span id=t_idt>preambleEn</span> <span id=t_kwd>or</span> <span id=t_idt>SOFSync</span> <span id=t_kwd>or</span> <span id=t_idt>transReq</span>) |
<span id=t_kwd>begin</span> |
<span id=t_kwd>case</span> (<span id=t_idt>address</span>) |
`<span id=t_idt>TX_CONTROL_REG</span> : <span id=t_idt>dataOut</span> <= {<span id=t_cns>5'b00000</span>, <span id=t_idt>preambleEn</span>, <span id=t_idt>SOFSync</span>, <span id=t_idt>transReq</span>} ; |
`<span id=t_idt>TX_TRANS_TYPE_REG</span> : <span id=t_idt>dataOut</span> <= {<span id=t_cns>6'b000000</span>, <span id=t_idt>TxTransTypeReg</span>}; |
`<span id=t_idt>TX_LINE_CONTROL_REG</span> : <span id=t_idt>dataOut</span> <= {<span id=t_cns>3'b000</span>, <span id=t_idt>TxLineControlReg</span>}; |
`<span id=t_idt>TX_SOF_ENABLE_REG</span> : <span id=t_idt>dataOut</span> <= {<span id=t_cns>7'b0000000</span>, <span id=t_idt>TxSOFEnableReg</span>}; |
`<span id=t_idt>TX_ADDR_REG</span> : <span id=t_idt>dataOut</span> <= {<span id=t_cns>1'b0</span>, <span id=t_idt>TxAddrReg</span>}; |
`<span id=t_idt>TX_ENDP_REG</span> : <span id=t_idt>dataOut</span> <= {<span id=t_cns>4'h0</span>, <span id=t_idt>TxEndPReg</span>}; |
`<span id=t_idt>FRAME_NUM_MSB_REG</span> : <span id=t_idt>dataOut</span> <= <span id=t_idt>frameNumIn</span>[<span id=t_cns>10</span>:<span id=t_cns>3</span>]; |
`<span id=t_idt>FRAME_NUM_LSB_REG</span> : <span id=t_idt>dataOut</span> <= {<span id=t_cns>5'b00000</span>, <span id=t_idt>frameNumIn</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>]}; |
`<span id=t_idt>INTERRUPT_STATUS_REG</span> : <span id=t_idt>dataOut</span> <= {<span id=t_cns>4'h0</span>, <span id=t_idt>SOFSentInt</span>, <span id=t_idt>connEventInt</span>, <span id=t_idt>resumeInt</span>, <span id=t_idt>transDoneInt</span>}; |
`<span id=t_idt>INTERRUPT_MASK_REG</span> : <span id=t_idt>dataOut</span> <= {<span id=t_cns>4'h0</span>, <span id=t_idt>interruptMaskReg</span>}; |
`<span id=t_idt>RX_STATUS_REG</span> : <span id=t_idt>dataOut</span> <= <span id=t_idt>RxPktStatusIn</span>; |
`<span id=t_idt>RX_PID_REG</span> : <span id=t_idt>dataOut</span> <= {<span id=t_cns>4'b0000</span>, <span id=t_idt>RxPIDIn</span>}; |
`<span id=t_idt>RX_CONNECT_STATE_REG</span> : <span id=t_idt>dataOut</span> <= {<span id=t_cns>6'b000000</span>, <span id=t_idt>connectStateIn</span>}; |
<span id=t_kwd>default</span>: <span id=t_idt>dataOut</span> <= <span id=t_cns>8'h00</span>; |
<span id=t_kwd>endcase</span> |
<span id=t_kwd>end</span> |
|
|
<span id=t_kwd>endmodule</span> |
</pre> |
</body> |
</html> |
tags/rel_00_06_alpha/doc/html/src/hostController/USBHostControlBI.v/index.htm
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: tags/rel_00_06_alpha/doc/src/USBHostSlave_IPCore_Specification.sxw
===================================================================
--- tags/rel_00_06_alpha/doc/src/USBHostSlave_IPCore_Specification.sxw (nonexistent)
+++ tags/rel_00_06_alpha/doc/src/USBHostSlave_IPCore_Specification.sxw (revision 13)
@@ -0,0 +1,347 @@
+PK lq92á¥19 mimetypeapplication/vnd.sun.xml.writerPK lq92 - Pictures/2000000F00001FD5000011164093EADD.svmÝ]»®$IA á±×XÐX¸¨$>€a±ƒU¸‹ÆY¤‘ w¥ú5Æ/k~¡L0ÇÆ›/()ˆ®ÊÌ8‘Y•U]}o÷fwÔG>âä9Ýó¸úê_ÿñ÷¯šß4KyÕü¢ÁòÊÚÙ4?jšŸñÅ?ùÖø篚‡³ÎþÁg?‰ýü=\—æ/|ñòîó˧&ÛËßøìûošæw_÷ÍRû·?nš_óÏÿ±};»õÓùþŸÿjüæÒ²ul=Ûn´l[Ï6²Q¨Ô²ul=ÛÈF¡aËÖ±õl#…ÎZ¶ŽgÙèrø[Ï6Ò2àåÕ±õl#'Z¶ŽgÙ(8Ö²ul=ÛÈFÁÙ–cëÙF6
+ Z¶ŽgÙ(€jÙ:¶žmd£ ôâÍåÕ³lÀ·l[Ï6²Q˜–cëÙF6
+“Ô²ul=ÛÈFaâZ¶ŽgÙ(LfËÖ±õl#… ngOúù5²Q˜ô–cëÙF6
+D´l[Ï6²Q §eëØz¶‘a-[ÇÖ³lHlÙ:¶žmd£@l;ÏÊ8{syQ »eëØz¶‘‚ Z¶ŽgÙ(ˆ¢eëØz¶‘‚PZ¶ŽgÙ(ˆ§eëØz¶‘hQK7ÏÍž\Ö²ul=ÛÈFAt-[ÇÖ³l„زul=ÛÈFAœ-[ÇÖ³lt¹Ç«³cëÙFºø)¾›§§Ëñu|7¯__Žoâ»yóær|ßÍÛ·—ã»ønÞ½»ßÇwóþýåø!¾›.ÇñÝ|üx9~ŠïæÓ§Ëñs|7Ÿ?ž×8……
+´˜/Ãtye=hÉáœx=»G·)ç0e^/àÙ¹ÅáLÀ2p_ÂÁ“ŠÅiÙû¡€58"}|!kœ«|=4XSœ/‚yP!+œ Ö&˜‡ãVá,Ã|x°ˆ3@Ñ.o‚y!#ÎàbÌ6s÷Îá“Öbî#Ùñ¹)¼Ç2à\\®cá Ø—åpî€)-EȚϜl7]|!gøTÏkÝ»w°>ñ18\ãÚý
+yOåˆvûÁ„,8çáŒS¥«
+ï¬àÌÈÖ:®ƒÛ5ÎÝŸ^¶àìrFZÌ©þ`öù¹]ãs‚|72Iù:´íÞË‚]ã3Á„ó\D¥/^p”r™ CÀa‚£>£J4
+ ·<è°×r›pFÙJ‡¸&꜀«á&céEø])Ï*däsE¶v+ÁÚZ‚I)¿åòLBv|â é¾r ŸÅcúäD,×ULÜlŸfÀ0¬ª1%>Cá5õM™Þv‚¹BÈ|š¡À]
++nË+L_·á6âa¦È§|¯WÀgê#¸j&À‚Ørët°§—ÝVtÒ5Lž4¹ Èõ¹8ž(dàÓg·ilâžås˜bäMm2|ªiªa׃=Âí*Ÿ>íS =Ÿªl§ûD‡mÝB¹ì
+ŸJ²éL?I.¨©Š×dÛádZUÛýB68§Ÿ˜"„ŸnC˜VI".m ×$v˜æSWÂ9ßpM2°ýç+[p[Ú+§Iõj'¦TvpædëÒLØe!‘“ø„]¢ {5ÈO}LžÛtOøÌɪ°AS²Hä—šv½ë„P$|N ‡š•»
+6´]åSwï¨
+Åt…Ù®^Í”¦A‡6Œägì¹
+*•CÐÒrOR"’šz¶Ô3àS‰<%x¦úœË¯ïKí5´™;Ÿ5ènU¦ˆµ0ìX×ô¶RÊ€uΕZ‘ê9öcúÛ+íšx*NT …|†ØÒ;©†i³¦Ÿqä,ce°é¬QÔÀÔ+T Mv›KI!2Ó…|ê´Ñ&CIÈJEšÏ:œ2H¼ŠðèA9œY—¡âÕ pBÐË)-¸bl ?ðY mElfžôÆB([熤׷ÝUDvÏRÇø, ]\¡à<ðœÛk=°BÒë;³fqOÖ`åY“.kÃP©‘erµ·e›á“pQä#7 3×$|^%[7Îj6ÔAÅ ƒû®osFÈêÚñy…l}Idç\È~m}*—¦S{r>ÜÂ&D¸¢{
+ˆîPØU!›V‘›ð©]ÓáÁ'¸Ò&/[typ"'/d›˜&>§>¯RÖ-“Tˆ£ùm%yéøôBVt!Ÿi³]ó´¸ï-0ë´<»Œ˜bMT£•âsS¶ ¾+³î§MVs²Íò™£!ÂŒ|ÖÊÖ£E¤hW“ ™<³ž=³ùX‰˜J>õðV® ›
+R.Á›
+ÝŸ÷ûÒ{%Ÿ¹¬]=Š”4ØRʦ‚Ñ#·ØëÀgMÊeÊÉ+€F‡–~då–ÓF†òWšÏ²%%18*Ð;!"Üriã”á3ú%Wèw °Ù%[Höq@*'°q=“Ù„P[Ú”ÃPŸÒ|fõqòœŸ‚ÐZ’\Ùö¼¯âSÒ³2ŸzŽ‘á+°ªUȆìÓ~Ÿ„Ó1è{øqI€Ò ëUzËE…ð,Ê-ä3F¹²;‰ä§²À>+‘¶‡kû©S‹Å|ÖËvHñ‹,Ì·Úë0Ûýñhq`ì¶â³ÛAø\—ˆë*>aE)‹#˜åœ±jáÜøê<_jWð ¼@]|¨°Ygǧ¬\µve¹J´TñIð‡¦Ÿ8èŸ[cwÉÆcñ\øœ¶øÙ&0”¸Aèú
+ŸÚÉkfÀâýħŠŠùN´K0s¸ð0LZÔá|ÊÌ8´¸¸[
+“á“Öø„x™Ÿ”ÎÜLbŠ&»_6Ñ>}ÕBßS%Ÿ"[-HäÓµŸ@¶¸f3Vï, y*øGÉâSÃ&%j%au—(£¿-y„Ï•Q3‘ø´)Ax–» À xŸ4ž‘ó|æ;Ä@Ü¢ÃR· -õ’L""=ïÆ™á³TfÕpâ.£›¶/Ãa?:Ø
+é ·ìöqÿ¬Hä…+ͧbIõNeƒVkÖäZ²ê«£lg>+¥¡%9¿²Ò2ÇHŠ,$½Å#\Ë–VN òþJÛ&!®FaÅŠøKÛŠK»UÍ4ne)H4Ù«ù”•¹Oj(#z··úm%¨“G»Á
+#™ZJ×6Ïç„
+ë÷RtÙ‘ˆÏ…!’ 'xºMIe÷Ÿ‚4OUÜÉJV™†òû¬4ÇågÅúV£`Â÷$éÏËðñn°äÖŠQîR-#[5%j|ðpZ²E/¨øçŸ~«6¯m¤jbòG»{:>A.}qiãº_J¶”þ¾I®ÑQnÁqÞºÎ,ŸÓ*M¯ô=aÿ>õ©`óÜÂZËd¼~%ãúžÌ]iUôÀòI¡šVG„¬v;ÙýT¯:Þ"_ñy¯“íæØøuùÿMÖÁøçuy¨ö‰NÕmš!µòy×ú¨¸¾kþÿ>Sá(X—Ž§`#½†ûÈ<®r»/¬¨e[ø'+À²o#ð0ïÁÉ(¤U|nà¼!X2µM«Á,CXó>÷€9$ä’Ãäšú“õ-w6¼®æÓ8snSßÐa¸öño¥Ëa ;p&‡n6³fãý\šAÛ}ÙîÄY æ€uÍz0Û”«?µ Žà\Ê…l¸à“jEogð™sè\°Ø›
+C.^—z8‰Ïœ['
+Å;À?çR}®zt&Ÿ¦ëU0þùÎo-LýµöÓ ²Û3qÊ çyŠ2ÄþöÈötœi˜Ûû«ÿPF·ÂéܺØrçàÊí„|/|b¹
+·ÅâÂÐsáœËóMa+ÝyNœK¹ÝZ¶/€s)7åvraèÅpÎåV`‡ûáÊéB5î‡O(ìáï‡$ÛûâÊBŽwõ³û¹”«„œêëIºGœs9 VÕ4-îçRÙ|Êã\Ê.nåÖxœsÙAúÏd4óƒs)›B–ZêΣá\Ê·¶ç\J`³¢~`œKYÙZ°<<ιl¯ÙÎ¥SAZ~áà\âoEÍýS9ƒ_‚Ú¼*ýÔ…ß]úPK(p¢4é šu PK lq92 - Pictures/200000070000AFCE0000FBDFB308A81C.wmfíÛ?n^E…ñëQ(ÒPÒ%û`_‹¡diBÏ
+`ˆÎ|öÖ§Û÷Ï™9çy~"…¿÷ÌÓr³¼^–Û·-ËÍòÏŸËÅW—_·7ß.__þþæÕ/øæþŸ¾{õ~y÷ð'~úþÇåÓåw~[>Þÿñå»w˧˟zùç¿ÿßúááßýúûÍòöÍòðë?w €l?/Ëú—ûÔö9áŒÏB"'ó¿!‘öz&$rÂv/†DNØbcHä„çí
+‰œð”!‘¾t8$rµ“!‘V’È ÂÈifòÈiNB"§Ù4
+‰œæÑ!$rš
+9AŽœ GNÐ"'h‘´È Bä-r‚9Aˆœ DN"'‘„È Bä!r‚9ÄûX–ÈÉ%çÉÈ©®ÀW#§r´O&|¸Ì«ð”!‘ÓlÚU$|»À“ð™>!‘Óðz†tþíOªHä4*Z"' WH'.óª™yC"§‘ØCŠm‰œv±WtòÕb›=¡óO–|Û<ìýHž,ù¶yØã)Ô9=ÏO–Èé)örT•áðìÙm‰œ¾dÏFøLUî•=›Ò-‘Ó5{6Õ["§Gölh‰œVölÆh‰œîÜûÔ9Ù÷©¥És²?XK3çd_~¼–¦ÍÉ>û-Í™“}sÕCØo&'ûà·DNö¿ÆøŠÒ9
+ó
+c|EÝœFz…1¾¢hNç¶O=Ò'ÔÍIr°}ça“ðZûÎÕ/ÓxÏQúøº9÷"EÏ®žS»;+nk£nNC¾KÅ›«ç4äÓÔº6çÛûìÖíÙÇ´Ç`_ Ãh!UÉÉuÞ ëÙ;‰Ä{^Ýݺ}N•YBn«2×vör:ï“v[Î%Bö~:5Æm-~zö„Ú{ØØìÉ_-ö°Ø+¾ZìaS±‡tþÕb›=¤3¯{ØÌì-xµØÃ`oi׫ņ•½¥¯{®Ù[Úòj±‡áš=¤-¯{®Ù+Úø^ùNÎ^Ñ®gªrç„ìx rÏÀþ(‡ßÅ~vÅ¢Ú}…ý-N~ˆýøEuøûH^Áþ ÉQõùûìÂåíU·±O-_Ûþ99uõ¼Ü¾j£aí•0HÏí£ wËü:ã =ï´&Ü͵gì&=Oµ/¦-dÕ¨Mì_Qq´ñ¶êcCuáI>3d®wþ£æ{í±¿.j+ ûö±_e(-ûò‰ì——X©û Ú‰ìÇ—X©û,´4FH+û8’¡ì—‡ïÓ}"Z#¤•}(Z#¤•}®Ã‹ÙÏΜūèbö·ÎœÅ®âhöçÜ$D¹Ýì/ž6H”ZÓÙ=j@…Ö³¿{αªhú•ØÐþú #”?£= û…„io€v ßÓ^!í’<©=BÚ+vU{„t@ì°ö*é€ÌmíaÒ1ÛÛ ¤ÃG¶BH‡îlï„K›Úž
+!‘6¸=B:#ms{6„tFÔìör館ñ;wBHr9-iïÙr'!ÉÍ“Ó‹?Kõ 3‹jIuÏÆÛI.-'ÕI[®"$¹´–Î_Õâl”™ÓÞÃÝ€½bszþÂÖ?Ç„·„ZÈ Bä!r‚9Aˆœ DN"'‘„È B's¢(\#'ω¢ðH’Ea¥Ê‰¢p—÷¿m¢4mNt5¹F9ÑÕœZçDiS!$„ B„!B‚!Aˆ DH"$„ B„!B‚!Aˆ DH"$„ àE·Ë½PKŠ¡£V $Î PK lq92Ï£€ï[ [ - Pictures/10000000000000200000002000309F1C.png‰PNG
+
+
+IHDR D¤ŠÆ PLTE € € €€€ € €€€ €€€ÀÀÀ ÿ ÿ ÿÿÿ ÿ ÿÿÿ ÿÿÿ 3 f ™ Ì ÿ 3 33 f3 ™3 Ì3 ÿ3 f 3f ff ™f Ìf ÿf ™ 3™ f™ ™™ Ì™ ÿ™ Ì 3Ì fÌ ™Ì ÌÌ ÿÌ ÿ 3ÿ fÿ ™ÿ Ìÿ ÿÿ 33 3f 3™ 3Ì 3ÿ 3 33333f33™33Ì33ÿ33 f33f3ff3™f3Ìf3ÿf3 ™33™3f™3™™3Ì™3ÿ™3 Ì33Ì3fÌ3™Ì3ÌÌ3ÿÌ3 ÿ33ÿ3fÿ3™ÿ3Ìÿ3ÿÿ3 f3 ff f™ fÌ fÿ f 3f33ff3f™3fÌ3fÿ3f ff3fffff™ffÌffÿff ™f3™ff™f™™fÌ™fÿ™f Ìf3ÌffÌf™ÌfÌÌfÿÌf ÿf3ÿffÿf™ÿfÌÿfÿÿf ™3 ™f ™™ ™Ì ™ÿ ™ 3™33™f3™™3™Ì3™ÿ3™ f™3f™ff™™f™Ìf™ÿf™ ™™3™™f™™™™™Ì™™ÿ™™ Ì™3Ì™fÌ™™Ì™ÌÌ™ÿÌ™ ÿ™3ÿ™fÿ™™ÿ™Ìÿ™ÿÿ™ Ì3 Ìf Ì™ ÌÌ Ìÿ Ì 3Ì33Ìf3Ì™3ÌÌ3Ìÿ3Ì fÌ3fÌffÌ™fÌÌfÌÿfÌ ™Ì3™Ìf™Ì™™ÌÌ™Ìÿ™Ì ÌÌ3ÌÌfÌÌ™ÌÌÌÌÌÿÌÌ ÿÌ3ÿÌfÿÌ™ÿÌÌÿÌÿÿÌ ÿ3 ÿf ÿ™ ÿÌ ÿÿ ÿ 3ÿ33ÿf3ÿ™3ÿÌ3ÿÿ3ÿ fÿ3fÿffÿ™fÿÌfÿÿfÿ ™ÿ3™ÿf™ÿ™™ÿÌ™ÿÿ™ÿ Ìÿ3ÌÿfÌÿ™ÌÿÌÌÿÿÌÿ ÿÿ3ÿÿfÿÿ™ÿÿÌÿÿÿÿÿ ¸ÿ ¸ÒO IDATxœcà' FŒ*U0R ËU<4àð IEND®B`‚PK lq92ºÂ´’– – layout-cache p’ F € @ ¨ P P P š P § P ± F à Ë( À } P º F 6 :% ç&