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Rev 12 → Rev 13

/trunk/csm.vhd File deleted
/trunk/csm_pb.vhd
0,0 → 1,171
--
-- Wishbone compliant cycle shared memory, priority based selection
-- author: Richard Herveille
--
-- rev.: 1.0 july 12th, 2001. Initial release
--
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
entity csm_pb is
generic(
DWIDTH : natural := 32; -- databus width
AWIDTH : natural := 8 -- addressbus width
);
port(
-- SYSCON signals
CLK_I : in std_logic; -- wishbone clock input
RST_I : in std_logic; -- synchronous active high reset
nRESET : in std_logic; -- asynchronous active low reset
 
-- wishbone slave0 connections
ADR0_I : in unsigned(AWIDTH -1 downto 0); -- address input
DAT0_I : in std_logic_vector(DWIDTH -1 downto 0); -- data input
DAT0_O : out std_logic_vector(DWIDTH -1 downto 0); -- data output
SEL0_I : in std_logic_vector( (DWIDTH/8) -1 downto 0); -- byte select input
WE0_I : in std_logic; -- write enable input
STB0_I : in std_logic; -- strobe input
CYC0_I : in std_logic; -- valid bus cycle input
ACK0_O : out std_logic; -- acknowledge output
ERR0_O : out std_logic; -- error output
 
-- wishbone slave1 connections
ADR1_I : in unsigned(AWIDTH -1 downto 0); -- address input
DAT1_I : in std_logic_vector(DWIDTH -1 downto 0); -- data input
DAT1_O : out std_logic_vector(DWIDTH -1 downto 0); -- data output
SEL1_I : in std_logic_vector( (DWIDTH/8) -1 downto 0); -- byte select input
WE1_I : in std_logic; -- write enable input
STB1_I : in std_logic; -- strobe input
CYC1_I : in std_logic; -- valid bus cycle input
ACK1_O : out std_logic; -- acknowledge output
ERR1_O : out std_logic -- error output
);
end entity csm_pb;
 
architecture structural of csm_pb is
-- function declarations
function "and"(L: std_logic_vector; R : std_logic) return std_logic_vector is
variable tmp : std_logic_vector(L'range);
begin
for n in L'range loop
tmp(n) := L(n) and R;
end loop;
return tmp;
end function "and";
 
function "and"(L: std_logic; R : std_logic_vector) return std_logic_vector is
begin
return (R and L);
end function "and";
 
-- define memory array
type mem_array is array(2**AWIDTH -1 downto 0) of std_logic_vector(DWIDTH -1 downto 0);
signal mem : mem_array;
 
-- multiplexor select signal
signal wb0_acc, dwb0_acc : std_logic;
signal wb1_acc, dwb1_acc : std_logic;
signal sel_wb0 : std_logic;
signal sel_wb1 : std_logic;
signal ack0_pipe, ack1_pipe : std_logic_vector(3 downto 0);
-- multiplexed memory busses / signals
signal mem_adr, mem_radr : unsigned(AWIDTH -1 downto 0);
signal mem_dati, mem_dato : std_logic_vector(DWIDTH -1 downto 0);
signal mem_we : std_logic;
 
-- acknowledge generation
signal wb0_ack, wb1_ack : std_logic;
 
-- error signal generation
signal err0, err1 : std_logic_vector( (DWIDTH/8) -1 downto 0);
 
begin
-- generate multiplexor select signal
wb0_acc <= CYC0_I and STB0_I;
wb1_acc <= CYC1_I and STB1_I and not sel_wb0;
 
process(CLK_I)
begin
if (CLK_I'event and CLK_I = '1') then
dwb0_acc <= wb0_acc and not wb0_ack;
dwb1_acc <= wb1_acc and not wb1_ack;
end if;
end process;
 
sel_wb0 <= wb0_acc and not dwb0_acc;
sel_wb1 <= wb1_acc and not dwb1_acc;
 
gen_ack_pipe: process(CLK_I, nRESET)
begin
if (nRESET = '0') then
ack0_pipe <= (others => '0');
ack1_pipe <= (others => '0');
elsif (CLK_I'event and CLK_I = '1') then
if (RST_I = '1') then
ack0_pipe <= (others => '0');
ack1_pipe <= (others => '0');
else
ack0_pipe <= (ack0_pipe(2 downto 0) & sel_wb0) and not wb0_ack;
ack1_pipe <= (ack1_pipe(2 downto 0) & sel_wb1) and not wb1_ack;
end if;
end if;
end process gen_ack_pipe;
 
-- multiplex memory bus
gen_muxs: process(CLK_I)
begin
if (CLK_I'event and CLK_I = '1') then
if (sel_wb0 = '1') then
mem_adr <= adr0_i;
mem_dati <= dat0_i;
mem_we <= we0_i and cyc0_i and stb0_i and not wb0_ack;
else
mem_adr <= adr1_i;
mem_dati <= dat1_i;
mem_we <= we1_i and cyc1_i and stb1_i and not wb1_ack;
end if;
end if;
end process gen_muxs;
 
-- memory access
gen_mem: process(CLK_I)
begin
if (CLK_I'event and CLK_I = '1') then
-- write operation
if (mem_we = '1') then
mem(conv_integer(mem_adr)) <= mem_dati;
end if;
 
-- read operation
mem_radr <= mem_adr; -- FLEX RAMs require address to be registered with inclock for read operation.
mem_dato <= mem(conv_integer(mem_radr));
end if;
end process gen_mem;
 
-- assign DAT_O outputs
DAT1_O <= mem_dato;
DAT0_O <= mem_dato;
 
-- assign ACK_O outputs
gen_ack: process(CLK_I)
begin
if (CLK_I'event and CLK_I = '1') then
wb0_ack <= ( (sel_wb0 and WE0_I) or (ack0_pipe(1)) ) and not wb0_ack;
wb1_ack <= ( (sel_wb1 and WE1_I) or (ack1_pipe(1)) ) and not wb1_ack;
end if;
end process gen_ack;
-- ACK outputs
ACK0_O <= wb0_ack;
ACK1_O <= wb1_ack;
 
-- ERR outputs
err0 <= (others => '1');
ERR0_O <= '1' when ( (SEL0_I /= err0) and (CYC0_I = '1') and (STB0_I = '1') ) else '0';
 
err1 <= (others => '1');
ERR1_O <= '1' when ( (SEL1_I /= err1) and (CYC1_I = '1') and (STB1_I = '1') ) else '0';
end architecture;
/trunk/vga_and_clut_tstbench.vhd
23,7 → 23,6
component vga_and_clut is
port(
CLK_I : in std_logic; -- wishbone clock input
CLKx2_I : in std_logic; -- 2X wishbone clock input (double frequency)
RST_I : in std_logic; -- synchronous active high reset
NRESET : in std_logic := '1'; -- asynchronous active low reset
INTA_O : out std_logic; -- interrupt request output
100,7 → 99,7
--
 
-- clock & reset
signal clk_x2, clk, vga_clk : std_logic := '0';
signal clk, vga_clk : std_logic := '0';
signal rst : std_logic := '1';
signal init : std_logic := '0';
 
126,12 → 125,9
-- generate clocks
clk_block: block
begin
process(clk_x2)
process(clk)
begin
clk_x2 <= not clk_x2 after 1.25 ns; -- 400MHz clock
if (clk_x2 = '1') then
clk <= not clk; -- 200MHz wishbone clock
end if;
clk <= not clk after 2.5 ns; -- 200MHz wishbone clock
end process;
 
process(vga_clk)
152,7 → 148,7
--
-- hookup vga + clut core
--
u1: vga_and_clut port map (CLK_I => clk, CLKx2_I => clk_x2, RST_I => RST, ADR_I => h_adr_o(9 downto 2),
u1: vga_and_clut port map (CLK_I => clk, RST_I => RST, ADR_I => h_adr_o(9 downto 2),
SDAT_I => h_dat_o, SDAT_O => h_dat_i, SEL_I => h_sel_o, WE_I => h_we_o, VGA_STB_I => h_adr_o(31),
CLUT_STB_I => h_adr_o(30), CYC_I => h_cyc_o, ACK_O => h_ack_i, ERR_O => h_err_i,
ADR_O => vga_adr_o, MDAT_I => vga_dat_i, SEL_O => vga_sel_o, WE_O => vga_we_o, STB_O => vga_stb_o,
265,7 → 261,7
-- program vga controller
(x"80000008",'1',x"04090018","1111",'0'), --32 program horizontal timing register
(x"8000000c",'1',x"05010002","1111",'0'), -- program vertical timing register
(x"80000010",'1',x"00640064","1111",'0'), -- program horizontal/vertical length register (100x100 pixels)
(x"80000010",'1',x"00320032","1111",'0'), -- program horizontal/vertical length register (50x50 pixels)
(x"80000014",'1',x"10000000","1111",'0'), -- program video base address 0 register (sdram)
(x"8000001c",'1',x"10200000","1111",'0'), -- program color lookup table (sram)
(x"80000000",'1',x"00000901","1111",'0'), -- program control register (enable video system)
412,6 → 408,3
ack_o <= my_ack;
end architecture behavioral;
 
 
 
 
/trunk/vga_and_clut.vhd
3,8 → 3,8
-- project: VGA/LCD controller + Color Lookup Table
-- author: Richard Herveille
--
-- rev 1.0 July 4th, 2001.
--
-- rev. 1.0 July 4th, 2001.
-- rev. 1.1 July 15th, 2001. Changed cycle_shared_memory to csm_pb. The core does not require a CLKx2 clock anymore.
 
library ieee;
use ieee.std_logic_1164.all;
13,7 → 13,6
entity vga_and_clut is
port(
CLK_I : in std_logic; -- wishbone clock input
CLKx2_I : in std_logic; -- 2X wishbone clock input (double frequency)
RST_I : in std_logic; -- synchronous active high reset
NRESET : in std_logic; -- asynchronous active low reset
INTA_O : out std_logic; -- interrupt request output
94,7 → 93,7
);
end component vga;
 
component cycle_shared_mem is
component csm_pb is
generic(
DWIDTH : natural := 32; -- databus width
AWIDTH : natural := 8 -- addressbus width
101,7 → 100,6
);
port(
-- SYSCON signals
CLKx2_I : in std_logic; -- memory clock, 2x wishbone clock
CLK_I : in std_logic; -- wishbone clock input
RST_I : in std_logic; -- synchronous active high reset
nRESET : in std_logic; -- asynchronous active low reset
128,7 → 126,7
ACK1_O : out std_logic; -- acknowledge output
ERR1_O : out std_logic -- error output
);
end component cycle_shared_mem;
end component csm_pb;
 
--
-- Signal declarations
182,9 → 180,9
-- hookup cycle shared memory
--
empty_data <= (others => '0');
u2: cycle_shared_mem
u2: csm_pb
generic map (DWIDTH => 24, AWIDTH => 8)
port map (CLKx2_I => CLKx2_I, CLK_I => CLK_I, RST_I => RST_I, nRESET => nReset,
port map (CLK_I => CLK_I, RST_I => RST_I, nRESET => nReset,
ADR0_I => vga_adr_o(9 downto 2), DAT0_I => empty_data, DAT0_O => mem0_dat_o, SEL0_I => vga_sel_o(2 downto 0),
WE0_I => vga_we_o, STB0_I => vga_stb_o, CYC0_I => vga_cyc_o, ACK0_O => mem0_ack_o, ERR0_O => mem0_err_o,
ADR1_I => ADR_I(9 downto 2), DAT1_I => SDAT_I(23 downto 0), DAT1_O => mem1_dat_o, SEL1_I => SEL_I(2 downto 0),
195,7 → 193,7
--
 
-- wishbone master
CYC_O <= vga_cyc_o;
CYC_O <= '0' when (vga_clut_acc = '1') else vga_cyc_o;
STB_O <= '0' when (vga_clut_acc = '1') else vga_stb_o;
ADR_O <= vga_adr_o;
SEL_O <= vga_sel_o;
212,4 → 210,3
end architecture structural;
 
 
 

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