URL
https://opencores.org/ocsvn/video_systems/video_systems/trunk
Subversion Repositories video_systems
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- This comparison shows the changes necessary to convert path
/
- from Rev 12 to Rev 13
- ↔ Reverse comparison
Rev 12 → Rev 13
/trunk/common/qnr/rtl/verilog/div.v
File deleted
/trunk/common/qnr/rtl/verilog/div_us.v
File deleted
/trunk/common/qnr/rtl/verilog/div_uu.v
1,6 → 1,6
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Non-restoring unsinged dividor //// |
//// Non-restoring unsinged divider //// |
//// //// |
//// Author: Richard Herveille //// |
//// richard@asics.ws //// |
34,10 → 34,10
|
// CVS Log |
// |
// $Id: div_uu.v,v 1.2 2002-10-23 09:07:03 rherveille Exp $ |
// $Id: div_uu.v,v 1.3 2002-10-31 12:52:55 rherveille Exp $ |
// |
// $Date: 2002-10-23 09:07:03 $ |
// $Revision: 1.2 $ |
// $Date: 2002-10-31 12:52:55 $ |
// $Revision: 1.3 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
44,6 → 44,12
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2002/10/23 09:07:03 rherveille |
// Improved many files. |
// Fixed some bugs in Run-Length-Encoder. |
// Removed dependency on ud_cnt and ro_cnt. |
// Started (Motion)JPEG hardware encoder project. |
// |
|
//synopsys translate_off |
`include "timescale.v" |
113,7 → 119,7
// |
// variables |
// |
reg [d_width -1:0] q_pipe [d_width:0]; |
reg [d_width-1:0] q_pipe [d_width-1:0]; |
reg [z_width:0] s_pipe [d_width:0]; |
reg [z_width:0] d_pipe [d_width:0]; |
|
151,6 → 157,9
|
// generate quotient pipe |
always @(posedge clk) |
q_pipe[0] <= #1 0; |
|
always @(posedge clk) |
if(ena) |
for(n2=1; n2 < d_width; n2=n2+1) |
q_pipe[n2] <= #1 gen_q(q_pipe[n2-1], s_pipe[n2]); |
/trunk/common/qnr/rtl/verilog/jpeg_qnr.v
34,10 → 34,10
|
// CVS Log |
// |
// $Id: jpeg_qnr.v,v 1.2 2002-10-23 09:07:03 rherveille Exp $ |
// $Id: jpeg_qnr.v,v 1.3 2002-10-31 12:52:55 rherveille Exp $ |
// |
// $Date: 2002-10-23 09:07:03 $ |
// $Revision: 1.2 $ |
// $Date: 2002-10-31 12:52:55 $ |
// $Revision: 1.3 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
44,8 → 44,16
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2002/10/23 09:07:03 rherveille |
// Improved many files. |
// Fixed some bugs in Run-Length-Encoder. |
// Removed dependency on ud_cnt and ro_cnt. |
// Started (Motion)JPEG hardware encoder project. |
// |
|
`timescale 1ns/10ps |
//synopsys translate_off |
`include "timescale.v" |
//synopsys translate_on |
|
module jpeg_qnr(clk, ena, rst, dstrb, din, qnt_val, qnt_cnt, dout, douten); |
|
/trunk/common/qnr/rtl/verilog/div_su.v
35,10 → 35,10
|
// CVS Log |
// |
// $Id: div_su.v,v 1.2 2002-10-23 09:07:03 rherveille Exp $ |
// $Id: div_su.v,v 1.3 2002-10-31 12:52:54 rherveille Exp $ |
// |
// $Date: 2002-10-23 09:07:03 $ |
// $Revision: 1.2 $ |
// $Date: 2002-10-31 12:52:54 $ |
// $Revision: 1.3 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
45,6 → 45,12
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2002/10/23 09:07:03 rherveille |
// Improved many files. |
// Fixed some bugs in Run-Length-Encoder. |
// Removed dependency on ud_cnt and ro_cnt. |
// Started (Motion)JPEG hardware encoder project. |
// |
|
//synopsys translate_off |
`include "timescale.v" |
61,18 → 67,19
// |
// inputs & outputs |
// |
input clk; // system clock |
input ena; // clock enable |
input clk; // system clock |
input ena; // clock enable |
|
input [z_width -1:0] z; // divident |
input [d_width -1:0] d; // divisor |
output [d_width :0] q; // quotient |
input [z_width-1:0] z; // divident |
input [d_width-1:0] d; // divisor |
output [d_width :0] q; // quotient |
output [d_width-1:0] s; // remainder |
output div0; |
output ovf; |
|
reg [d_width :0] q; |
output [d_width -1:0] s; // remainder |
reg [d_width :0] s; |
output div0; |
reg [d_width-1:0] s; |
reg div0; |
output ovf; |
reg ovf; |
|
// |
/trunk/common/jpeg/rtl/verilog/jpeg_encoder.v
34,10 → 34,10
|
// CVS Log |
// |
// $Id: jpeg_encoder.v,v 1.2 2002-10-23 18:58:51 rherveille Exp $ |
// $Id: jpeg_encoder.v,v 1.3 2002-10-31 12:51:44 rherveille Exp $ |
// |
// $Date: 2002-10-23 18:58:51 $ |
// $Revision: 1.2 $ |
// $Date: 2002-10-31 12:51:44 $ |
// $Revision: 1.3 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
44,6 → 44,9
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2002/10/23 18:58:51 rherveille |
// Fixed a bug in the zero-run (run-length-coder) |
// |
// Revision 1.1 2002/10/23 09:07:01 rherveille |
// Improved many files. |
// Fixed some bugs in Run-Length-Encoder. |
51,8 → 54,9
// Started (Motion)JPEG hardware encoder project. |
// |
|
|
//synopsys translate_off |
`include "timescale.v" |
//synopsys translate_on |
|
module jpeg_encoder( |
clk, |
/trunk/common/run_length_coding/rtl/verilog/jpeg_rzs.v
37,10 → 37,10
|
// CVS Log |
// |
// $Id: jpeg_rzs.v,v 1.3 2002-10-23 18:58:54 rherveille Exp $ |
// $Id: jpeg_rzs.v,v 1.4 2002-10-31 12:53:39 rherveille Exp $ |
// |
// $Date: 2002-10-23 18:58:54 $ |
// $Revision: 1.3 $ |
// $Date: 2002-10-31 12:53:39 $ |
// $Revision: 1.4 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 47,9
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2002/10/23 18:58:54 rherveille |
// Fixed a bug in the zero-run (run-length-coder) |
// |
// Revision 1.2 2002/10/23 09:07:04 rherveille |
// Improved many files. |
// Fixed some bugs in Run-Length-Encoder. |
54,14 → 57,17
// Started (Motion)JPEG hardware encoder project. |
// |
|
`timescale 1ns/10ps |
//synopsys translate_off |
`include "timescale.v" |
//synopsys translate_on |
|
module jpeg_rzs(clk, rst, deni, dci, rleni, sizei, ampi, deno, dco, rleno, sizeo, ampo); |
module jpeg_rzs(clk, ena, rst, deni, dci, rleni, sizei, ampi, deno, dco, rleno, sizeo, ampo); |
|
// |
// inputs & outputs |
// |
input clk; |
input ena; |
input rst; |
input deni; |
input dci; |
/trunk/common/run_length_coding/rtl/verilog/jpeg_rle.v
38,10 → 38,10
|
// CVS Log |
// |
// $Id: jpeg_rle.v,v 1.3 2002-10-23 18:58:54 rherveille Exp $ |
// $Id: jpeg_rle.v,v 1.4 2002-10-31 12:53:39 rherveille Exp $ |
// |
// $Date: 2002-10-23 18:58:54 $ |
// $Revision: 1.3 $ |
// $Date: 2002-10-31 12:53:39 $ |
// $Revision: 1.4 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
48,6 → 48,9
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2002/10/23 18:58:54 rherveille |
// Fixed a bug in the zero-run (run-length-coder) |
// |
// Revision 1.2 2002/10/23 09:07:04 rherveille |
// Improved many files. |
// Fixed some bugs in Run-Length-Encoder. |
55,7 → 58,9
// Started (Motion)JPEG hardware encoder project. |
// |
|
`timescale 1ns/10ps |
//synopsys translate_off |
`include "timescale.v" |
//synopsys translate_on |
|
module jpeg_rle(clk, rst, ena, dstrb, din, size, rlen, amp, douten, bstart); |
|
117,6 → 122,7
jpeg_rzs rz1( |
.clk(clk), |
.rst(rst), |
.ena(ena), |
.rleni(rle_rlen), |
.sizei(rle_size), |
.ampi(rle_amp), |
133,6 → 139,7
jpeg_rzs rz2( |
.clk(clk), |
.rst(rst), |
.ena(ena), |
.rleni(rz1_rlen), |
.sizei(rz1_size), |
.ampi(rz1_amp), |
149,6 → 156,7
jpeg_rzs rz3( |
.clk(clk), |
.rst(rst), |
.ena(ena), |
.rleni(rz2_rlen), |
.sizei(rz2_size), |
.ampi(rz2_amp), |
165,6 → 173,7
jpeg_rzs rz4( |
.clk(clk), |
.rst(rst), |
.ena(ena), |
.rleni(rz3_rlen), |
.sizei(rz3_size), |
.ampi(rz3_amp), |
/trunk/common/run_length_coding/rtl/verilog/jpeg_rle1.v
39,10 → 39,10
|
// CVS Log |
// |
// $Id: jpeg_rle1.v,v 1.3 2002-10-23 18:58:54 rherveille Exp $ |
// $Id: jpeg_rle1.v,v 1.4 2002-10-31 12:53:39 rherveille Exp $ |
// |
// $Date: 2002-10-23 18:58:54 $ |
// $Revision: 1.3 $ |
// $Date: 2002-10-31 12:53:39 $ |
// $Revision: 1.4 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
49,6 → 49,9
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2002/10/23 18:58:54 rherveille |
// Fixed a bug in the zero-run (run-length-coder) |
// |
// Revision 1.2 2002/10/23 09:07:04 rherveille |
// Improved many files. |
// Fixed some bugs in Run-Length-Encoder. |
56,7 → 59,9
// Started (Motion)JPEG hardware encoder project. |
// |
|
`timescale 1ns/10ps |
//synopsys translate_off |
`include "timescale.v" |
//synopsys translate_on |
|
module jpeg_rle1(clk, rst, ena, go, din, rlen, size, amp, den, dcterm); |
|
67,14 → 72,14
// |
// inputs & outputs |
// |
input clk; // system clock |
input rst; // asynchronous reset |
input ena; // clock enable |
input clk; // system clock |
input rst; // asynchronous reset |
input ena; // clock enable |
input go; |
input [11:0] din; // data input |
|
output [ 3:0] rlen; // run-length |
output [ 3:0] size; // size |
output [ 3:0] size; // size (or category) |
output [11:0] amp; // amplitude |
output den; // data output enable |
output dcterm; // DC-term (start of new block) |
91,8 → 96,6
reg [3:0] zero_cnt; |
wire is_zero; |
|
wire [3:0] sizeof_din; |
|
reg state; |
parameter dc = 1'b0; |
parameter ac = 1'b1; |
101,7 → 104,11
// module body |
// |
|
// |
// function declarations |
// |
|
// Function abs; absolute value |
function [10:0] abs; |
input [11:0] a; |
begin |
112,41 → 119,72
end |
endfunction |
|
function [3:0] sizef; |
// Function cat, calculates category for Din |
function [3:0] cat; |
input [11:0] a; |
reg [10:0] tmp; |
begin |
// get absolute value |
tmp = abs(a); |
// get absolute value |
tmp = abs(a); |
|
// determine size |
casex (tmp) // synopsys full_case parallel_case |
11'b1??_????_???? : sizef = 4'hb; // 1024..2047 |
11'b01?_????_???? : sizef = 4'ha; // 512..1023 |
11'b001_????_???? : sizef = 4'h9; // 256.. 511 |
11'b000_1???_???? : sizef = 4'h8; // 128.. 255 |
11'b000_01??_???? : sizef = 4'h7; // 64.. 127 |
11'b000_001?_???? : sizef = 4'h6; // 32.. 63 |
11'b000_0001_???? : sizef = 4'h5; // 16.. 31 |
11'b000_0000_1??? : sizef = 4'h4; // 8.. 15 |
11'b000_0000_01?? : sizef = 4'h3; // 4.. 7 |
11'b000_0000_001? : sizef = 4'h2; // 2.. 3 |
11'b000_0000_0001 : sizef = 4'h1; // 1 |
default : sizef = 4'h0; // 0 (DC only) |
endcase |
// determine category |
casex(tmp) // synopsys full_case parallel_case |
11'b1??_????_???? : cat = 4'hb; // 1024..2047 |
11'b01?_????_???? : cat = 4'ha; // 512..1023 |
11'b001_????_???? : cat = 4'h9; // 256.. 511 |
11'b000_1???_???? : cat = 4'h8; // 128.. 255 |
11'b000_01??_???? : cat = 4'h7; // 64.. 127 |
11'b000_001?_???? : cat = 4'h6; // 32.. 63 |
11'b000_0001_???? : cat = 4'h5; // 16.. 31 |
11'b000_0000_1??? : cat = 4'h4; // 8.. 15 |
11'b000_0000_01?? : cat = 4'h3; // 4.. 7 |
11'b000_0000_001? : cat = 4'h2; // 2.. 3 |
11'b000_0000_0001 : cat = 4'h1; // 1 |
11'b000_0000_0000 : cat = 4'h0; // 0 (DC only) |
endcase |
end |
endfunction |
|
|
// Function modamp, calculate additional bits per category |
function [10:0] rem; |
input [11:0] a; |
reg [10:0] tmp, tmp_rem; |
begin |
tmp_rem = a[11] ? (a[10:0] - 10'h1) : a[10:0]; |
|
if(0) |
begin |
// get absolute value |
tmp = abs(a); |
|
casex(tmp) // synopsys full_case parallel_case |
11'b1??_????_???? : rem = tmp_rem & 11'b111_1111_1111; |
11'b01?_????_???? : rem = tmp_rem & 11'b011_1111_1111; |
11'b001_????_???? : rem = tmp_rem & 11'b001_1111_1111; |
11'b000_1???_???? : rem = tmp_rem & 11'b000_1111_1111; |
11'b000_01??_???? : rem = tmp_rem & 11'b000_0111_1111; |
11'b000_001?_???? : rem = tmp_rem & 11'b000_0011_1111; |
11'b000_0001_???? : rem = tmp_rem & 11'b000_0001_1111; |
11'b000_0000_1??? : rem = tmp_rem & 11'b000_0000_1111; |
11'b000_0000_01?? : rem = tmp_rem & 11'b000_0000_0111; |
11'b000_0000_001? : rem = tmp_rem & 11'b000_0000_0011; |
11'b000_0000_0001 : rem = tmp_rem & 11'b000_0000_0001; |
11'b000_0000_0000 : rem = tmp_rem & 11'b000_0000_0000; |
endcase |
end |
else |
rem = tmp_rem; |
end |
endfunction |
|
// detect zero |
assign is_zero = ~|din; |
|
// hookup sizef function |
assign sizeof_din = sizef(din); |
|
// assign dout |
always @(posedge clk) |
if (ena) |
amp <= #1 din; |
amp <= #1 rem(din); |
|
// generate sample counter |
always @(posedge clk) |
177,25 → 215,24
else if (ena) |
case (state) // synopsys full_case parallel_case |
dc: |
if(go) |
begin |
state <= #1 ac; |
begin |
rlen <= #1 0; |
size <= #1 cat(din); |
|
rlen <= #1 0; |
size <= #1 sizeof_din; |
den <= #1 1'b1; |
dcterm <= #1 1'b1; |
end |
else |
begin |
state <= #1 dc; |
if(go) |
begin |
state <= #1 ac; |
den <= #1 1'b1; |
dcterm <= #1 1'b1; |
end |
else |
begin |
state <= #1 dc; |
den <= #1 1'b0; |
dcterm <= #1 1'b0; |
end |
end |
|
rlen <= #1 0; |
size <= #1 0; |
den <= #1 1'b0; |
dcterm <= #1 1'b0; |
end |
|
ac: |
if(&sample_cnt) // finished current block |
begin |
211,7 → 248,7
else |
begin |
rlen <= #1 zero_cnt; |
size <= #1 sizeof_din; |
size <= #1 cat(din); |
den <= #1 1'b1; |
dcterm <= #1 1'b0; |
end |
218,31 → 255,20
end |
else |
begin |
state <= #1 ac; |
state <= #1 ac; |
|
rlen <= #1 zero_cnt; |
dcterm <= #1 1'b0; |
|
if (is_zero) |
begin |
if (&zero_cnt) |
begin |
rlen <= #1 zero_cnt; |
size <= #1 0; |
den <= #1 1'b1; |
dcterm <= #1 1'b0; |
end |
else |
begin |
rlen <= #1 zero_cnt; |
size <= #1 0; |
den <= #1 1'b0; |
dcterm <= #1 1'b0; |
end |
size <= #1 0; |
den <= #1 &zero_cnt; |
end |
else |
begin |
rlen <= #1 zero_cnt; |
size <= #1 sizeof_din; |
size <= #1 cat(din); |
den <= #1 1'b1; |
dcterm <= #1 1'b0; |
end |
end |
endcase |
/trunk/common/dct/rtl/verilog/dctu.v
34,10 → 34,10
|
// CVS Log |
// |
// $Id: dctu.v,v 1.2 2002-10-23 09:06:59 rherveille Exp $ |
// $Id: dctu.v,v 1.3 2002-10-31 12:50:03 rherveille Exp $ |
// |
// $Date: 2002-10-23 09:06:59 $ |
// $Revision: 1.2 $ |
// $Date: 2002-10-31 12:50:03 $ |
// $Revision: 1.3 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
44,9 → 44,17
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2002/10/23 09:06:59 rherveille |
// Improved many files. |
// Fixed some bugs in Run-Length-Encoder. |
// Removed dependency on ud_cnt and ro_cnt. |
// Started (Motion)JPEG hardware encoder project. |
// |
|
|
//synopsys translate_off |
`include "timescale.v" |
//synopsys translate_on |
|
module dctu(clk, ena, ddgo, x, y, ddin, dout); |
|
/trunk/common/dct/rtl/verilog/fdct.v
34,10 → 34,10
|
// CVS Log |
// |
// $Id: fdct.v,v 1.2 2002-10-23 09:06:59 rherveille Exp $ |
// $Id: fdct.v,v 1.3 2002-10-31 12:50:03 rherveille Exp $ |
// |
// $Date: 2002-10-23 09:06:59 $ |
// $Revision: 1.2 $ |
// $Date: 2002-10-31 12:50:03 $ |
// $Revision: 1.3 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
44,9 → 44,17
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2002/10/23 09:06:59 rherveille |
// Improved many files. |
// Fixed some bugs in Run-Length-Encoder. |
// Removed dependency on ud_cnt and ro_cnt. |
// Started (Motion)JPEG hardware encoder project. |
// |
|
|
//synopsys translate_off |
`include "timescale.v" |
//synopsys translate_on |
|
module fdct(clk, ena, rst, dstrb, din, dout, douten); |
|
/trunk/common/dct/rtl/verilog/dctub.v
34,10 → 34,10
|
// CVS Log |
// |
// $Id: dctub.v,v 1.2 2002-10-23 09:06:59 rherveille Exp $ |
// $Id: dctub.v,v 1.3 2002-10-31 12:50:03 rherveille Exp $ |
// |
// $Date: 2002-10-23 09:06:59 $ |
// $Revision: 1.2 $ |
// $Date: 2002-10-31 12:50:03 $ |
// $Revision: 1.3 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
44,9 → 44,17
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2002/10/23 09:06:59 rherveille |
// Improved many files. |
// Fixed some bugs in Run-Length-Encoder. |
// Removed dependency on ud_cnt and ro_cnt. |
// Started (Motion)JPEG hardware encoder project. |
// |
|
|
//synopsys translate_off |
`include "timescale.v" |
//synopsys translate_on |
|
module dctub(clk, ena, ddgo, x, y, ddin, |
dout0, dout1, dout2, dout3, dout4, dout5, dout6, dout7); |
/trunk/common/dct/rtl/verilog/dct_syn.v
1,92 → 1,95
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Discrete Cosine Transform Synthesis Test //// |
//// //// |
//// Author: Richard Herveille //// |
//// richard@asics.ws //// |
//// www.asics.ws //// |
//// //// |
//// Synthesis results: //// |
//// Device: Altera EP20K400EBC652-1x, 50MHz clk area optimized //// |
//// 12bit coeff.: 15957lcells(96%), 17440membits(8%), 76MHz //// //// |
//// 11bit coeff.: 15327lcells(92%), 15456membits(7%), 76MHz //// |
//// //// |
//// //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2002 Richard Herveille //// |
//// richard@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// |
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// |
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// |
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// |
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// |
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// |
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// |
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// |
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// |
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// |
//// POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
|
// CVS Log |
// |
// $Id: dct_syn.v,v 1.2 2002-10-23 09:06:59 rherveille Exp $ |
// |
// $Date: 2002-10-23 09:06:59 $ |
// $Revision: 1.2 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
|
module dct_syn(clk, ena, rst, dstrb, din, dout, den); |
|
input clk; |
input ena; |
input rst; |
|
input dstrb; |
input [7:0] din; |
|
output [11:0] dout; |
output den; |
|
// |
// DCT unit |
// |
|
// As little as 11bits coefficients can be used while |
// all errors remain in the decimal bit range (dout[0]) |
// total errors = 5(14bit resolution) |
// = 12(13bit resolution) |
// = 26(12bit resolution) |
// = 54(11bit resolution) |
fdct #(9) dut ( |
.clk(clk), |
.ena(1'b1), |
.rst(rst), |
.dstrb(dstrb), |
.din(din), |
.dout(dout), |
.douten(den) |
); |
|
endmodule |
//// //// |
//// Discrete Cosine Transform Synthesis Test //// |
//// //// |
//// Author: Richard Herveille //// |
//// richard@asics.ws //// |
//// www.asics.ws //// |
//// //// |
//// Synthesis results: //// |
//// //// |
//// //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2002 Richard Herveille //// |
//// richard@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// |
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// |
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// |
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// |
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// |
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// |
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// |
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// |
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// |
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// |
//// POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
|
// CVS Log |
// |
// $Id: dct_syn.v,v 1.3 2002-10-31 12:50:03 rherveille Exp $ |
// |
// $Date: 2002-10-31 12:50:03 $ |
// $Revision: 1.3 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2002/10/23 09:06:59 rherveille |
// Improved many files. |
// Fixed some bugs in Run-Length-Encoder. |
// Removed dependency on ud_cnt and ro_cnt. |
// Started (Motion)JPEG hardware encoder project. |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
|
module dct_syn(clk, ena, rst, dstrb, din, dout, den); |
|
input clk; |
input ena; |
input rst; |
|
input dstrb; |
input [7:0] din; |
|
output [11:0] dout; |
output den; |
|
// |
// DCT unit |
// |
|
// As little as 11bits coefficients can be used while |
// all errors remain in the decimal bit range (dout[0]) |
// total errors = 5(14bit resolution) |
// = 12(13bit resolution) |
// = 26(12bit resolution) |
// = 54(11bit resolution) |
fdct #(13) dut ( |
.clk(clk), |
.ena(1'b1), |
.rst(rst), |
.dstrb(dstrb), |
.din(din), |
.dout(dout), |
.douten(den) |
); |
|
endmodule |
/trunk/common/dct/rtl/verilog/dct.v
34,10 → 34,10
|
// CVS Log |
// |
// $Id: dct.v,v 1.2 2002-10-23 09:06:59 rherveille Exp $ |
// $Id: dct.v,v 1.3 2002-10-31 12:50:03 rherveille Exp $ |
// |
// $Date: 2002-10-23 09:06:59 $ |
// $Revision: 1.2 $ |
// $Date: 2002-10-31 12:50:03 $ |
// $Revision: 1.3 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
44,8 → 44,16
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2002/10/23 09:06:59 rherveille |
// Improved many files. |
// Fixed some bugs in Run-Length-Encoder. |
// Removed dependency on ud_cnt and ro_cnt. |
// Started (Motion)JPEG hardware encoder project. |
// |
|
//synopsys translate_off |
`include "timescale.v" |
//synopsys translate_on |
|
module dct( |
clk, |
126,6 → 134,9
if (~rst) |
begin |
go <= #1 1'b0; |
dgo <= #1 1'b0; |
ddgo <= #1 1'b0; |
ddin <= #1 0; |
|
douten <= #1 1'b0; |
ddcnt <= #1 1'b1; |
/trunk/common/dct/rtl/verilog/dct_mac.v
36,10 → 36,10
|
// CVS Log |
// |
// $Id: dct_mac.v,v 1.2 2002-10-23 09:06:59 rherveille Exp $ |
// $Id: dct_mac.v,v 1.3 2002-10-31 12:50:03 rherveille Exp $ |
// |
// $Date: 2002-10-23 09:06:59 $ |
// $Revision: 1.2 $ |
// $Date: 2002-10-31 12:50:03 $ |
// $Revision: 1.3 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
46,8 → 46,16
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2002/10/23 09:06:59 rherveille |
// Improved many files. |
// Fixed some bugs in Run-Length-Encoder. |
// Removed dependency on ud_cnt and ro_cnt. |
// Started (Motion)JPEG hardware encoder project. |
// |
|
//synopsys translate_off |
`include "timescale.v" |
//synopsys translate_on |
|
module dct_mac(clk, ena, dclr, din, coef, result); |
|