URL
https://opencores.org/ocsvn/zet86/zet86/trunk
Subversion Repositories zet86
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 12 to Rev 13
- ↔ Reverse comparison
Rev 12 → Rev 13
/trunk/impl/virtex4-ml403ep/memory/mem_map_step.v
0,0 → 1,494
// |
// Memory map test. It testes all kind of memory accesses in |
// different RAM / ROM / video areas. RAM contents at the end: |
// |
// Mem[01:00] = xx34 |
// Mem[03:02] = 1234 |
// Mem[05:04] = Mem[09:08] |
// Mem[07:06] = 0a0b |
// Mem[0d:0c] = 12xx |
// Mem[0f:0e] = xxMem[08] |
// Mem[11:10] = ff83 |
// Mem[13:12] = 0034 |
// Mem[15:14] = 0062 |
// Mem[17:16] = ext(Mem[09]) |
// Mem[19:18] = Mem[09]xx |
// Mem[1b:1a] = 0b06 |
// Mem[1d:1c] = Mem[08]12 |
// Mem[1f:1e] = 0365 |
// |
// In the screen: Aet erotessor ... (first & second 'e' yellow |
// and fist 'o' yellow) |
// |
|
module mem_map_test ( |
input sys_clk_in_, |
|
output sram_clk_, |
output [20:0] sram_flash_addr_, |
inout [15:0] sram_flash_data_, |
output sram_flash_oe_n_, |
output sram_flash_we_n_, |
output [ 3:0] sram_bw_, |
output sram_cen_, |
output flash_ce2_, |
|
output tft_lcd_clk_, |
output tft_lcd_r_, |
output tft_lcd_g_, |
output tft_lcd_b_, |
output tft_lcd_hsync_, |
output tft_lcd_vsync_, |
|
output rs_, |
output rw_, |
output e_, |
output [7:4] db_, |
|
input bot_c_, |
input bot_r_ |
); |
|
// Net declarations |
wire rst; |
wire clk; |
wire [15:0] dada_ent; |
wire ack; |
wire clk_100M; |
wire [63:0] f1, f2; |
wire [15:0] m1, m2; |
|
// Register declarations |
reg [ 7:0] estat; |
reg [15:0] dada_sor; |
reg [15:0] dada1; |
reg [15:0] dada2; |
reg [19:0] adr; |
reg we; |
reg stb; |
reg byte_o; |
|
// Module instantiations |
clock c0 ( |
.sys_clk_in_ (sys_clk_in_), |
.clk (clk), |
.clk_100M (clk_100M), |
.vdu_clk (tft_lcd_clk_), |
.rst (rst) |
); |
|
mem_map mem_map0 ( |
// Wishbone signals |
.clk_i (clk), |
.rst_i (rst), |
.adr_i (adr), |
.dat_i (dada_sor), |
.dat_o (dada_ent), |
.we_i (we), |
.ack_o (ack), |
.stb_i (stb), |
.byte_i (byte_o), |
|
// Pad signals |
.sram_clk_ (sram_clk_), |
.sram_flash_addr_ (sram_flash_addr_), |
.sram_flash_data_ (sram_flash_data_), |
.sram_flash_oe_n_ (sram_flash_oe_n_), |
.sram_flash_we_n_ (sram_flash_we_n_), |
.sram_bw_ (sram_bw_), |
.sram_cen_ (sram_cen_), |
.flash_ce2_ (flash_ce2_), |
|
// VGA pad signals |
.vdu_clk (tft_lcd_clk_), |
.vga_red_o (tft_lcd_r_), |
.vga_green_o (tft_lcd_g_), |
.vga_blue_o (tft_lcd_b_), |
.horiz_sync (tft_lcd_hsync_), |
.vert_sync (tft_lcd_vsync_) |
); |
|
lcd_display lcd0 ( |
.f1 (f1), // 1st row |
.f2 (f2), // 2nd row |
.m1 (m1), // 1st row mask |
.m2 (m2), // 2nd row mask |
|
.clk (clk_100M), // 100 Mhz clock |
|
// Pad signals |
.lcd_rs_ (rs_), |
.lcd_rw_ (rw_), |
.lcd_e_ (e_), |
.lcd_dat_ (db_) |
); |
|
// Continuous assignments |
assign f1 = { estat, 4'h0, dada_sor, 4'h0, dada1, dada2 }; |
assign f2 = { adr, 7'h0, we, 7'h0, stb, 7'h0, byte_o, 4'h0, dada_ent }; |
assign m1 = 16'b1101111011111111; |
assign m2 = 16'b1111101010101111; |
|
|
// Behavioral description |
always @(posedge clk) |
if (rst) |
begin |
estat <= 8'h00; |
dada_sor <= 16'd0; |
dada1 <= 16'h1234; |
dada2 <= 16'h6789; |
adr <= 21'hc0002; |
we <= 1'd0; |
stb <= 1'd0; |
byte_o <= 1'd0; |
end |
else |
case (estat) |
8'h00: |
begin // ROM word read (dada2 = 0a0b) |
estat <= 8'h01; |
dada_sor <= dada_sor; |
dada1 <= dada1; |
dada2 <= dada2; |
adr <= 20'hc0004; |
we <= 1'd0; |
stb <= 1'd1; |
byte_o <= 1'd0; |
end |
8'h01: |
if (ack) begin |
estat <= 8'h05; |
stb <= 1'b0; |
dada2 <= dada_ent; |
end |
8'h05: |
if (bot_c_) begin // RAM word read (@4) |
estat <= 8'h06; |
dada_sor <= dada_sor; |
dada1 <= dada1; |
dada2 <= dada2; |
adr <= 20'h8; |
we <= 1'd0; |
stb <= 1'd1; |
byte_o <= 1'd0; |
end |
8'h06: |
if (ack) begin |
estat <= 8'h10; |
stb <= 1'b0; |
dada_sor <= dada_ent; |
end |
8'h10: |
if (bot_r_) begin // RAM write (@2 = @4) |
estat <= 8'h11; |
dada_sor <= dada_sor; |
dada1 <= dada1; |
dada2 <= dada2; |
adr <= 20'h4; |
we <= 1'd1; |
stb <= 1'd1; |
byte_o <= 1'd0; |
end |
8'h11: |
if (ack) begin |
estat <= 8'h15; |
stb <= 1'b0; |
we <= 1'b0; |
end |
8'h15: |
if (bot_c_) begin // RAM write (@3 = 0a0b) |
estat <= 8'h16; |
dada_sor <= dada2; |
dada1 <= dada1; |
dada2 <= dada2; |
adr <= 20'h6; |
we <= 1'd1; |
stb <= 1'd1; |
byte_o <= 1'd0; |
end |
8'h16: |
if (ack) begin |
estat <= 8'h20; |
stb <= 1'b0; |
we <= 1'b0; |
end |
8'h20: |
if (bot_r_) begin // RAM write (@1 = 1234) |
estat <= 8'h25; |
dada_sor <= dada1; |
dada1 <= dada1; |
dada2 <= dada2; |
adr <= 20'h2; |
we <= 1'd1; |
stb <= 1'd1; |
byte_o <= 1'd0; |
end |
8'h25: |
if (ack) begin // ROM read byte (83) |
estat <= 8'h30; |
dada_sor <= dada_sor; |
dada1 <= dada1; |
dada2 <= dada2; |
adr <= 20'hc0040; |
we <= 1'd0; |
stb <= 1'd1; |
byte_o <= 1'd1; |
end |
8'h30: |
if (ack) begin // RAM word write (@8 = ff83) |
estat <= 8'h35; |
dada_sor <= dada_ent; |
dada1 <= dada1; |
dada2 <= dada2; |
adr <= 20'h10; |
we <= 1'd1; |
stb <= 1'd1; |
byte_o <= 1'd0; |
end |
8'h35: |
if (ack) begin // RAM byte read (07) |
estat <= 8'h40; |
dada_sor <= dada_sor; |
dada1 <= dada1; |
dada2 <= dada2; |
adr <= 20'h2; |
we <= 1'd0; |
stb <= 1'd1; |
byte_o <= 1'd1; |
end |
8'h40: |
if (ack) begin // RAM word write (@9 = 0034) |
estat <= 8'h45; |
dada_sor <= dada_ent; |
dada1 <= dada1; |
dada2 <= dada2; |
adr <= 20'h12; |
we <= 1'd1; |
stb <= 1'd1; |
byte_o <= 1'd0; |
end |
8'h45: |
if (ack) begin // RAM byte write (@0 = 34) |
estat <= 8'h50; |
dada_sor <= dada_sor; |
dada1 <= dada1; |
dada2 <= dada2; |
adr <= 20'h0; |
we <= 1'd1; |
stb <= 1'd1; |
byte_o <= 1'd1; |
end |
8'h50: |
if (ack) begin // ROM read byte odd (62) |
estat <= 8'h55; |
dada_sor <= dada_sor; |
dada1 <= dada1; |
dada2 <= dada2; |
adr <= 20'hc0031; |
we <= 1'd0; |
stb <= 1'd1; |
byte_o <= 1'd1; |
end |
8'h55: |
if (ack) begin // RAM word write (@10 = 0062) |
estat <= 8'h60; |
dada_sor <= dada_ent; |
dada1 <= dada1; |
dada2 <= dada2; |
adr <= 20'h14; |
we <= 1'd1; |
stb <= 1'd1; |
byte_o <= 1'd0; |
end |
8'h60: |
if (ack) begin // RAM byte read odd (8c) |
estat <= 8'h65; |
dada_sor <= dada_sor; |
dada1 <= dada1; |
dada2 <= dada2; |
adr <= 20'h9; |
we <= 1'd0; |
stb <= 1'd1; |
byte_o <= 1'd1; |
end |
8'h65: |
if (ack) begin // RAM word write (@11 = ff8c) |
estat <= 8'h70; |
dada_sor <= dada_ent; |
dada1 <= dada1; |
dada2 <= dada2; |
adr <= 20'h16; |
we <= 1'd1; |
stb <= 1'd1; |
byte_o <= 1'd0; |
end |
8'h70: |
if (ack) begin // RAM byte write odd (@12 = 8cxx) |
estat <= 8'h75; |
dada_sor <= dada_sor; |
dada1 <= dada1; |
dada2 <= dada2; |
adr <= 20'h19; |
we <= 1'd1; |
stb <= 1'd1; |
byte_o <= 1'd1; |
end |
8'h75: |
if (ack) begin // ROM word read odd (0b06) |
estat <= 8'h80; |
dada_sor <= dada_sor; |
dada1 <= dada1; |
dada2 <= dada2; |
adr <= 20'hc0003; |
we <= 1'd0; |
stb <= 1'd1; |
byte_o <= 1'd0; |
end |
8'h80: |
if (ack) begin // RAM word write (@13 = 0b06) |
estat <= 8'h85; |
dada_sor <= dada_ent; |
dada1 <= dada1; |
dada2 <= dada2; |
adr <= 20'h1a; |
we <= 1'd1; |
stb <= 1'd1; |
byte_o <= 1'd0; |
end |
8'h85: |
if (ack) begin // RAM word read (odd) |
estat <= 8'h90; |
dada_sor <= dada_sor; |
dada1 <= dada1; |
dada2 <= dada2; |
adr <= 20'h3; |
we <= 1'd0; |
stb <= 1'd1; |
byte_o <= 1'd0; |
end |
8'h90: |
if (ack) begin // RAM word write (even) |
estat <= 8'h95; |
dada_sor <= dada_ent; |
dada1 <= dada_ent; |
dada2 <= dada2; |
adr <= 20'h1c; |
we <= 1'd1; |
stb <= 1'd1; |
byte_o <= 1'd0; |
end |
8'h95: |
if (ack) begin // RAM word write (odd) |
estat <= 8'h96; |
dada_sor <= dada1; |
dada1 <= dada1; |
dada2 <= dada2; |
adr <= 20'd13; |
we <= 1'd1; |
stb <= 1'd1; |
byte_o <= 1'd0; |
end |
8'h96: |
if (ack) begin |
estat <= 8'ha0; |
stb <= 1'b0; |
we <= 1'b0; |
end |
|
// Video test |
8'ha0: |
if (bot_c_) begin // byte write even / A |
estat <= 8'ha1; |
dada_sor <= 16'h41; |
dada1 <= dada1; |
dada2 <= dada2; |
adr <= 20'hb8000; |
we <= 1'd1; |
stb <= 1'd1; |
byte_o <= 1'd1; |
end |
8'ha1: |
if (ack) begin |
estat <= 8'ha5; |
stb <= 1'b0; |
we <= 1'b0; |
end |
8'ha5: |
if (bot_r_) begin // byte write odd (attr) yellow (e) |
estat <= 8'hb0; |
dada_sor <= 16'h03; |
dada1 <= dada1; |
dada2 <= dada2; |
adr <= 20'hb8003; |
we <= 1'd1; |
stb <= 1'd1; |
byte_o <= 1'd1; |
end |
8'hb0: |
if (ack) begin // word read (even) - yellow e |
estat <= 8'hb5; |
dada_sor <= dada_sor; |
dada1 <= dada1; |
dada2 <= dada2; |
adr <= 20'hb8002; |
we <= 1'd0; |
stb <= 1'd1; |
byte_o <= 1'd0; |
end |
8'hb5: |
if (ack) begin // word write (even) RAM @7 = 0365 |
estat <= 8'hc0; |
dada_sor <= dada_ent; |
dada1 <= dada_ent; |
dada2 <= dada_ent; |
adr <= 20'h1e; |
we <= 1'd1; |
stb <= 1'd1; |
byte_o <= 1'd0; |
end |
8'hc0: // word write (even) yellow e in |
// place of the p of processor |
if (ack) begin |
estat <= 8'hc5; |
dada_sor <= dada1; |
dada1 <= dada1; |
dada2 <= dada2; |
adr <= 20'hb8008; |
we <= 1'd1; |
stb <= 1'd1; |
byte_o <= 1'd0; |
end |
8'hc5: |
if (ack) begin // word read (odd) 7403 't' yellow |
estat <= 8'hd0; |
dada_sor <= dada_sor; |
dada1 <= dada1; |
dada2 <= dada2; |
adr <= 20'hb8003; // b8009 |
we <= 1'd0; |
stb <= 1'd1; |
byte_o <= 1'd0; |
end |
8'hd0: |
if (ack) begin // word write (odd) |
// This changes the color attribute of the |
// 'o' in "processor" and writes a 't' in place |
// of the 'o' |
estat <= 8'hd5; |
dada_sor <= dada_ent; |
dada1 <= dada_ent; |
dada2 <= dada2; |
adr <= 20'hb800d; |
we <= 1'd1; |
stb <= 1'd1; |
byte_o <= 1'd0; |
end |
8'hd5: |
if (ack) begin |
estat <= 8'he0; |
we <= 1'b0; |
stb <= 1'b0; |
end |
endcase |
endmodule |
/trunk/impl/virtex4-ml403ep/memory/ml403-with-but.ucf
0,0 → 1,115
NET sys_clk_in_ TNM_NET = "sys_clk_in_"; |
TIMESPEC "TSSYSCLK" = PERIOD "sys_clk_in_" 9.9 ns HIGH 50 %; |
|
NET sys_clk_in_ LOC = AE14; |
NET sys_clk_in_ IOSTANDARD = LVCMOS33; |
|
#NET trx LOC = W1; |
NET sram_clk_ LOC = AF7 ; |
|
#NET sram_flash_addr_[24] LOC = T21; |
#NET sram_flash_addr_[23] LOC = U20; |
#NET sram_flash_addr_[22] LOC = T19; |
NET sram_flash_addr_[20] LOC = AC5; |
NET sram_flash_addr_[19] LOC = AB5; |
NET sram_flash_addr_[18] LOC = AC4; |
NET sram_flash_addr_[17] LOC = AB4; |
NET sram_flash_addr_[16] LOC = AB3; |
NET sram_flash_addr_[15] LOC = AA4; |
NET sram_flash_addr_[14] LOC = AA3; |
NET sram_flash_addr_[13] LOC = W5; |
NET sram_flash_addr_[12] LOC = W6; |
NET sram_flash_addr_[11] LOC = W3; |
NET sram_flash_addr_[10] LOC = AF3; |
NET sram_flash_addr_[9] LOC = AE3; |
NET sram_flash_addr_[8] LOC = AD2; |
NET sram_flash_addr_[7] LOC = AD1; |
NET sram_flash_addr_[6] LOC = AC2; |
NET sram_flash_addr_[5] LOC = AC1; |
NET sram_flash_addr_[4] LOC = AB2; |
NET sram_flash_addr_[3] LOC = AB1; |
NET sram_flash_addr_[2] LOC = AA1; |
NET sram_flash_addr_[1] LOC = Y2; |
NET sram_flash_addr_[0] LOC = Y1; |
#NET sram_flash_addr_[0] LOC = T20; |
|
NET sram_flash_data_[15] LOC = AA14; |
NET sram_flash_data_[14] LOC = AB14; |
NET sram_flash_data_[13] LOC = AC12; |
NET sram_flash_data_[12] LOC = AC11; |
NET sram_flash_data_[11] LOC = AA16; |
NET sram_flash_data_[10] LOC = AA15; |
NET sram_flash_data_[9] LOC = AB13; |
NET sram_flash_data_[8] LOC = AA13; |
NET sram_flash_data_[7] LOC = AC14; |
NET sram_flash_data_[6] LOC = AD14; |
NET sram_flash_data_[5] LOC = AA12; |
NET sram_flash_data_[4] LOC = AA11; |
NET sram_flash_data_[3] LOC = AC16; |
NET sram_flash_data_[2] LOC = AC15; |
NET sram_flash_data_[1] LOC = AC13; |
NET sram_flash_data_[0] LOC = AD13; |
|
NET sram_flash_oe_n_ LOC = AC6; |
NET sram_flash_we_n_ LOC = AB6; |
|
NET sram_bw_[3] LOC = Y3; #Y4; |
NET sram_bw_[2] LOC = Y4; #Y3; |
NET sram_bw_[1] LOC = Y5; #Y6; |
NET sram_bw_[0] LOC = Y6; #Y5; |
|
NET sram_cen_ LOC = V7; |
|
NET flash_ce2_ LOC = W7; |
|
#NET flash_byte_n LOC = N22; |
#NET flash_audio_reset_n LOC = AD10; |
|
NET tft_lcd_clk_ LOC = AF8; |
NET tft_lcd_r_ LOC = E6; # VGA_R7 |
NET tft_lcd_g_ LOC = C1; # VGA_G7 |
NET tft_lcd_b_ LOC = F8; # VGA_B7 |
NET tft_lcd_hsync_ LOC = C10; |
NET tft_lcd_vsync_ LOC = A8; |
|
NET tft_lcd_clk_ SLEW = FAST; |
NET tft_lcd_clk_ DRIVE = 8; |
|
NET tft_lcd_r_ SLEW = FAST; |
NET tft_lcd_r_ DRIVE = 8; |
|
NET tft_lcd_g_ SLEW = FAST; |
NET tft_lcd_g_ DRIVE = 8; |
|
NET tft_lcd_b_ SLEW = FAST; |
NET tft_lcd_b_ DRIVE = 8; |
|
NET tft_lcd_hsync_ SLEW = FAST; |
NET tft_lcd_hsync_ DRIVE = 8; |
|
NET tft_lcd_vsync_ SLEW = FAST; |
NET tft_lcd_vsync_ DRIVE = 8; |
|
NET e_ LOC = AE13 | IOSTANDARD = LVCMOS33 | TIG; # LCD_E |
NET rs_ LOC = AC17 | IOSTANDARD = LVCMOS33 | TIG; # LCD_RS |
NET rw_ LOC = AB17 | IOSTANDARD = LVCMOS33 | TIG; # LCD_RW |
|
NET db_[7] LOC = AF12 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB7 |
NET db_[6] LOC = AE12 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB6 |
NET db_[5] LOC = AC10 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB5 |
NET db_[4] LOC = AB10 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB4 |
|
NET bot_c_ LOC = B6; # C Button |
NET bot_r_ LOC = F10; # E Button |
|
#NET leds_[0] LOC = G5; #GPLED0 |
#NET leds_[1] LOC = G6; #GPLED1 |
#NET leds_[2] LOC = A11; #GPLED2 |
#NET leds_[3] LOC = A12; #GPLED3 |
|
# North-East-South-West-Center LEDs |
#NET leds_[4] LOC = C6; # C LED |
#NET leds_[5] LOC = F9; # W LED |
#NET leds_[6] LOC = A5; # S LED |
#NET leds_[7] LOC = E10; # E LED |
#NET leds_[8] LOC = E2; # N LED |
/trunk/impl/virtex4-ml403ep/memory/README
12,3 → 12,5
* ../../spartan3an-sk/rtl/vga/ram2k_b16.v |
* ../../spartan3an-sk/rtl/vga/vdu.v |
|
And to execute it step by step, substitute in the project the files |
mem_map_test.v by mem_map_step.v and ml403-with-tft.ucf by ml403-with-but.ucf |