OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

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    from Rev 121 to Rev 122
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Rev 121 → Rev 122

/trunk/bench/verilog/system.v
39,6 → 39,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.19 2003/08/21 21:00:38 tadejm
// Added support for WB B3. Some testcases were updated.
//
// Revision 1.18 2003/08/03 18:04:44 mihad
// Added limited WISHBONE B3 support for WISHBONE Slave Unit.
// Doesn't support full speed bursts yet.
191,11 → 194,11
wire reset_wb ; // reset to Wb devices
 
`ifdef PCI_BIST
wire scanb_so ;
reg scanb_si ;
reg scanb_rst ;
reg scanb_en ;
reg scanb_clk ;
wire mbist_so_o ;
reg mbist_si_i ;
reg mbist_rst ;
reg mbist_en_i ;
reg mbist_clk ;
`endif
 
wire RST ;
269,11 → 272,9
`ifdef PCI_BIST
,
// bist chain signals
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_so),
.scanb_en (scanb_en)
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i ({mbist_en_i, mbist_clk, mbist_rst})
`endif
) ;
 
704,10 → 705,10
begin
 
`ifdef PCI_BIST
scanb_si = 0 ;
scanb_en = 0 ;
scanb_clk = 0 ;
scanb_rst = 0 ;
mbist_si_i = 0 ;
mbist_ctrl_i = 0 ;
mbist_clk = 0 ;
mbist_rst = 0 ;
`endif
next_test_name[79:0] <= "Nowhere___";
reset = 1'b1 ;
909,7 → 910,7
// if BIST is implemented, give it a go
`ifdef PCI_BIST
run_bist_test ;
scanb_rst <= #1 1'b1 ;
mbist_rst <= #1 1'b1 ;
`endif
test_initial_conf_values ;
 
19688,10 → 19689,10
 
test_name = "BIST FOR RAMS RUN" ;
 
scanb_en = 0 ;
scanb_si = 0 ;
scanb_rst = 0 ;
scanb_clk = 0 ;
mbist_ctrl_i = 0 ;
mbist_si_i = 0 ;
mbist_rst = 0 ;
mbist_clk = 0 ;
 
fork
begin
19705,14 → 19706,14
join
 
// test is run by reseting the test logic
scanb_rst <= 1'b1 ;
mbist_rst <= 1'b1 ;
// toggle scan clock for a few times
repeat (20)
#50 scanb_clk = !scanb_clk ;
#50 mbist_clk = !mbist_clk ;
// release bist reset
scanb_rst <= 1'b0 ;
mbist_rst <= 1'b0 ;
 
bist_result_vector = 0 ;
 
19722,19 → 19723,19
while (bist_result_vector !== {bist_chain_length{1'b1}})
begin
#1 ;
@(posedge scanb_clk) ;
scanb_en <= #1 1'b1 ;
@(posedge mbist_clk) ;
mbist_ctrl_i <= #1 1'b1 ;
for (count = 0 ; count < bist_chain_length ; count = count + 1'b1)
begin
@(posedge scanb_clk) ;
bist_result_vector[count] = scanb_so ;
@(posedge mbist_clk) ;
bist_result_vector[count] = mbist_so_o ;
end
 
scanb_en <= #1 1'b0 ;
mbist_ctrl_i <= #1 1'b0 ;
end
#1 disable deadlock ;
@(negedge scanb_clk) ;
#1 disable scanb_clk_gen ;
@(negedge mbist_clk) ;
#1 disable mbist_clk_gen ;
test_ok ;
end
begin:deadlock
19745,15 → 19746,15
end
 
test_fail("BIST Test didn't finish as expected") ;
scanb_en <= #1 1'b0 ;
mbist_ctrl_i <= #1 1'b0 ;
disable scan ;
@(negedge scanb_clk) ;
@(negedge mbist_clk) ;
#1 ;
disable scanb_clk_gen ;
disable mbist_clk_gen ;
end
begin:scanb_clk_gen
begin:mbist_clk_gen
forever
#50 scanb_clk = !scanb_clk ;
#50 mbist_clk = !mbist_clk ;
end
join
end
/trunk/rtl/verilog/pci_bridge32.v
43,6 → 43,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.12 2003/08/21 20:49:03 tadejm
// Added signals for WB Master B3.
//
// Revision 1.11 2003/08/08 16:36:33 tadejm
// Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.
//
57,7 → 60,7
// Changed BIST signal names etc..
//
// Revision 1.7 2002/10/18 03:36:37 tadejm
// Changed wrong signal name scanb_sen into scanb_en.
// Changed wrong signal name mbist_sen into mbist_ctrl_i.
//
// Revision 1.6 2002/10/17 22:51:50 tadejm
// Changed BIST signals for RAMs.
200,11 → 203,9
`ifdef PCI_BIST
,
// debug chain signals
scanb_rst, // bist scan reset
scanb_clk, // bist scan clock
scanb_si, // bist scan serial in
scanb_so, // bist scan serial out
scanb_en // bist scan shift enable
mbist_si_i, // bist scan serial in
mbist_so_o, // bist scan serial out
mbist_ctrl_i // bist chain shift control
`endif
);
 
318,11 → 319,9
/*-----------------------------------------------------
BIST debug chain port signals
-----------------------------------------------------*/
input scanb_rst; // bist scan reset
input scanb_clk; // bist scan clock
input scanb_si; // bist scan serial in
output scanb_so; // bist scan serial out
input scanb_en; // bist scan shift enable
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
 
// internal wires for serial chain connection
wire SO_internal ;
921,11 → 920,9
 
`ifdef PCI_BIST
,
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_so_internal),
.scanb_en (scanb_en)
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o_internal),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
 
1106,11 → 1103,9
 
`ifdef PCI_BIST
,
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_so_internal),
.scanb_so (scanb_so),
.scanb_en (scanb_en)
.mbist_si_i (mbist_so_o_internal),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
 
/trunk/rtl/verilog/pci_wb_slave_unit.v
42,8 → 42,11
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2003/01/27 16:49:31 mihad
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
//
// Revision 1.8 2002/10/18 03:36:37 tadejm
// Changed wrong signal name scanb_sen into scanb_en.
// Changed wrong signal name mbist_sen into mbist_ctrl_i.
//
// Revision 1.7 2002/10/17 22:49:22 tadejm
// Changed BIST signals for RAMs.
165,11 → 168,9
`ifdef PCI_BIST
,
// debug chain signals
scanb_rst, // bist scan reset
scanb_clk, // bist scan clock
scanb_si, // bist scan serial in
scanb_so, // bist scan serial out
scanb_en // bist scan shift enable
mbist_si_i, // bist scan serial in
mbist_so_o, // bist scan serial out
mbist_ctrl_i // bist chain shift control
`endif
);
 
276,11 → 277,9
/*-----------------------------------------------------
BIST debug chain port signals
-----------------------------------------------------*/
input scanb_rst; // bist scan reset
input scanb_clk; // bist scan clock
input scanb_si; // bist scan serial in
output scanb_so; // bist scan serial out
input scanb_en; // bist scan shift enable
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`endif
 
// pci master interface outputs
584,11 → 583,9
 
`ifdef PCI_BIST
,
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_so),
.scanb_en (scanb_en)
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
) ;
 
/trunk/rtl/verilog/top.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.11 2003/08/21 20:49:03 tadejm
// Added signals for WB Master B3.
//
// Revision 1.10 2003/08/03 18:05:06 mihad
// Added limited WISHBONE B3 support for WISHBONE Slave Unit.
// Doesn't support full speed bursts yet.
50,7 → 53,7
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
//
// Revision 1.8 2002/10/18 03:36:37 tadejm
// Changed wrong signal name scanb_sen into scanb_en.
// Changed wrong signal name mbist_sen into mbist_ctrl_i.
//
// Revision 1.7 2002/10/17 22:49:22 tadejm
// Changed BIST signals for RAMs.
140,11 → 143,9
`ifdef PCI_BIST
,
// debug chain signals
scanb_rst, // bist scan reset
scanb_clk, // bist scan clock
scanb_si, // bist scan serial in
scanb_so, // bist scan serial out
scanb_en // bist scan shift enable
mbist_si_i, // bist scan serial in
mbist_so_o, // bist scan serial out
mbist_ctrl_i // bist chain shift control
`endif
);
 
205,11 → 206,9
/*-----------------------------------------------------
BIST debug chain port signals
-----------------------------------------------------*/
input scanb_rst; // bist scan reset
input scanb_clk; // bist scan clock
input scanb_si; // bist scan serial in
output scanb_so; // bist scan serial out
input scanb_en; // bist scan shift enable
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`endif
 
wire [31:0] AD_out ;
376,11 → 375,9
 
`ifdef PCI_BIST
,
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_so),
.scanb_en (scanb_en)
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
/trunk/rtl/verilog/pci_wb_tpram.v
62,11 → 62,14
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2003/08/14 13:06:03 simons
// synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated.
//
// Revision 1.1 2003/01/27 16:49:31 mihad
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
//
// Revision 1.7 2002/10/18 03:36:37 tadejm
// Changed wrong signal name scanb_sen into scanb_en.
// Changed wrong signal name mbist_sen into mbist_ctrl_i.
//
// Revision 1.6 2002/10/17 22:49:22 tadejm
// Changed BIST signals for RAMs.
115,11 → 118,9
`ifdef PCI_BIST
,
// debug chain signals
scanb_rst, // bist scan reset
scanb_clk, // bist scan clock
scanb_si, // bist scan serial in
scanb_so, // bist scan serial out
scanb_en // bist scan shift enable
mbist_si_i, // bist scan serial in
mbist_so_o, // bist scan serial out
mbist_ctrl_i // bist chain shift control
`endif
);
 
151,11 → 152,9
 
`ifdef PCI_BIST
// debug chain signals
input scanb_rst; // bist scan reset
input scanb_clk; // bist scan clock
input scanb_si; // bist scan serial in
output scanb_so; // bist scan serial out
input scanb_en; // bist scan shift enable
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`endif
 
//
181,11 → 180,9
`ifdef PCI_BIST
,
// debug chain signals
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_so),
.scanb_en (scanb_en)
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
216,11 → 213,9
.AB(addr_b),
.DB(di_b),
.OENB(~oe_b),
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_so),
.scanb_en (scanb_en)
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
);
`else
art_hsdp_64x40 /*#(dw, 1<<aw, aw) */ artisan_sdp
/trunk/rtl/verilog/pci_pci_tpram.v
62,11 → 62,14
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2003/08/14 13:06:03 simons
// synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated.
//
// Revision 1.1 2003/01/27 16:49:31 mihad
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
//
// Revision 1.7 2002/10/18 03:36:37 tadejm
// Changed wrong signal name scanb_sen into scanb_en.
// Changed wrong signal name mbist_sen into mbist_ctrl_i.
//
// Revision 1.6 2002/10/17 22:51:08 tadejm
// Changed BIST signals for RAMs.
115,11 → 118,9
`ifdef PCI_BIST
,
// debug chain signals
scanb_rst, // bist scan reset
scanb_clk, // bist scan clock
scanb_si, // bist scan serial in
scanb_so, // bist scan serial out
scanb_en // bist scan shift enable
mbist_si_i, // bist scan serial in
mbist_so_o, // bist scan serial out
mbist_ctrl_i // bist chain shift control
`endif
);
 
151,11 → 152,9
 
`ifdef PCI_BIST
// debug chain signals
input scanb_rst; // bist scan reset
input scanb_clk; // bist scan clock
input scanb_si; // bist scan serial in
output scanb_so; // bist scan serial out
input scanb_en; // bist scan shift enable
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`endif
 
//
181,11 → 180,9
`ifdef PCI_BIST
,
// debug chain signals
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_so),
.scanb_en (scanb_en)
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
 
216,11 → 213,9
.AB(addr_b),
.DB(di_b),
.OENB(~oe_b),
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_so),
.scanb_en (scanb_en)
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
);
`else
art_hsdp_64x40 /*#(dw, 1<<aw, aw) */ artisan_sdp
/trunk/rtl/verilog/pci_target_unit.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.13 2003/08/21 20:55:14 tadejm
// Corrected bug when writing to FIFO (now it is registered).
//
// Revision 1.12 2003/08/08 16:36:33 tadejm
// Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.
//
49,7 → 52,7
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
//
// Revision 1.10 2002/10/18 03:36:37 tadejm
// Changed wrong signal name scanb_sen into scanb_en.
// Changed wrong signal name mbist_sen into mbist_ctrl_i.
//
// Revision 1.9 2002/10/17 22:51:08 tadejm
// Changed BIST signals for RAMs.
181,11 → 184,9
`ifdef PCI_BIST
,
// debug chain signals
scanb_rst, // bist scan reset
scanb_clk, // bist scan clock
scanb_si, // bist scan serial in
scanb_so, // bist scan serial out
scanb_en // bist scan shift enable
mbist_si_i, // bist scan serial in
mbist_so_o, // bist scan serial out
mbist_ctrl_i // bist chain shift control
`endif
);
 
290,11 → 291,9
/*-----------------------------------------------------
BIST debug chain port signals
-----------------------------------------------------*/
input scanb_rst; // bist scan reset
input scanb_clk; // bist scan clock
input scanb_si; // bist scan serial in
output scanb_so; // bist scan serial out
input scanb_en; // bist scan shift enable
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`endif
 
 
583,11 → 582,9
 
`ifdef PCI_BIST
,
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_so),
.scanb_en (scanb_en)
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
) ;
 
/trunk/rtl/verilog/pci_wbw_wbr_fifos.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2003/08/14 13:06:03 simons
// synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated.
//
// Revision 1.3 2003/03/26 13:16:18 mihad
// Added the reset value parameter to the synchronizer flop module.
// Added resets to all synchronizer flop instances.
54,7 → 57,7
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
//
// Revision 1.9 2002/10/18 03:36:37 tadejm
// Changed wrong signal name scanb_sen into scanb_en.
// Changed wrong signal name mbist_sen into mbist_ctrl_i.
//
// Revision 1.8 2002/10/17 22:49:22 tadejm
// Changed BIST signals for RAMs.
120,11 → 123,9
`ifdef PCI_BIST
,
// debug chain signals
scanb_rst, // bist scan reset
scanb_clk, // bist scan clock
scanb_si, // bist scan serial in
scanb_so, // bist scan serial out
scanb_en // bist scan shift enable
mbist_si_i, // bist scan serial in
mbist_so_o, // bist scan serial out
mbist_ctrl_i // bist chain shift control
`endif
) ;
 
230,11 → 231,9
/*-----------------------------------------------------
BIST debug chain port signals
-----------------------------------------------------*/
input scanb_rst; // bist scan reset
input scanb_clk; // bist scan clock
input scanb_si; // bist scan serial in
output scanb_so; // bist scan serial out
input scanb_en; // bist scan shift enable
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`endif
 
/*-----------------------------------------------------------------------------------------------------------
350,8 → 349,8
wire wbr_read_enable = 1'b1 ;
 
`ifdef PCI_BIST
wire scanb_so_internal ; // wires for connection of debug ports on two rams
wire scanb_si_internal = scanb_so_internal ;
wire mbist_so_o_internal ; // wires for connection of debug ports on two rams
wire mbist_si_i_internal = mbist_so_o_internal ;
`endif
 
// instantiate and connect two generic rams - one for wishbone write fifo and one for wishbone read fifo
378,11 → 377,9
 
`ifdef PCI_BIST
,
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_so_internal),
.scanb_en (scanb_en)
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o_internal),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
 
409,11 → 406,9
 
`ifdef PCI_BIST
,
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si_internal),
.scanb_so (scanb_so),
.scanb_en (scanb_en)
.mbist_si_i (mbist_si_i_internal),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
 
472,11 → 467,9
 
`ifdef PCI_BIST
,
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_so),
.scanb_en (scanb_en)
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
 
/trunk/rtl/verilog/pci_pciw_pcir_fifos.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2003/08/14 13:06:03 simons
// synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated.
//
// Revision 1.4 2003/08/08 16:36:33 tadejm
// Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.
//
57,7 → 60,7
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
//
// Revision 1.10 2002/10/18 03:36:37 tadejm
// Changed wrong signal name scanb_sen into scanb_en.
// Changed wrong signal name mbist_sen into mbist_ctrl_i.
//
// Revision 1.9 2002/10/17 22:51:08 tadejm
// Changed BIST signals for RAMs.
132,11 → 135,9
`ifdef PCI_BIST
,
// debug chain signals
scanb_rst, // bist scan reset
scanb_clk, // bist scan clock
scanb_si, // bist scan serial in
scanb_so, // bist scan serial out
scanb_en // bist scan shift enable
mbist_si_i, // bist scan serial in
mbist_so_o, // bist scan serial out
mbist_ctrl_i // bist chain shift control
`endif
) ;
 
253,11 → 254,9
/*-----------------------------------------------------
BIST debug chain port signals
-----------------------------------------------------*/
input scanb_rst; // bist scan reset
input scanb_clk; // bist scan clock
input scanb_si; // bist scan serial in
output scanb_so; // bist scan serial out
input scanb_en; // bist scan shift enable
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`endif
 
/*-----------------------------------------------------------------------------------------------------------
381,8 → 380,8
wire pcir_read_enable = 1'b1 ;
 
`ifdef PCI_BIST
wire scanb_so_internal ; // wires for connection of debug ports on two rams
wire scanb_si_internal = scanb_so_internal ;
wire mbist_so_o_internal ; // wires for connection of debug ports on two rams
wire mbist_si_i_internal = mbist_so_o_internal ;
`endif
 
// instantiate and connect two generic rams - one for pci write fifo and one for pci read fifo
409,11 → 408,9
 
`ifdef PCI_BIST
,
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_so_internal),
.scanb_en (scanb_en)
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o_internal),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
 
440,11 → 437,9
 
`ifdef PCI_BIST
,
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si_internal),
.scanb_so (scanb_so),
.scanb_en (scanb_en)
.mbist_si_i (mbist_si_i_internal),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
 
503,11 → 498,9
 
`ifdef PCI_BIST
,
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_so),
.scanb_en (scanb_en)
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
 
/trunk/apps/test/rtl/verilog/pci_bridge32.v
43,6 → 43,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2003/06/12 02:55:26 mihad
// Added a test application!
//
// Revision 1.9 2003/01/27 16:49:31 mihad
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
//
50,7 → 53,7
// Changed BIST signal names etc..
//
// Revision 1.7 2002/10/18 03:36:37 tadejm
// Changed wrong signal name scanb_sen into scanb_en.
// Changed wrong signal name mbist_sen into mbist_ctrl_i.
//
// Revision 1.6 2002/10/17 22:51:50 tadejm
// Changed BIST signals for RAMs.
187,11 → 190,9
`ifdef PCI_BIST
,
// debug chain signals
scanb_rst, // bist scan reset
scanb_clk, // bist scan clock
scanb_si, // bist scan serial in
scanb_so, // bist scan serial out
scanb_en // bist scan shift enable
mbist_si_i, // bist scan serial in
mbist_so_o, // bist scan serial out
mbist_ctrl_i // bist chain shift control
`endif
);
 
300,11 → 301,9
/*-----------------------------------------------------
BIST debug chain port signals
-----------------------------------------------------*/
input scanb_rst; // bist scan reset
input scanb_clk; // bist scan clock
input scanb_si; // bist scan serial in
output scanb_so; // bist scan serial out
input scanb_en; // bist scan shift enable
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
 
// internal wires for serial chain connection
wire SO_internal ;
824,11 → 823,9
 
`ifdef PCI_BIST
,
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_so_internal),
.scanb_en (scanb_en)
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o_internal),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
 
1006,11 → 1003,9
 
`ifdef PCI_BIST
,
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_so_internal),
.scanb_so (scanb_so),
.scanb_en (scanb_en)
.mbist_si_i (mbist_so_o_internal),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
 

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