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https://opencores.org/ocsvn/can/can/trunk
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- from Rev 123 to Rev 124
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Rev 123 → Rev 124
/trunk/rtl/verilog/can_defines.v
50,6 → 50,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.10 2003/08/14 16:04:52 simons |
// Artisan ram instances added. |
// |
// Revision 1.9 2003/06/27 20:56:15 simons |
// Virtual silicon ram instances added. |
// |
90,6 → 93,9
// Uncomment following line if you want to use CAN in Actel APA devices (embedded memory used) |
`define ACTEL_APA_RAM |
|
// Uncomment following line if you want to use CAN in Altera devices (embedded memory used) |
// `define ALTERA_RAM |
|
// Uncomment following line if you want to use CAN in Xilinx devices (embedded memory used) |
// `define XILINX_RAM |
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/trunk/rtl/verilog/can_fifo.v
50,6 → 50,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.22 2003/08/20 09:59:16 mohor |
// Artisan RAM fixed (when not using BIST). |
// |
// Revision 1.21 2003/08/14 16:04:52 simons |
// Artisan ram instances added. |
// |
182,6 → 185,8
wire scanb_s_0; |
`endif |
|
`ifdef ALTERA_RAM |
`else |
`ifdef ACTEL_APA_RAM |
`else |
`ifdef XILINX_RAM |
199,6 → 204,7
`endif |
`endif |
`endif |
`endif |
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reg [5:0] rd_pointer; |
reg [5:0] wr_pointer; |
363,6 → 369,55
end |
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`ifdef ALTERA_RAM |
// altera_ram_64x8_sync fifo |
lpm_ram_dp fifo |
( |
.q (data_out), |
.rdclock (clk), |
.wrclock (clk), |
.data (data_in), |
.wren (~(wr & (~fifo_full))), |
.rden (~fifo_selected), |
.wraddress (wr_pointer), |
.rdaddress (read_address) |
); |
defparam fifo.lpm_width = 8; |
defparam fifo.lpm_widthad = 6; |
|
|
// altera_ram_64x4_sync info_fifo |
lpm_ram_dp info_fifo |
( |
.q (length_info), |
.rdclock (clk), |
.wrclock (clk), |
.data (len_cnt & {4{~initialize_memories}}), |
.wren (~(write_length_info & (~info_full) | initialize_memories)), |
.rden (1'b0), // always enabled |
.wraddress (wr_info_pointer), |
.rdaddress (rd_info_pointer) |
); |
defparam info_fifo.lpm_width = 4; |
defparam info_fifo.lpm_widthad = 6; |
|
|
// altera_ram_64x1_sync overrun_fifo |
lpm_ram_dp overrun_fifo |
( |
.q (overrun), |
.rdclock (clk), |
.wrclock (clk), |
.data ((latch_overrun | (wr & fifo_full)) & (~initialize_memories)), |
.wren (~(write_length_info & (~info_full) | initialize_memories)), |
.rden (1'b0), // always enabled |
.wraddress (wr_info_pointer), |
.rdaddress (rd_info_pointer) |
); |
defparam overrun_fifo.lpm_width = 1; |
defparam overrun_fifo.lpm_widthad = 6; |
|
`else |
`ifdef ACTEL_APA_RAM |
actel_ram_64x8_sync fifo |
( |
690,6 → 745,7
`endif |
`endif |
`endif |
`endif |
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