OpenCores
URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

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Rev 123 → Rev 124

/sdhc-sc-core/trunk/src/grpSd/unitSdTop/Files.tcl
0,0 → 1,28
set pkgs {Global Global
Sd Sd
Crc CRCs
Rs232 Rs232
Components Ics307Values
Wishbone Wishbone
Sd SdWb
}
 
set units {Crc Crc {Rtl}
Sd SdCmd {Rtl}
StrobesClocks Counter {Rtl}
Sd SdController {Rtl}
Sd SdData {Rtl}
Cyclone2 CycSimpleDualPortedRam {Syn}
Memory SimpleDualPortedRam {Rtl}
Memory SinglePortedRam {Rtl}
StrobesClocks StrobeGen {Rtl}
Sd SdWbSlave {Rtl}
Sd SdClockMaster {Rtl}
Sd SdCardSynchronizer {Rtl}
Synchronization Synchronizer {Rtl}
StrobesClocks EdgeDetector {Rtl}
Sd SdWbSdControllerSync {Rtl}
Cyclone2 WriteDataFifo {Syn}
Sd SdTop {Rtl}}
 
 
sdhc-sc-core/trunk/src/grpSd/unitSdTop/Files.tcl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: sdhc-sc-core/trunk/src/grpSd/unitSdTop/src/SdTop-Rtl-ea.vhdl =================================================================== --- sdhc-sc-core/trunk/src/grpSd/unitSdTop/src/SdTop-Rtl-ea.vhdl (revision 123) +++ sdhc-sc-core/trunk/src/grpSd/unitSdTop/src/SdTop-Rtl-ea.vhdl (revision 124) @@ -80,7 +80,8 @@ signal WriteFifoToSdWbSlave : aiWriteFifo; signal iReadFifo : aiReadFifo; signal oReadFifo : aoReadFifo; - signal ReadFifoQTemp : std_logic_vector(31 downto 0); + signal ReadFifoQTemp : std_logic_vector(31 downto 0); + signal DisableSdClk : std_ulogic; begin @@ -187,7 +188,8 @@ iData => iData, oData => oData, oReadFifo => oReadFifo, - iReadFifo => iReadFifo + iReadFifo => iReadFifo, + oDisableSdClk => DisableSdClk ); DataRam_inst: entity work.SimpleDualPortedRam @@ -213,6 +215,7 @@ iClk => iSdClk, iRstSync => iRstSync, iHighSpeed => HighSpeed, + iDisable => DisableSdClk, oSdStrobe => SdStrobe, oSdCardClk => oSClk );
/sdhc-sc-core/trunk/src/grpSd/unitSdTop/syn/SdTopsyn.tcl
15,72 → 15,47
# Quartus II: Generate Tcl File for Project
# File: SdCmdsyn.tcl
# Generated on: Wed Jun 23 17:07:05 2010
 
# Load Quartus II Tcl Project package
package require ::quartus::project
package require ::quartus::flow
 
set need_to_close_project 0
set make_assignments 1
project_new TbdSdsyn -revision TbdSdSyn -overwrite
 
# Check that the right project is open
if {[is_project_open]} {
if {[string compare $quartus(project) "SdTopsyn"]} {
puts "Project SdTopsyn is not open"
set make_assignments 0
}
} else {
# Only open if not already open
if {[project_exists SdTopsyn]} {
project_open -revision SdTopsyn SdTopsyn
} else {
project_new -revision SdTopsyn SdTopsyn
}
set need_to_close_project 1
}
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C35F484C8
set_global_assignment -name TOP_LEVEL_ENTITY SdTop
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
 
# Make assignments
if {$make_assignments} {
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C35F484C8
set_global_assignment -name TOP_LEVEL_ENTITY SdTop
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.1 SP2"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:01:43 APRIL 16, 2010"
set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP2"
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name VHDL_FILE "../../../grpGlobal/pkgGlobal/src/Global-p.vhdl"
set_global_assignment -name VHDL_FILE "../../../grpSd/pkgSd/src/Sd-p.vhdl"
set_global_assignment -name VHDL_FILE "../../../grpCrc/pkgCRCs/src/CRCs-p.vhdl"
set_global_assignment -name VHDL_FILE "../../../grpCrc/unitCrc/src/Crc-Rtl-ea.vhdl"
set_global_assignment -name VHDL_FILE "../../../grpSd/unitSdCmd/src/SdCmd-Rtl-ea.vhdl"
set_global_assignment -name VHDL_FILE "../../../grpSd/unitSdController/src/SdController-Rtl-ea.vhdl"
set_global_assignment -name VHDL_FILE "../../../grpSd/unitSdTop/src/SdTop-Rtl-ea.vhdl"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name FMAX_REQUIREMENT "100 MHz" -section_id Clock
set_global_assignment -name ENABLE_DRC_SETTINGS OFF
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
set_instance_assignment -name CLOCK_SETTINGS Clock -to iClk
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
source ../Files.tcl
source ../../../syn/syn.tcl
 
# Commit assignments
export_assignments
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name FMAX_REQUIREMENT "100 MHz" -section_id Clock
set_global_assignment -name ENABLE_DRC_SETTINGS OFF
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
 
# Compile project
if {[catch {execute_flow -compile} result]} {
puts "\nResult: $result\n"
puts "ERROR: Compilation failed. See report files.\n"
} else {
puts "\nINFO: Compilation was successful.\n"
}
# Generate RBF
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
 
# Close project
if {$need_to_close_project} {
project_close
}
source ../Pins.tcl
 
set_instance_assignment -name CLOCK_SETTINGS Clock -to iWbClk
set_instance_assignment -name CLOCK_SETTINGS Clock -to iSdClk
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 
# Commit assignments
export_assignments
 
# Compile project
if {[catch {execute_flow -compile} result]} {
puts "\nResult: $result\n"
puts "ERROR: Compilation failed. See report files.\n"
} else {
puts "\nINFO: Compilation was successful.\n"
}
 
project_close
 
/sdhc-sc-core/trunk/src/grpSd/unitSdTop/Pins.tcl
0,0 → 1,123
# Pin & Location Assignments
# Signal Pin Pullup
set pins {
iClk A12 0
inResetAsync Y20 1
ioCmd A8 1
ioData[0] A9 1
ioData[1] D6 1
ioData[2] C14 1
ioData[3] B8 1
oSclk B9 0
oIcs307Sclk C10 0
oIcs307Data C9 0
oIcs307Strobe E9 0
oLedBank[0] Y6 0
oLedBank[1] W5 0
oLedBank[2] Y5 0
oLedBank[3] Y7 0
oLedBank[4] V8 0
oLedBank[5] W8 0
oLedBank[6] Y9 0
oLedBank[7] W7 0
oDigitAdr[3] Y3 0
oDigitAdr[2] Y4 0
oDigitAdr[1] W4 0
oTx B5 0
}
 
# Set according to pins
source ../../../syn/pins.tcl
 
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
 
# #set_location_assignment PIN_B20 -to AVRAD[0]
# #set_location_assignment PIN_A20 -to AVRAD[1]
# #set_location_assignment PIN_B19 -to AVRAD[2]
# #set_location_assignment PIN_A19 -to AVRAD[3]
# #set_location_assignment PIN_B18 -to AVRAD[4]
# #set_location_assignment PIN_A18 -to AVRAD[5]
# #set_location_assignment PIN_B17 -to AVRAD[6]
# #set_location_assignment PIN_A17 -to AVRAD[7]
# #set_location_assignment PIN_A11 -to AVRADR[8]
# #set_location_assignment PIN_A13 -to AVRADR[9]
# #set_location_assignment PIN_B13 -to AVRADR[10]
# #set_location_assignment PIN_A14 -to AVRADR[11]
# #set_location_assignment PIN_B14 -to AVRADR[12]
# #set_location_assignment PIN_A15 -to AVRADR[13]
# #set_location_assignment PIN_B15 -to AVRADR[14]
# #set_location_assignment PIN_A16 -to AVRADR[15]
# #set_location_assignment PIN_B16 -to AVRALE
# #set_location_assignment PIN_E15 -to AVRIRQ
# #set_location_assignment PIN_B11 -to AVRRD
# #set_location_assignment PIN_A10 -to AVRWR
# #set_location_assignment PIN_C21 -to BCLK
# #set_location_assignment PIN_D22 -to DIN
# #set_location_assignment PIN_E22 -to DOUT
# #set_location_assignment PIN_D21 -to LRCIN
# #set_location_assignment PIN_E21 -to LRCOUT
# #set_location_assignment PIN_E19 -to MCLK
# set_location_assignment PIN_A12 -to iClk
# #set_location_assignment PIN_AB11 -to iClk
# #set_location_assignment PIN_C22 -to CS
# set_location_assignment PIN_AB5 -to inKey1
# set_location_assignment PIN_AA5 -to inKey2
# set_location_assignment PIN_AB4 -to inKey3
# set_location_assignment PIN_AA4 -to inKey4
# set_location_assignment PIN_AB3 -to inKey5
# set_location_assignment PIN_AA3 -to inKey6
# set_location_assignment PIN_Y6 -to oSeg0
# set_location_assignment PIN_W5 -to oSeg1
# set_location_assignment PIN_Y5 -to oSeg2
# set_location_assignment PIN_Y7 -to oSeg3
# set_location_assignment PIN_V8 -to oSeg4
# set_location_assignment PIN_W8 -to oSeg5
# set_location_assignment PIN_Y9 -to oSeg6
# set_location_assignment PIN_W7 -to oSeg7
# set_location_assignment PIN_W4 -to oDIGIT_ADR_A
# set_location_assignment PIN_Y4 -to oDIGIT_ADR_B
# set_location_assignment PIN_Y3 -to oDIGIT_ADR_C
# #set_location_assignment PIN_B4 -to Txd232
# set_location_assignment PIN_Y20 -to inResetAsync
# #set_location_assignment PIN_D5 -to Ps2Clk1
# #set_location_assignment PIN_E7 -to Ps2Clk2
# #set_location_assignment PIN_D4 -to Ps2Dat1
# #set_location_assignment PIN_C4 -to Ps2Dat2
# #set_location_assignment PIN_A4 -to Rxd232
# #set_location_assignment PIN_W14 -to VgaBl0
# #set_location_assignment PIN_Y14 -to VgaBl1
# #set_location_assignment PIN_Y16 -to VgaGr0
# #set_location_assignment PIN_W15 -to VgaGr1
# #set_location_assignment PIN_V14 -to VgaHsync
# #set_location_assignment PIN_Y17 -to VgaRd0
# #set_location_assignment PIN_W16 -to VgaRd1
# #set_location_assignment PIN_AA6 -to VgaVsync
# #set_location_assignment PIN_C19 -to SCLK
# #set_location_assignment PIN_C20 -to SDIN
# #set_location_assignment PIN_AB7 -to mcoll_pad_i
# #set_location_assignment PIN_AA7 -to mcrs_pad_i
# #set_location_assignment PIN_W12 -to mrx_clk_pad_i
# #set_location_assignment PIN_AA14 -to mrxd_pad_i[0]
# #set_location_assignment PIN_AB15 -to mrxd_pad_i[1]
# #set_location_assignment PIN_AA15 -to mrxd_pad_i[2]
# #set_location_assignment PIN_AB16 -to mrxd_pad_i[3]
# #set_location_assignment PIN_AB13 -to mrxdv_pad_i
# #set_location_assignment PIN_AA13 -to mrxerr_pad_i
# #set_location_assignment PIN_V12 -to mtx_clk_pad_i
# #set_location_assignment PIN_AB9 -to mtxd_pad_o[0]
# #set_location_assignment PIN_AA9 -to mtxd_pad_o[1]
# #set_location_assignment PIN_AB8 -to mtxd_pad_o[2]
# #set_location_assignment PIN_AA8 -to mtxd_pad_o[3]
# #set_location_assignment PIN_AB12 -to mtxen_pad_o
# #set_location_assignment PIN_AB14 -to mtxerr_pad_o
# #set_location_assignment PIN_AB6 -to ETH_Reset_o
# #set_location_assignment PIN_AB17 -to md_io
# #set_location_assignment PIN_AA16 -to mdc_o
#
# set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to inKey1
# set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to inKey2
# set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to inKey3
# set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to inKey4
# set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to inKey5
# set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to inKey6
# set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to
sdhc-sc-core/trunk/src/grpSd/unitSdTop/Pins.tcl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: sdhc-sc-core/trunk/src/grpSd/unitSdClockMaster/src/SdClockMaster-Rtl-a.vhdl =================================================================== --- sdhc-sc-core/trunk/src/grpSd/unitSdClockMaster/src/SdClockMaster-Rtl-a.vhdl (revision 123) +++ sdhc-sc-core/trunk/src/grpSd/unitSdClockMaster/src/SdClockMaster-Rtl-a.vhdl (revision 124) @@ -27,33 +27,63 @@ Counter <= 0; SdClk <= cInactivated; else + if (iDisable = cActivated) then + SdClk <= cActivated; + else - if (iHighSpeed = cActivated) then - if (Counter = 0 or Counter = 2) then - SdClk <= cActivated; + if (iHighSpeed = cActivated) then + if (Counter = 0 or Counter = 2) then + SdClk <= cActivated; + else + SdClk <= cInactivated; + end if; else - SdClk <= cInactivated; + if (Counter = 0 or Counter = 1) then + SdClk <= cActivated; + else + SdClk <= cInactivated; + end if; end if; - else - if (Counter = 0 or Counter = 1) then - SdClk <= cActivated; - else - SdClk <= cInactivated; + + if (Counter < 3) then + Counter <= Counter + 1; + else + Counter <= 0; end if; end if; + end if; + end if; + end process ClkDivider; - if (Counter < 3) then - Counter <= Counter + 1; - else - Counter <= 0; + + RegSdStrobe : process (iClk, iRstSync) + begin + if (rising_edge(iClk)) then + -- synchronous reset + if (iRstSync = cActivated) then + oSdCardClk <= cInactivated; + oSdStrobe <= cInactivated; + else + + if (iDisable = cActivated) then + oSdCardClk <= cInactivated; + oSdStrobe <= cInactivated; + + else + + oSdCardClk <= not SdClk; + + if (iHighSpeed = cInactivated) then + oSdStrobe <= SdStrobe25MHz; + else + oSdStrobe <= SdStrobe50MHz; + end if; + end if; end if; end if; - end process ClkDivider; + end process RegSdStrobe; - oSdCardClk <= not SdClk; - oSdStrobe <= SdStrobe25MHz when iHighSpeed = cInactivated else SdStrobe50MHz; - SdStrobe_inst25: entity work.StrobeGen(Rtl) generic map ( gClkFrequency => gClkFrequency,
/sdhc-sc-core/trunk/src/grpSd/unitSdClockMaster/src/SdClockMaster-e.vhdl
21,6 → 21,7
iClk : in std_ulogic;
iRstSync : in std_ulogic;
iHighSpeed : in std_ulogic;
iDisable : in std_ulogic;
oSdStrobe : out std_ulogic;
oSdCardClk : out std_ulogic
);
/sdhc-sc-core/trunk/src/grpSd/unitSdData/src/SdData-Rtl-a.vhdl
25,12 → 25,12
WordCounter : aWordCounter;
FirstSend : std_ulogic;
Data : aoSdData;
Enable : std_ulogic;
Controller : aSdDataToController;
Ram : aSdDataToRam;
ReadFifo : aoReadFifo;
Mode : aSdDataBusMode;
Word : aWord;
DisableSdClk : std_ulogic;
end record aReg;
 
constant cDefaultReg : aReg := (
41,12 → 41,12
ByteCounter => to_unsigned(7, aByteCounter'length),
FirstSend => cInactivated,
Data => (Data => "0000", En => "0000"),
Enable => cInactivated,
Controller => cDefaultSdDataToController,
Ram => cDefaultSdDataToRam,
ReadFifo => cDefaultoReadFifo,
Mode => standard,
Word => (others => '0'));
Word => (others => '0'),
DisableSdClk => cInactivated);
 
type aCrcOut is record
Clear : std_ulogic;
82,6 → 82,7
oSdDataToController <= R.Controller;
oSdDataToRam <= R.Ram;
oReadFifo <= R.ReadFifo;
oDisableSdClk <= R.DisableSdClk;
 
Regs : process (iClk, inResetAsync)
begin
91,11 → 92,12
if (iStrobe = cActivated) then
R <= NextR;
end if;
R.ReadFifo.rdreq <= NextR.ReadFifo.rdreq and not iStrobe;
R.ReadFifo.rdreq <= NextR.ReadFifo.rdreq and iStrobe;
R.DisableSdClk <= NextR.DisableSdClk;
end if;
end process Regs;
 
Comb : process (iData.Data, iSdDataFromController, CrcIn, iStrobe, iReadFifo, R)
Comb : process (iData.Data, iSdDataFromController, CrcIn, iReadFifo, R)
 
procedure ShiftIntoCrc (constant data : in std_ulogic_vector(3 downto 0)) is
begin
183,7 → 185,7
 
begin
NextR <= R;
NextR.Enable <= cInactivated;
NextR.Data.En <= (others => cInactivated);
NextR.Controller <= cDefaultSdDataToController;
NextR.Ram.We <= cInactivated;
NextR.Ram.En <= cInactivated;
221,11 → 223,14
case iReadFifo.rdempty is
when cActivated =>
report "Fifo empty, waiting for data" severity note;
NextR.DisableSdClk <= cActivated;
 
when cInactivated =>
NextR.State <= send;
NextR.Region <= startbit;
NextR.ReadFifo.rdreq <= cActivated;
NextR.DisableSdClk <= cInactivated;
NextR.WordCounter <= to_unsigned(0, aWordCounter'length);
 
when others =>
report "rdempty invalid" severity error;
262,12 → 267,6
end loop;
SendBitAndShiftIntoCrc(temp);
 
if (R.ByteCounter = 7 and R.WordCounter = 3 and R.BlockCounter < 127 and R.BlockCounter > 0) then
-- TODO: handle rdempty
-- request new data from fifo
NextR.ReadFifo.rdreq <= cActivated;
end if;
 
if (R.ByteCounter = 3) then
NextR.ByteCounter <= to_unsigned(7, aByteCounter'length);
 
293,14 → 292,34
NextR.ByteCounter <= R.ByteCounter - 4;
end if;
 
if ((R.ByteCounter = 7 and R.WordCounter = 3 and R.BlockCounter < 127)) then
-- handle rdempty
if (iReadFifo.rdempty = cActivated) then
report "No data available, fifo empty, waiting for new data" severity note;
NextR.DisableSdClk <= cActivated;
NextR.ByteCounter <= R.ByteCounter;
 
else
-- request new data from fifo
NextR.DisableSdClk <= cInactivated;
NextR.ReadFifo.rdreq <= cActivated;
end if;
end if;
 
 
when standard =>
temp := "111" & R.Word(CalcBitAddrInWord(R.WordCounter, R.ByteCounter));
SendBitAndShiftIntoCrc(temp);
 
if (R.ByteCounter = 1 and R.WordCounter = 3 and R.BlockCounter < 127 and R.BlockCounter > 0) then
if (R.ByteCounter = 1 and R.WordCounter = 3 and R.BlockCounter < 127) then
-- TODO: handle rdempty
-- request new data from fifo
NextR.ReadFifo.rdreq <= cActivated;
if (iReadFifo.rdempty = cActivated) then
report "No data available, fifo empty, waiting for new data" severity note;
 
else
-- request new data from fifo
NextR.ReadFifo.rdreq <= cActivated;
end if;
end if;
 
if (R.ByteCounter = 0) then
336,8 → 355,9
NextR.Data.Data <= CrcIn.Serial;
 
if (R.BlockCounter = 15) then
NextR.BlockCounter <= to_unsigned(0, aBlockCounter'length);
NextR.Region <= endbit;
NextR.BlockCounter <= to_unsigned(0, aBlockCounter'length);
NextR.Region <= endbit;
NextR.Controller.Ack <= cActivated;
 
else
NextR.BlockCounter <= R.BlockCounter + 1;
344,7 → 364,6
end if;
 
when endbit =>
NextR.Controller.Ack <= cActivated;
NextR.Data.Data <= cSdEndBits;
NextR.State <= idle;
 
/sdhc-sc-core/trunk/src/grpSd/unitSdData/src/SdData-e.vhdl
35,7 → 35,9
-- ReadFifo
iReadFifo : in aiReadFifo;
oReadFifo : out aoReadFifo
oReadFifo : out aoReadFifo;
 
oDisableSdClk : out std_ulogic
);
end entity SdData;
 
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/Files.tcl
14,6 → 14,7
StrobesClocks Counter {Rtl}
Sd SdController {Rtl}
Sd SdData {Rtl}
Cyclone2 CycSimpleDualPortedRam {Syn}
Memory SimpleDualPortedRam {Rtl}
Memory SinglePortedRam {Rtl}
StrobesClocks StrobeGen {Rtl}
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/src/SdVerificationTestbench.sv
48,17 → 48,6
 
begin // driver for SdCardModel
card.init();
 
Bus.Write('b100, 'h00000001);
Bus.Write('b100, 'h00000002);
Bus.Write('b100, 'h00000003);
Bus.Write('b100, 'h00000004);
Bus.Write('b100, 'h00000005);
Bus.Write('b100, 'h00000006);
Bus.Write('b100, 'h00000007);
Bus.Write('b100, 'h00000008);
Bus.Write('b001, 'h00000001);
Bus.Write('b000, 'h00000010);
card.write();
 
/*for (int i = 0; i < `cCmdCount; i++) begin
69,6 → 58,25
end*/
end
 
begin // driver for wishbone interface
@$root.Testbed.InitDone;
 
Bus.Write('b100, 'h01010101);
Bus.Write('b100, 'h02020202);
Bus.Write('b100, 'h03030303);
Bus.Write('b100, 'h04040404);
Bus.Write('b100, 'h05050505);
Bus.Write('b100, 'h06060606);
Bus.Write('b100, 'h07070707);
Bus.Write('b100, 'h08080808);
Bus.Write('b001, 'h00000001);
Bus.Write('b000, 'h00000010);
 
#10000;
Bus.Write('b100, 'h09090909);
 
end
 
begin // checker
@$root.Testbed.InitDone;
/*
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/wave.do
57,7 → 57,7
add wave -noupdate -format Literal /Testbed/top/sddata_inst/crcin
add wave -noupdate -format Literal /Testbed/top/sddata_inst/crcout
add wave -noupdate -format Literal /Testbed/top/sddata_inst/crcdatain
add wave -noupdate -format Literal /Testbed/top/sddata_inst/r
add wave -noupdate -format Literal -expand /Testbed/top/sddata_inst/r
add wave -noupdate -format Literal /Testbed/top/sddata_inst/nextr
add wave -noupdate -divider fifo
add wave -noupdate -format Literal -radix unsigned /Testbed/top/writedatafifo_inst/data
69,7 → 69,7
add wave -noupdate -format Logic /Testbed/top/writedatafifo_inst/rdempty
add wave -noupdate -format Logic /Testbed/top/writedatafifo_inst/wrfull
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {10084823 ns} 0}
WaveRestoreCursors {{Cursor 1} {7675026 ns} 0} {{Cursor 2} {10084945 ns} 0} {{Cursor 3} {10085095 ns} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
84,4 → 84,4
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {10084721 ns} {10085176 ns}
WaveRestoreZoom {10084910 ns} {10085169 ns}
/sdhc-sc-core/trunk/src/grpSd/unitSdController/src/SdController-Rtl-a.vhdl
765,7 → 765,8
NextR.ToSdData.Valid <= cActivated;
 
if (iSdData.Ack = cActivated) then
NextR.Region <= NextRegion;
NextR.ToSdData.Valid <= cInactivated;
NextR.Region <= NextRegion;
end if;
 
when checkbusy =>
/sdhc-sc-core/trunk/src/grpMemory/unitSimpleDualPortedRam/src/SimpleDualPortedRam-Rtl-a.vhdl
9,27 → 9,25
 
architecture Rtl of SimpleDualPortedRam is
 
subtype aWord is std_ulogic_vector(gDataWidth - 1 downto 0);
type aMemory is array (0 to 2**gAddrWidth - 1) of aWord;
signal tempq : std_logic_vector(31 downto 0);
signal rdaddr, wraddr : unsigned(6 downto 0);
 
signal memory : aMemory := (others => (others => '0'));
 
begin
 
DualPort : process (iClk)
begin
if (iClk'event and iClk = '1') then
if (iWeRW = '1') then
memory(iAddrRW) <= iDataRW;
Ram_inst: ENTITY work.CycSimpleDualPortedRam
PORT map
(
clock => iClk,
data => std_logic_vector(iDataRw),
rdaddress => std_logic_vector(rdaddr),
wraddress => std_logic_vector(wraddr),
wren => iWeRW,
q => tempq
);
 
oDataRW <= iDataRW;
else
oDataRW <= memory(iAddrRW);
end if;
 
oDataR <= memory(iAddrR);
end if;
end process DualPort;
oDataR <= std_ulogic_vector(tempq);
rdaddr <= to_unsigned(iAddrR, rdaddr'length);
wraddr <= to_unsigned(iAddrRW, wraddr'length);
end architecture Rtl;
 
/sdhc-sc-core/trunk/src/grpCyclone2/unitCycSimpleDualPortedRam/src/CycSimpleDualPortedRam-Syn-ea.vhdl
0,0 → 1,233
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
 
-- ============================================================
-- File Name: CycSimpleDualPortedRam.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
 
 
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
LIBRARY altera_mf;
USE altera_mf.all;
 
ENTITY CycSimpleDualPortedRam IS
PORT
(
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
wraddress : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END CycSimpleDualPortedRam;
 
 
ARCHITECTURE SYN OF cycsimpledualportedram IS
 
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
 
 
 
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_b : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_mixed_ports : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
 
BEGIN
q <= sub_wire0(31 DOWNTO 0);
 
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone II",
lpm_type => "altsyncram",
numwords_a => 128,
numwords_b => 128,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "OLD_DATA",
widthad_a => 7,
widthad_b => 7,
width_a => 32,
width_b => 32,
width_byteena_a => 1
)
PORT MAP (
wren_a => wren,
clock0 => clock,
address_a => wraddress,
address_b => rdaddress,
data_a => data,
q_b => sub_wire0
);
 
 
 
END SYN;
 
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "4"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "4"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "128"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "128"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "7"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "7"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
-- Retrieval info: USED_PORT: rdaddress 0 0 7 0 INPUT NODEFVAL rdaddress[6..0]
-- Retrieval info: USED_PORT: wraddress 0 0 7 0 INPUT NODEFVAL wraddress[6..0]
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND wren
-- Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
-- Retrieval info: CONNECT: @address_a 0 0 7 0 wraddress 0 0 7 0
-- Retrieval info: CONNECT: @address_b 0 0 7 0 rdaddress 0 0 7 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL CycSimpleDualPortedRam.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL CycSimpleDualPortedRam.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL CycSimpleDualPortedRam.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL CycSimpleDualPortedRam.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL CycSimpleDualPortedRam_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL CycSimpleDualPortedRam_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL CycSimpleDualPortedRam_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
sdhc-sc-core/trunk/src/grpCyclone2/unitCycSimpleDualPortedRam/src/CycSimpleDualPortedRam-Syn-ea.vhdl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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