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    from Rev 1232 to Rev 1233
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Rev 1232 → Rev 1233

/branches/branch_qmem/or1200/rtl/verilog/or1200_du.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9.4.1 2004/01/15 06:46:38 markom
// interface to debug changed; no more opselect; stb-ack protocol
//
// Revision 1.9 2003/01/22 03:23:47 lampret
// Updated sensitivity list for trace buffer [only relevant for Xilinx FPGAs]
//
166,7 → 169,7
input [aw-1:0] dbg_adr_i; // External Address Input
input [dw-1:0] dbg_dat_i; // External Data Input
output [dw-1:0] dbg_dat_o; // External Data Output
output dbg_ack_i; // External Data Acknowledge (not WB compatible)
output dbg_ack_o; // External Data Acknowledge (not WB compatible)
 
 
//
/branches/branch_qmem/or1200/rtl/verilog/or1200_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.10.4.7 2004/01/17 19:06:38 simons
// Error fixed.
//
// Revision 1.10.4.6 2004/01/17 18:39:48 simons
// Error fixed.
//
953,8 → 956,8
.dbg_we_i(dbg_we_i),
.dbg_adr_i(dbg_adr_i),
.dbg_dat_i(dbg_dat_i),
.dbg_dat_o(dbg_dat_o)
.dbg_ack_o(dbg_ack_o),
.dbg_dat_o(dbg_dat_o),
.dbg_ack_o(dbg_ack_o)
);
 
//

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